qcom-spmi-iadc.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/bitops.h>
  6. #include <linux/completion.h>
  7. #include <linux/delay.h>
  8. #include <linux/err.h>
  9. #include <linux/iio/iio.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/kernel.h>
  12. #include <linux/mutex.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/of_device.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/regmap.h>
  18. #include <linux/slab.h>
  19. /* IADC register and bit definition */
  20. #define IADC_REVISION2 0x1
  21. #define IADC_REVISION2_SUPPORTED_IADC 1
  22. #define IADC_PERPH_TYPE 0x4
  23. #define IADC_PERPH_TYPE_ADC 8
  24. #define IADC_PERPH_SUBTYPE 0x5
  25. #define IADC_PERPH_SUBTYPE_IADC 3
  26. #define IADC_STATUS1 0x8
  27. #define IADC_STATUS1_OP_MODE 4
  28. #define IADC_STATUS1_REQ_STS BIT(1)
  29. #define IADC_STATUS1_EOC BIT(0)
  30. #define IADC_STATUS1_REQ_STS_EOC_MASK 0x3
  31. #define IADC_MODE_CTL 0x40
  32. #define IADC_OP_MODE_SHIFT 3
  33. #define IADC_OP_MODE_NORMAL 0
  34. #define IADC_TRIM_EN BIT(0)
  35. #define IADC_EN_CTL1 0x46
  36. #define IADC_EN_CTL1_SET BIT(7)
  37. #define IADC_CH_SEL_CTL 0x48
  38. #define IADC_DIG_PARAM 0x50
  39. #define IADC_DIG_DEC_RATIO_SEL_SHIFT 2
  40. #define IADC_HW_SETTLE_DELAY 0x51
  41. #define IADC_CONV_REQ 0x52
  42. #define IADC_CONV_REQ_SET BIT(7)
  43. #define IADC_FAST_AVG_CTL 0x5a
  44. #define IADC_FAST_AVG_EN 0x5b
  45. #define IADC_FAST_AVG_EN_SET BIT(7)
  46. #define IADC_PERH_RESET_CTL3 0xda
  47. #define IADC_FOLLOW_WARM_RB BIT(2)
  48. #define IADC_DATA 0x60 /* 16 bits */
  49. #define IADC_SEC_ACCESS 0xd0
  50. #define IADC_SEC_ACCESS_DATA 0xa5
  51. #define IADC_NOMINAL_RSENSE 0xf4
  52. #define IADC_NOMINAL_RSENSE_SIGN_MASK BIT(7)
  53. #define IADC_REF_GAIN_MICRO_VOLTS 17857
  54. #define IADC_INT_RSENSE_DEVIATION 15625 /* nano Ohms per bit */
  55. #define IADC_INT_RSENSE_IDEAL_VALUE 10000 /* micro Ohms */
  56. #define IADC_INT_RSENSE_DEFAULT_VALUE 7800 /* micro Ohms */
  57. #define IADC_INT_RSENSE_DEFAULT_GF 9000 /* micro Ohms */
  58. #define IADC_INT_RSENSE_DEFAULT_SMIC 9700 /* micro Ohms */
  59. #define IADC_CONV_TIME_MIN_US 2000
  60. #define IADC_CONV_TIME_MAX_US 2100
  61. #define IADC_DEF_PRESCALING 0 /* 1:1 */
  62. #define IADC_DEF_DECIMATION 0 /* 512 */
  63. #define IADC_DEF_HW_SETTLE_TIME 0 /* 0 us */
  64. #define IADC_DEF_AVG_SAMPLES 0 /* 1 sample */
  65. /* IADC channel list */
  66. #define IADC_INT_RSENSE 0
  67. #define IADC_EXT_RSENSE 1
  68. #define IADC_GAIN_17P857MV 3
  69. #define IADC_EXT_OFFSET_CSP_CSN 5
  70. #define IADC_INT_OFFSET_CSP2_CSN2 6
  71. /**
  72. * struct iadc_chip - IADC Current ADC device structure.
  73. * @regmap: regmap for register read/write.
  74. * @dev: This device pointer.
  75. * @base: base offset for the ADC peripheral.
  76. * @rsense: Values of the internal and external sense resister in micro Ohms.
  77. * @poll_eoc: Poll for end of conversion instead of waiting for IRQ.
  78. * @offset: Raw offset values for the internal and external channels.
  79. * @gain: Raw gain of the channels.
  80. * @lock: ADC lock for access to the peripheral.
  81. * @complete: ADC notification after end of conversion interrupt is received.
  82. */
  83. struct iadc_chip {
  84. struct regmap *regmap;
  85. struct device *dev;
  86. u16 base;
  87. bool poll_eoc;
  88. u32 rsense[2];
  89. u16 offset[2];
  90. u16 gain;
  91. struct mutex lock;
  92. struct completion complete;
  93. };
  94. static int iadc_read(struct iadc_chip *iadc, u16 offset, u8 *data)
  95. {
  96. unsigned int val;
  97. int ret;
  98. ret = regmap_read(iadc->regmap, iadc->base + offset, &val);
  99. if (ret < 0)
  100. return ret;
  101. *data = val;
  102. return 0;
  103. }
  104. static int iadc_write(struct iadc_chip *iadc, u16 offset, u8 data)
  105. {
  106. return regmap_write(iadc->regmap, iadc->base + offset, data);
  107. }
  108. static int iadc_reset(struct iadc_chip *iadc)
  109. {
  110. u8 data;
  111. int ret;
  112. ret = iadc_write(iadc, IADC_SEC_ACCESS, IADC_SEC_ACCESS_DATA);
  113. if (ret < 0)
  114. return ret;
  115. ret = iadc_read(iadc, IADC_PERH_RESET_CTL3, &data);
  116. if (ret < 0)
  117. return ret;
  118. ret = iadc_write(iadc, IADC_SEC_ACCESS, IADC_SEC_ACCESS_DATA);
  119. if (ret < 0)
  120. return ret;
  121. data |= IADC_FOLLOW_WARM_RB;
  122. return iadc_write(iadc, IADC_PERH_RESET_CTL3, data);
  123. }
  124. static int iadc_set_state(struct iadc_chip *iadc, bool state)
  125. {
  126. return iadc_write(iadc, IADC_EN_CTL1, state ? IADC_EN_CTL1_SET : 0);
  127. }
  128. static void iadc_status_show(struct iadc_chip *iadc)
  129. {
  130. u8 mode, sta1, chan, dig, en, req;
  131. int ret;
  132. ret = iadc_read(iadc, IADC_MODE_CTL, &mode);
  133. if (ret < 0)
  134. return;
  135. ret = iadc_read(iadc, IADC_DIG_PARAM, &dig);
  136. if (ret < 0)
  137. return;
  138. ret = iadc_read(iadc, IADC_CH_SEL_CTL, &chan);
  139. if (ret < 0)
  140. return;
  141. ret = iadc_read(iadc, IADC_CONV_REQ, &req);
  142. if (ret < 0)
  143. return;
  144. ret = iadc_read(iadc, IADC_STATUS1, &sta1);
  145. if (ret < 0)
  146. return;
  147. ret = iadc_read(iadc, IADC_EN_CTL1, &en);
  148. if (ret < 0)
  149. return;
  150. dev_err(iadc->dev,
  151. "mode:%02x en:%02x chan:%02x dig:%02x req:%02x sta1:%02x\n",
  152. mode, en, chan, dig, req, sta1);
  153. }
  154. static int iadc_configure(struct iadc_chip *iadc, int channel)
  155. {
  156. u8 decim, mode;
  157. int ret;
  158. /* Mode selection */
  159. mode = (IADC_OP_MODE_NORMAL << IADC_OP_MODE_SHIFT) | IADC_TRIM_EN;
  160. ret = iadc_write(iadc, IADC_MODE_CTL, mode);
  161. if (ret < 0)
  162. return ret;
  163. /* Channel selection */
  164. ret = iadc_write(iadc, IADC_CH_SEL_CTL, channel);
  165. if (ret < 0)
  166. return ret;
  167. /* Digital parameter setup */
  168. decim = IADC_DEF_DECIMATION << IADC_DIG_DEC_RATIO_SEL_SHIFT;
  169. ret = iadc_write(iadc, IADC_DIG_PARAM, decim);
  170. if (ret < 0)
  171. return ret;
  172. /* HW settle time delay */
  173. ret = iadc_write(iadc, IADC_HW_SETTLE_DELAY, IADC_DEF_HW_SETTLE_TIME);
  174. if (ret < 0)
  175. return ret;
  176. ret = iadc_write(iadc, IADC_FAST_AVG_CTL, IADC_DEF_AVG_SAMPLES);
  177. if (ret < 0)
  178. return ret;
  179. if (IADC_DEF_AVG_SAMPLES)
  180. ret = iadc_write(iadc, IADC_FAST_AVG_EN, IADC_FAST_AVG_EN_SET);
  181. else
  182. ret = iadc_write(iadc, IADC_FAST_AVG_EN, 0);
  183. if (ret < 0)
  184. return ret;
  185. if (!iadc->poll_eoc)
  186. reinit_completion(&iadc->complete);
  187. ret = iadc_set_state(iadc, true);
  188. if (ret < 0)
  189. return ret;
  190. /* Request conversion */
  191. return iadc_write(iadc, IADC_CONV_REQ, IADC_CONV_REQ_SET);
  192. }
  193. static int iadc_poll_wait_eoc(struct iadc_chip *iadc, unsigned int interval_us)
  194. {
  195. unsigned int count, retry;
  196. int ret;
  197. u8 sta1;
  198. retry = interval_us / IADC_CONV_TIME_MIN_US;
  199. for (count = 0; count < retry; count++) {
  200. ret = iadc_read(iadc, IADC_STATUS1, &sta1);
  201. if (ret < 0)
  202. return ret;
  203. sta1 &= IADC_STATUS1_REQ_STS_EOC_MASK;
  204. if (sta1 == IADC_STATUS1_EOC)
  205. return 0;
  206. usleep_range(IADC_CONV_TIME_MIN_US, IADC_CONV_TIME_MAX_US);
  207. }
  208. iadc_status_show(iadc);
  209. return -ETIMEDOUT;
  210. }
  211. static int iadc_read_result(struct iadc_chip *iadc, u16 *data)
  212. {
  213. return regmap_bulk_read(iadc->regmap, iadc->base + IADC_DATA, data, 2);
  214. }
  215. static int iadc_do_conversion(struct iadc_chip *iadc, int chan, u16 *data)
  216. {
  217. unsigned int wait;
  218. int ret;
  219. ret = iadc_configure(iadc, chan);
  220. if (ret < 0)
  221. goto exit;
  222. wait = BIT(IADC_DEF_AVG_SAMPLES) * IADC_CONV_TIME_MIN_US * 2;
  223. if (iadc->poll_eoc) {
  224. ret = iadc_poll_wait_eoc(iadc, wait);
  225. } else {
  226. ret = wait_for_completion_timeout(&iadc->complete,
  227. usecs_to_jiffies(wait));
  228. if (!ret)
  229. ret = -ETIMEDOUT;
  230. else
  231. /* double check conversion status */
  232. ret = iadc_poll_wait_eoc(iadc, IADC_CONV_TIME_MIN_US);
  233. }
  234. if (!ret)
  235. ret = iadc_read_result(iadc, data);
  236. exit:
  237. iadc_set_state(iadc, false);
  238. if (ret < 0)
  239. dev_err(iadc->dev, "conversion failed\n");
  240. return ret;
  241. }
  242. static int iadc_read_raw(struct iio_dev *indio_dev,
  243. struct iio_chan_spec const *chan,
  244. int *val, int *val2, long mask)
  245. {
  246. struct iadc_chip *iadc = iio_priv(indio_dev);
  247. s32 isense_ua, vsense_uv;
  248. u16 adc_raw, vsense_raw;
  249. int ret;
  250. switch (mask) {
  251. case IIO_CHAN_INFO_RAW:
  252. mutex_lock(&iadc->lock);
  253. ret = iadc_do_conversion(iadc, chan->channel, &adc_raw);
  254. mutex_unlock(&iadc->lock);
  255. if (ret < 0)
  256. return ret;
  257. vsense_raw = adc_raw - iadc->offset[chan->channel];
  258. vsense_uv = vsense_raw * IADC_REF_GAIN_MICRO_VOLTS;
  259. vsense_uv /= (s32)iadc->gain - iadc->offset[chan->channel];
  260. isense_ua = vsense_uv / iadc->rsense[chan->channel];
  261. dev_dbg(iadc->dev, "off %d gain %d adc %d %duV I %duA\n",
  262. iadc->offset[chan->channel], iadc->gain,
  263. adc_raw, vsense_uv, isense_ua);
  264. *val = isense_ua;
  265. return IIO_VAL_INT;
  266. case IIO_CHAN_INFO_SCALE:
  267. *val = 0;
  268. *val2 = 1000;
  269. return IIO_VAL_INT_PLUS_MICRO;
  270. }
  271. return -EINVAL;
  272. }
  273. static const struct iio_info iadc_info = {
  274. .read_raw = iadc_read_raw,
  275. };
  276. static irqreturn_t iadc_isr(int irq, void *dev_id)
  277. {
  278. struct iadc_chip *iadc = dev_id;
  279. complete(&iadc->complete);
  280. return IRQ_HANDLED;
  281. }
  282. static int iadc_update_offset(struct iadc_chip *iadc)
  283. {
  284. int ret;
  285. ret = iadc_do_conversion(iadc, IADC_GAIN_17P857MV, &iadc->gain);
  286. if (ret < 0)
  287. return ret;
  288. ret = iadc_do_conversion(iadc, IADC_INT_OFFSET_CSP2_CSN2,
  289. &iadc->offset[IADC_INT_RSENSE]);
  290. if (ret < 0)
  291. return ret;
  292. if (iadc->gain == iadc->offset[IADC_INT_RSENSE]) {
  293. dev_err(iadc->dev, "error: internal offset == gain %d\n",
  294. iadc->gain);
  295. return -EINVAL;
  296. }
  297. ret = iadc_do_conversion(iadc, IADC_EXT_OFFSET_CSP_CSN,
  298. &iadc->offset[IADC_EXT_RSENSE]);
  299. if (ret < 0)
  300. return ret;
  301. if (iadc->gain == iadc->offset[IADC_EXT_RSENSE]) {
  302. dev_err(iadc->dev, "error: external offset == gain %d\n",
  303. iadc->gain);
  304. return -EINVAL;
  305. }
  306. return 0;
  307. }
  308. static int iadc_version_check(struct iadc_chip *iadc)
  309. {
  310. u8 val;
  311. int ret;
  312. ret = iadc_read(iadc, IADC_PERPH_TYPE, &val);
  313. if (ret < 0)
  314. return ret;
  315. if (val < IADC_PERPH_TYPE_ADC) {
  316. dev_err(iadc->dev, "%d is not ADC\n", val);
  317. return -EINVAL;
  318. }
  319. ret = iadc_read(iadc, IADC_PERPH_SUBTYPE, &val);
  320. if (ret < 0)
  321. return ret;
  322. if (val < IADC_PERPH_SUBTYPE_IADC) {
  323. dev_err(iadc->dev, "%d is not IADC\n", val);
  324. return -EINVAL;
  325. }
  326. ret = iadc_read(iadc, IADC_REVISION2, &val);
  327. if (ret < 0)
  328. return ret;
  329. if (val < IADC_REVISION2_SUPPORTED_IADC) {
  330. dev_err(iadc->dev, "revision %d not supported\n", val);
  331. return -EINVAL;
  332. }
  333. return 0;
  334. }
  335. static int iadc_rsense_read(struct iadc_chip *iadc, struct device_node *node)
  336. {
  337. int ret, sign, int_sense;
  338. u8 deviation;
  339. ret = of_property_read_u32(node, "qcom,external-resistor-micro-ohms",
  340. &iadc->rsense[IADC_EXT_RSENSE]);
  341. if (ret < 0)
  342. iadc->rsense[IADC_EXT_RSENSE] = IADC_INT_RSENSE_IDEAL_VALUE;
  343. if (!iadc->rsense[IADC_EXT_RSENSE]) {
  344. dev_err(iadc->dev, "external resistor can't be zero Ohms");
  345. return -EINVAL;
  346. }
  347. ret = iadc_read(iadc, IADC_NOMINAL_RSENSE, &deviation);
  348. if (ret < 0)
  349. return ret;
  350. /*
  351. * Deviation value stored is an offset from 10 mili Ohms, bit 7 is
  352. * the sign, the remaining bits have an LSB of 15625 nano Ohms.
  353. */
  354. sign = (deviation & IADC_NOMINAL_RSENSE_SIGN_MASK) ? -1 : 1;
  355. deviation &= ~IADC_NOMINAL_RSENSE_SIGN_MASK;
  356. /* Scale it to nono Ohms */
  357. int_sense = IADC_INT_RSENSE_IDEAL_VALUE * 1000;
  358. int_sense += sign * deviation * IADC_INT_RSENSE_DEVIATION;
  359. int_sense /= 1000; /* micro Ohms */
  360. iadc->rsense[IADC_INT_RSENSE] = int_sense;
  361. return 0;
  362. }
  363. static const struct iio_chan_spec iadc_channels[] = {
  364. {
  365. .type = IIO_CURRENT,
  366. .datasheet_name = "INTERNAL_RSENSE",
  367. .channel = 0,
  368. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
  369. BIT(IIO_CHAN_INFO_SCALE),
  370. .indexed = 1,
  371. },
  372. {
  373. .type = IIO_CURRENT,
  374. .datasheet_name = "EXTERNAL_RSENSE",
  375. .channel = 1,
  376. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
  377. BIT(IIO_CHAN_INFO_SCALE),
  378. .indexed = 1,
  379. },
  380. };
  381. static int iadc_probe(struct platform_device *pdev)
  382. {
  383. struct device_node *node = pdev->dev.of_node;
  384. struct device *dev = &pdev->dev;
  385. struct iio_dev *indio_dev;
  386. struct iadc_chip *iadc;
  387. int ret, irq_eoc;
  388. u32 res;
  389. indio_dev = devm_iio_device_alloc(dev, sizeof(*iadc));
  390. if (!indio_dev)
  391. return -ENOMEM;
  392. iadc = iio_priv(indio_dev);
  393. iadc->dev = dev;
  394. iadc->regmap = dev_get_regmap(dev->parent, NULL);
  395. if (!iadc->regmap)
  396. return -ENODEV;
  397. init_completion(&iadc->complete);
  398. mutex_init(&iadc->lock);
  399. ret = of_property_read_u32(node, "reg", &res);
  400. if (ret < 0)
  401. return -ENODEV;
  402. iadc->base = res;
  403. ret = iadc_version_check(iadc);
  404. if (ret < 0)
  405. return -ENODEV;
  406. ret = iadc_rsense_read(iadc, node);
  407. if (ret < 0)
  408. return -ENODEV;
  409. dev_dbg(iadc->dev, "sense resistors %d and %d micro Ohm\n",
  410. iadc->rsense[IADC_INT_RSENSE],
  411. iadc->rsense[IADC_EXT_RSENSE]);
  412. irq_eoc = platform_get_irq(pdev, 0);
  413. if (irq_eoc == -EPROBE_DEFER)
  414. return irq_eoc;
  415. if (irq_eoc < 0)
  416. iadc->poll_eoc = true;
  417. ret = iadc_reset(iadc);
  418. if (ret < 0) {
  419. dev_err(dev, "reset failed\n");
  420. return ret;
  421. }
  422. if (!iadc->poll_eoc) {
  423. ret = devm_request_irq(dev, irq_eoc, iadc_isr, 0,
  424. "spmi-iadc", iadc);
  425. if (!ret)
  426. enable_irq_wake(irq_eoc);
  427. else
  428. return ret;
  429. } else {
  430. device_init_wakeup(iadc->dev, 1);
  431. }
  432. ret = iadc_update_offset(iadc);
  433. if (ret < 0) {
  434. dev_err(dev, "failed offset calibration\n");
  435. return ret;
  436. }
  437. indio_dev->name = pdev->name;
  438. indio_dev->modes = INDIO_DIRECT_MODE;
  439. indio_dev->info = &iadc_info;
  440. indio_dev->channels = iadc_channels;
  441. indio_dev->num_channels = ARRAY_SIZE(iadc_channels);
  442. return devm_iio_device_register(dev, indio_dev);
  443. }
  444. static const struct of_device_id iadc_match_table[] = {
  445. { .compatible = "qcom,spmi-iadc" },
  446. { }
  447. };
  448. MODULE_DEVICE_TABLE(of, iadc_match_table);
  449. static struct platform_driver iadc_driver = {
  450. .driver = {
  451. .name = "qcom-spmi-iadc",
  452. .of_match_table = iadc_match_table,
  453. },
  454. .probe = iadc_probe,
  455. };
  456. module_platform_driver(iadc_driver);
  457. MODULE_ALIAS("platform:qcom-spmi-iadc");
  458. MODULE_DESCRIPTION("Qualcomm SPMI PMIC current ADC driver");
  459. MODULE_LICENSE("GPL v2");
  460. MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");