qcom-spmi-adc5.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/bitops.h>
  6. #include <linux/completion.h>
  7. #include <linux/delay.h>
  8. #include <linux/err.h>
  9. #include <linux/iio/iio.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/kernel.h>
  12. #include <linux/log2.h>
  13. #include <linux/math64.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/regmap.h>
  18. #include <linux/slab.h>
  19. #include <dt-bindings/iio/qcom,spmi-vadc.h>
  20. #include "qcom-vadc-common.h"
  21. #define ADC5_USR_REVISION1 0x0
  22. #define ADC5_USR_STATUS1 0x8
  23. #define ADC5_USR_STATUS1_CONV_FAULT BIT(7)
  24. #define ADC5_USR_STATUS1_REQ_STS BIT(1)
  25. #define ADC5_USR_STATUS1_EOC BIT(0)
  26. #define ADC5_USR_STATUS1_REQ_STS_EOC_MASK 0x3
  27. #define ADC5_USR_STATUS2 0x9
  28. #define ADC5_USR_STATUS2_CONV_SEQ_MASK 0x70
  29. #define ADC5_USR_STATUS2_CONV_SEQ_MASK_SHIFT 0x5
  30. #define ADC5_USR_IBAT_MEAS 0xf
  31. #define ADC5_USR_IBAT_MEAS_SUPPORTED BIT(0)
  32. #define ADC5_USR_DIG_PARAM 0x42
  33. #define ADC5_USR_DIG_PARAM_CAL_VAL BIT(6)
  34. #define ADC5_USR_DIG_PARAM_CAL_VAL_SHIFT 6
  35. #define ADC5_USR_DIG_PARAM_CAL_SEL 0x30
  36. #define ADC5_USR_DIG_PARAM_CAL_SEL_SHIFT 4
  37. #define ADC5_USR_DIG_PARAM_DEC_RATIO_SEL 0xc
  38. #define ADC5_USR_DIG_PARAM_DEC_RATIO_SEL_SHIFT 2
  39. #define ADC5_USR_FAST_AVG_CTL 0x43
  40. #define ADC5_USR_FAST_AVG_CTL_EN BIT(7)
  41. #define ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK 0x7
  42. #define ADC5_USR_CH_SEL_CTL 0x44
  43. #define ADC5_USR_DELAY_CTL 0x45
  44. #define ADC5_USR_HW_SETTLE_DELAY_MASK 0xf
  45. #define ADC5_USR_EN_CTL1 0x46
  46. #define ADC5_USR_EN_CTL1_ADC_EN BIT(7)
  47. #define ADC5_USR_CONV_REQ 0x47
  48. #define ADC5_USR_CONV_REQ_REQ BIT(7)
  49. #define ADC5_USR_DATA0 0x50
  50. #define ADC5_USR_DATA1 0x51
  51. #define ADC5_USR_IBAT_DATA0 0x52
  52. #define ADC5_USR_IBAT_DATA1 0x53
  53. #define ADC_CHANNEL_OFFSET 0x8
  54. #define ADC_CHANNEL_MASK GENMASK(7, 0)
  55. /*
  56. * Conversion time varies based on the decimation, clock rate, fast average
  57. * samples and measurements queued across different VADC peripherals.
  58. * Set the timeout to a max of 100ms.
  59. */
  60. #define ADC5_CONV_TIME_MIN_US 263
  61. #define ADC5_CONV_TIME_MAX_US 264
  62. #define ADC5_CONV_TIME_RETRY 400
  63. #define ADC5_CONV_TIMEOUT msecs_to_jiffies(100)
  64. /* Digital version >= 5.3 supports hw_settle_2 */
  65. #define ADC5_HW_SETTLE_DIFF_MINOR 3
  66. #define ADC5_HW_SETTLE_DIFF_MAJOR 5
  67. /* For PMIC7 */
  68. #define ADC_APP_SID 0x40
  69. #define ADC_APP_SID_MASK GENMASK(3, 0)
  70. #define ADC7_CONV_TIMEOUT msecs_to_jiffies(10)
  71. enum adc5_cal_method {
  72. ADC5_NO_CAL = 0,
  73. ADC5_RATIOMETRIC_CAL,
  74. ADC5_ABSOLUTE_CAL
  75. };
  76. enum adc5_cal_val {
  77. ADC5_TIMER_CAL = 0,
  78. ADC5_NEW_CAL
  79. };
  80. /**
  81. * struct adc5_channel_prop - ADC channel property.
  82. * @channel: channel number, refer to the channel list.
  83. * @cal_method: calibration method.
  84. * @cal_val: calibration value
  85. * @decimation: sampling rate supported for the channel.
  86. * @sid: slave id of PMIC owning the channel, for PMIC7.
  87. * @prescale: channel scaling performed on the input signal.
  88. * @hw_settle_time: the time between AMUX being configured and the
  89. * start of conversion.
  90. * @avg_samples: ability to provide single result from the ADC
  91. * that is an average of multiple measurements.
  92. * @scale_fn_type: Represents the scaling function to convert voltage
  93. * physical units desired by the client for the channel.
  94. * @datasheet_name: Channel name used in device tree.
  95. */
  96. struct adc5_channel_prop {
  97. unsigned int channel;
  98. enum adc5_cal_method cal_method;
  99. enum adc5_cal_val cal_val;
  100. unsigned int decimation;
  101. unsigned int sid;
  102. unsigned int prescale;
  103. unsigned int hw_settle_time;
  104. unsigned int avg_samples;
  105. enum vadc_scale_fn_type scale_fn_type;
  106. const char *datasheet_name;
  107. };
  108. /**
  109. * struct adc5_chip - ADC private structure.
  110. * @regmap: SPMI ADC5 peripheral register map field.
  111. * @dev: SPMI ADC5 device.
  112. * @base: base address for the ADC peripheral.
  113. * @nchannels: number of ADC channels.
  114. * @chan_props: array of ADC channel properties.
  115. * @iio_chans: array of IIO channels specification.
  116. * @poll_eoc: use polling instead of interrupt.
  117. * @complete: ADC result notification after interrupt is received.
  118. * @lock: ADC lock for access to the peripheral.
  119. * @data: software configuration data.
  120. */
  121. struct adc5_chip {
  122. struct regmap *regmap;
  123. struct device *dev;
  124. u16 base;
  125. unsigned int nchannels;
  126. struct adc5_channel_prop *chan_props;
  127. struct iio_chan_spec *iio_chans;
  128. bool poll_eoc;
  129. struct completion complete;
  130. struct mutex lock;
  131. const struct adc5_data *data;
  132. };
  133. static const struct vadc_prescale_ratio adc5_prescale_ratios[] = {
  134. {.num = 1, .den = 1},
  135. {.num = 1, .den = 3},
  136. {.num = 1, .den = 4},
  137. {.num = 1, .den = 6},
  138. {.num = 1, .den = 20},
  139. {.num = 1, .den = 8},
  140. {.num = 10, .den = 81},
  141. {.num = 1, .den = 10},
  142. {.num = 1, .den = 16}
  143. };
  144. static int adc5_read(struct adc5_chip *adc, u16 offset, u8 *data, int len)
  145. {
  146. return regmap_bulk_read(adc->regmap, adc->base + offset, data, len);
  147. }
  148. static int adc5_write(struct adc5_chip *adc, u16 offset, u8 *data, int len)
  149. {
  150. return regmap_bulk_write(adc->regmap, adc->base + offset, data, len);
  151. }
  152. static int adc5_masked_write(struct adc5_chip *adc, u16 offset, u8 mask, u8 val)
  153. {
  154. return regmap_update_bits(adc->regmap, adc->base + offset, mask, val);
  155. }
  156. static int adc5_prescaling_from_dt(u32 num, u32 den)
  157. {
  158. unsigned int pre;
  159. for (pre = 0; pre < ARRAY_SIZE(adc5_prescale_ratios); pre++)
  160. if (adc5_prescale_ratios[pre].num == num &&
  161. adc5_prescale_ratios[pre].den == den)
  162. break;
  163. if (pre == ARRAY_SIZE(adc5_prescale_ratios))
  164. return -EINVAL;
  165. return pre;
  166. }
  167. static int adc5_hw_settle_time_from_dt(u32 value,
  168. const unsigned int *hw_settle)
  169. {
  170. unsigned int i;
  171. for (i = 0; i < VADC_HW_SETTLE_SAMPLES_MAX; i++) {
  172. if (value == hw_settle[i])
  173. return i;
  174. }
  175. return -EINVAL;
  176. }
  177. static int adc5_avg_samples_from_dt(u32 value)
  178. {
  179. if (!is_power_of_2(value) || value > ADC5_AVG_SAMPLES_MAX)
  180. return -EINVAL;
  181. return __ffs(value);
  182. }
  183. static int adc5_decimation_from_dt(u32 value,
  184. const unsigned int *decimation)
  185. {
  186. unsigned int i;
  187. for (i = 0; i < ADC5_DECIMATION_SAMPLES_MAX; i++) {
  188. if (value == decimation[i])
  189. return i;
  190. }
  191. return -EINVAL;
  192. }
  193. static int adc5_read_voltage_data(struct adc5_chip *adc, u16 *data)
  194. {
  195. int ret;
  196. u8 rslt_lsb, rslt_msb;
  197. ret = adc5_read(adc, ADC5_USR_DATA0, &rslt_lsb, sizeof(rslt_lsb));
  198. if (ret)
  199. return ret;
  200. ret = adc5_read(adc, ADC5_USR_DATA1, &rslt_msb, sizeof(rslt_lsb));
  201. if (ret)
  202. return ret;
  203. *data = (rslt_msb << 8) | rslt_lsb;
  204. if (*data == ADC5_USR_DATA_CHECK) {
  205. dev_err(adc->dev, "Invalid data:0x%x\n", *data);
  206. return -EINVAL;
  207. }
  208. dev_dbg(adc->dev, "voltage raw code:0x%x\n", *data);
  209. return 0;
  210. }
  211. static int adc5_poll_wait_eoc(struct adc5_chip *adc)
  212. {
  213. unsigned int count, retry = ADC5_CONV_TIME_RETRY;
  214. u8 status1;
  215. int ret;
  216. for (count = 0; count < retry; count++) {
  217. ret = adc5_read(adc, ADC5_USR_STATUS1, &status1,
  218. sizeof(status1));
  219. if (ret)
  220. return ret;
  221. status1 &= ADC5_USR_STATUS1_REQ_STS_EOC_MASK;
  222. if (status1 == ADC5_USR_STATUS1_EOC)
  223. return 0;
  224. usleep_range(ADC5_CONV_TIME_MIN_US, ADC5_CONV_TIME_MAX_US);
  225. }
  226. return -ETIMEDOUT;
  227. }
  228. static void adc5_update_dig_param(struct adc5_chip *adc,
  229. struct adc5_channel_prop *prop, u8 *data)
  230. {
  231. /* Update calibration value */
  232. *data &= ~ADC5_USR_DIG_PARAM_CAL_VAL;
  233. *data |= (prop->cal_val << ADC5_USR_DIG_PARAM_CAL_VAL_SHIFT);
  234. /* Update calibration select */
  235. *data &= ~ADC5_USR_DIG_PARAM_CAL_SEL;
  236. *data |= (prop->cal_method << ADC5_USR_DIG_PARAM_CAL_SEL_SHIFT);
  237. /* Update decimation ratio select */
  238. *data &= ~ADC5_USR_DIG_PARAM_DEC_RATIO_SEL;
  239. *data |= (prop->decimation << ADC5_USR_DIG_PARAM_DEC_RATIO_SEL_SHIFT);
  240. }
  241. static int adc5_configure(struct adc5_chip *adc,
  242. struct adc5_channel_prop *prop)
  243. {
  244. int ret;
  245. u8 buf[6];
  246. /* Read registers 0x42 through 0x46 */
  247. ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
  248. if (ret)
  249. return ret;
  250. /* Digital param selection */
  251. adc5_update_dig_param(adc, prop, &buf[0]);
  252. /* Update fast average sample value */
  253. buf[1] &= (u8) ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK;
  254. buf[1] |= prop->avg_samples;
  255. /* Select ADC channel */
  256. buf[2] = prop->channel;
  257. /* Select HW settle delay for channel */
  258. buf[3] &= (u8) ~ADC5_USR_HW_SETTLE_DELAY_MASK;
  259. buf[3] |= prop->hw_settle_time;
  260. /* Select ADC enable */
  261. buf[4] |= ADC5_USR_EN_CTL1_ADC_EN;
  262. /* Select CONV request */
  263. buf[5] |= ADC5_USR_CONV_REQ_REQ;
  264. if (!adc->poll_eoc)
  265. reinit_completion(&adc->complete);
  266. return adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
  267. }
  268. static int adc7_configure(struct adc5_chip *adc,
  269. struct adc5_channel_prop *prop)
  270. {
  271. int ret;
  272. u8 conv_req = 0, buf[4];
  273. ret = adc5_masked_write(adc, ADC_APP_SID, ADC_APP_SID_MASK, prop->sid);
  274. if (ret)
  275. return ret;
  276. ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
  277. if (ret)
  278. return ret;
  279. /* Digital param selection */
  280. adc5_update_dig_param(adc, prop, &buf[0]);
  281. /* Update fast average sample value */
  282. buf[1] &= ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK;
  283. buf[1] |= prop->avg_samples;
  284. /* Select ADC channel */
  285. buf[2] = prop->channel;
  286. /* Select HW settle delay for channel */
  287. buf[3] &= ~ADC5_USR_HW_SETTLE_DELAY_MASK;
  288. buf[3] |= prop->hw_settle_time;
  289. /* Select CONV request */
  290. conv_req = ADC5_USR_CONV_REQ_REQ;
  291. if (!adc->poll_eoc)
  292. reinit_completion(&adc->complete);
  293. ret = adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
  294. if (ret)
  295. return ret;
  296. return adc5_write(adc, ADC5_USR_CONV_REQ, &conv_req, 1);
  297. }
  298. static int adc5_do_conversion(struct adc5_chip *adc,
  299. struct adc5_channel_prop *prop,
  300. struct iio_chan_spec const *chan,
  301. u16 *data_volt, u16 *data_cur)
  302. {
  303. int ret;
  304. mutex_lock(&adc->lock);
  305. ret = adc5_configure(adc, prop);
  306. if (ret) {
  307. dev_err(adc->dev, "ADC configure failed with %d\n", ret);
  308. goto unlock;
  309. }
  310. if (adc->poll_eoc) {
  311. ret = adc5_poll_wait_eoc(adc);
  312. if (ret) {
  313. dev_err(adc->dev, "EOC bit not set\n");
  314. goto unlock;
  315. }
  316. } else {
  317. ret = wait_for_completion_timeout(&adc->complete,
  318. ADC5_CONV_TIMEOUT);
  319. if (!ret) {
  320. dev_dbg(adc->dev, "Did not get completion timeout.\n");
  321. ret = adc5_poll_wait_eoc(adc);
  322. if (ret) {
  323. dev_err(adc->dev, "EOC bit not set\n");
  324. goto unlock;
  325. }
  326. }
  327. }
  328. ret = adc5_read_voltage_data(adc, data_volt);
  329. unlock:
  330. mutex_unlock(&adc->lock);
  331. return ret;
  332. }
  333. static int adc7_do_conversion(struct adc5_chip *adc,
  334. struct adc5_channel_prop *prop,
  335. struct iio_chan_spec const *chan,
  336. u16 *data_volt, u16 *data_cur)
  337. {
  338. int ret;
  339. u8 status;
  340. mutex_lock(&adc->lock);
  341. ret = adc7_configure(adc, prop);
  342. if (ret) {
  343. dev_err(adc->dev, "ADC configure failed with %d\n", ret);
  344. goto unlock;
  345. }
  346. /* No support for polling mode at present */
  347. wait_for_completion_timeout(&adc->complete, ADC7_CONV_TIMEOUT);
  348. ret = adc5_read(adc, ADC5_USR_STATUS1, &status, 1);
  349. if (ret)
  350. goto unlock;
  351. if (status & ADC5_USR_STATUS1_CONV_FAULT) {
  352. dev_err(adc->dev, "Unexpected conversion fault\n");
  353. ret = -EIO;
  354. goto unlock;
  355. }
  356. ret = adc5_read_voltage_data(adc, data_volt);
  357. unlock:
  358. mutex_unlock(&adc->lock);
  359. return ret;
  360. }
  361. typedef int (*adc_do_conversion)(struct adc5_chip *adc,
  362. struct adc5_channel_prop *prop,
  363. struct iio_chan_spec const *chan,
  364. u16 *data_volt, u16 *data_cur);
  365. static irqreturn_t adc5_isr(int irq, void *dev_id)
  366. {
  367. struct adc5_chip *adc = dev_id;
  368. complete(&adc->complete);
  369. return IRQ_HANDLED;
  370. }
  371. static int adc5_of_xlate(struct iio_dev *indio_dev,
  372. const struct of_phandle_args *iiospec)
  373. {
  374. struct adc5_chip *adc = iio_priv(indio_dev);
  375. int i;
  376. for (i = 0; i < adc->nchannels; i++)
  377. if (adc->chan_props[i].channel == iiospec->args[0])
  378. return i;
  379. return -EINVAL;
  380. }
  381. static int adc7_of_xlate(struct iio_dev *indio_dev,
  382. const struct of_phandle_args *iiospec)
  383. {
  384. struct adc5_chip *adc = iio_priv(indio_dev);
  385. int i, v_channel;
  386. for (i = 0; i < adc->nchannels; i++) {
  387. v_channel = (adc->chan_props[i].sid << ADC_CHANNEL_OFFSET) |
  388. adc->chan_props[i].channel;
  389. if (v_channel == iiospec->args[0])
  390. return i;
  391. }
  392. return -EINVAL;
  393. }
  394. static int adc_read_raw_common(struct iio_dev *indio_dev,
  395. struct iio_chan_spec const *chan, int *val, int *val2,
  396. long mask, adc_do_conversion do_conv)
  397. {
  398. struct adc5_chip *adc = iio_priv(indio_dev);
  399. struct adc5_channel_prop *prop;
  400. u16 adc_code_volt, adc_code_cur;
  401. int ret;
  402. prop = &adc->chan_props[chan->address];
  403. switch (mask) {
  404. case IIO_CHAN_INFO_PROCESSED:
  405. ret = do_conv(adc, prop, chan,
  406. &adc_code_volt, &adc_code_cur);
  407. if (ret)
  408. return ret;
  409. ret = qcom_adc5_hw_scale(prop->scale_fn_type,
  410. &adc5_prescale_ratios[prop->prescale],
  411. adc->data,
  412. adc_code_volt, val);
  413. if (ret)
  414. return ret;
  415. return IIO_VAL_INT;
  416. default:
  417. return -EINVAL;
  418. }
  419. }
  420. static int adc5_read_raw(struct iio_dev *indio_dev,
  421. struct iio_chan_spec const *chan, int *val, int *val2,
  422. long mask)
  423. {
  424. return adc_read_raw_common(indio_dev, chan, val, val2,
  425. mask, adc5_do_conversion);
  426. }
  427. static int adc7_read_raw(struct iio_dev *indio_dev,
  428. struct iio_chan_spec const *chan, int *val, int *val2,
  429. long mask)
  430. {
  431. return adc_read_raw_common(indio_dev, chan, val, val2,
  432. mask, adc7_do_conversion);
  433. }
  434. static const struct iio_info adc5_info = {
  435. .read_raw = adc5_read_raw,
  436. .of_xlate = adc5_of_xlate,
  437. };
  438. static const struct iio_info adc7_info = {
  439. .read_raw = adc7_read_raw,
  440. .of_xlate = adc7_of_xlate,
  441. };
  442. struct adc5_channels {
  443. const char *datasheet_name;
  444. unsigned int prescale_index;
  445. enum iio_chan_type type;
  446. long info_mask;
  447. enum vadc_scale_fn_type scale_fn_type;
  448. };
  449. /* In these definitions, _pre refers to an index into adc5_prescale_ratios. */
  450. #define ADC5_CHAN(_dname, _type, _mask, _pre, _scale) \
  451. { \
  452. .datasheet_name = _dname, \
  453. .prescale_index = _pre, \
  454. .type = _type, \
  455. .info_mask = _mask, \
  456. .scale_fn_type = _scale, \
  457. }, \
  458. #define ADC5_CHAN_TEMP(_dname, _pre, _scale) \
  459. ADC5_CHAN(_dname, IIO_TEMP, \
  460. BIT(IIO_CHAN_INFO_PROCESSED), \
  461. _pre, _scale) \
  462. #define ADC5_CHAN_VOLT(_dname, _pre, _scale) \
  463. ADC5_CHAN(_dname, IIO_VOLTAGE, \
  464. BIT(IIO_CHAN_INFO_PROCESSED), \
  465. _pre, _scale) \
  466. static const struct adc5_channels adc5_chans_pmic[ADC5_MAX_CHANNEL] = {
  467. [ADC5_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0,
  468. SCALE_HW_CALIB_DEFAULT)
  469. [ADC5_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
  470. SCALE_HW_CALIB_DEFAULT)
  471. [ADC5_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
  472. SCALE_HW_CALIB_DEFAULT)
  473. [ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 1,
  474. SCALE_HW_CALIB_DEFAULT)
  475. [ADC5_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0,
  476. SCALE_HW_CALIB_PMIC_THERM)
  477. [ADC5_USB_IN_I] = ADC5_CHAN_VOLT("usb_in_i_uv", 0,
  478. SCALE_HW_CALIB_DEFAULT)
  479. [ADC5_USB_IN_V_16] = ADC5_CHAN_VOLT("usb_in_v_div_16", 8,
  480. SCALE_HW_CALIB_DEFAULT)
  481. [ADC5_CHG_TEMP] = ADC5_CHAN_TEMP("chg_temp", 0,
  482. SCALE_HW_CALIB_PM5_CHG_TEMP)
  483. /* Charger prescales SBUx and MID_CHG to fit within 1.8V upper unit */
  484. [ADC5_SBUx] = ADC5_CHAN_VOLT("chg_sbux", 1,
  485. SCALE_HW_CALIB_DEFAULT)
  486. [ADC5_MID_CHG_DIV6] = ADC5_CHAN_VOLT("chg_mid_chg", 3,
  487. SCALE_HW_CALIB_DEFAULT)
  488. [ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm", 0,
  489. SCALE_HW_CALIB_XOTHERM)
  490. [ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 0,
  491. SCALE_HW_CALIB_THERM_100K_PULLUP)
  492. [ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 0,
  493. SCALE_HW_CALIB_THERM_100K_PULLUP)
  494. [ADC5_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_100k_pu", 0,
  495. SCALE_HW_CALIB_THERM_100K_PULLUP)
  496. [ADC5_AMUX_THM2] = ADC5_CHAN_TEMP("amux_thm2", 0,
  497. SCALE_HW_CALIB_PM5_SMB_TEMP)
  498. };
  499. static const struct adc5_channels adc7_chans_pmic[ADC5_MAX_CHANNEL] = {
  500. [ADC7_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0,
  501. SCALE_HW_CALIB_DEFAULT)
  502. [ADC7_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
  503. SCALE_HW_CALIB_DEFAULT)
  504. [ADC7_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
  505. SCALE_HW_CALIB_DEFAULT)
  506. [ADC7_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 3,
  507. SCALE_HW_CALIB_DEFAULT)
  508. [ADC7_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0,
  509. SCALE_HW_CALIB_PMIC_THERM_PM7)
  510. [ADC7_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_pu2", 0,
  511. SCALE_HW_CALIB_THERM_100K_PU_PM7)
  512. [ADC7_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_pu2", 0,
  513. SCALE_HW_CALIB_THERM_100K_PU_PM7)
  514. [ADC7_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_pu2", 0,
  515. SCALE_HW_CALIB_THERM_100K_PU_PM7)
  516. [ADC7_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_pu2", 0,
  517. SCALE_HW_CALIB_THERM_100K_PU_PM7)
  518. [ADC7_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_pu2", 0,
  519. SCALE_HW_CALIB_THERM_100K_PU_PM7)
  520. [ADC7_AMUX_THM6_100K_PU] = ADC5_CHAN_TEMP("amux_thm6_pu2", 0,
  521. SCALE_HW_CALIB_THERM_100K_PU_PM7)
  522. [ADC7_GPIO1_100K_PU] = ADC5_CHAN_TEMP("gpio1_pu2", 0,
  523. SCALE_HW_CALIB_THERM_100K_PU_PM7)
  524. [ADC7_GPIO2_100K_PU] = ADC5_CHAN_TEMP("gpio2_pu2", 0,
  525. SCALE_HW_CALIB_THERM_100K_PU_PM7)
  526. [ADC7_GPIO3_100K_PU] = ADC5_CHAN_TEMP("gpio3_pu2", 0,
  527. SCALE_HW_CALIB_THERM_100K_PU_PM7)
  528. [ADC7_GPIO4_100K_PU] = ADC5_CHAN_TEMP("gpio4_pu2", 0,
  529. SCALE_HW_CALIB_THERM_100K_PU_PM7)
  530. };
  531. static const struct adc5_channels adc5_chans_rev2[ADC5_MAX_CHANNEL] = {
  532. [ADC5_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0,
  533. SCALE_HW_CALIB_DEFAULT)
  534. [ADC5_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
  535. SCALE_HW_CALIB_DEFAULT)
  536. [ADC5_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
  537. SCALE_HW_CALIB_DEFAULT)
  538. [ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 1,
  539. SCALE_HW_CALIB_DEFAULT)
  540. [ADC5_VCOIN] = ADC5_CHAN_VOLT("vcoin", 1,
  541. SCALE_HW_CALIB_DEFAULT)
  542. [ADC5_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0,
  543. SCALE_HW_CALIB_PMIC_THERM)
  544. [ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 0,
  545. SCALE_HW_CALIB_THERM_100K_PULLUP)
  546. [ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 0,
  547. SCALE_HW_CALIB_THERM_100K_PULLUP)
  548. [ADC5_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_100k_pu", 0,
  549. SCALE_HW_CALIB_THERM_100K_PULLUP)
  550. [ADC5_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_100k_pu", 0,
  551. SCALE_HW_CALIB_THERM_100K_PULLUP)
  552. [ADC5_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_100k_pu", 0,
  553. SCALE_HW_CALIB_THERM_100K_PULLUP)
  554. [ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm_100k_pu", 0,
  555. SCALE_HW_CALIB_THERM_100K_PULLUP)
  556. };
  557. static int adc5_get_dt_channel_data(struct adc5_chip *adc,
  558. struct adc5_channel_prop *prop,
  559. struct device_node *node,
  560. const struct adc5_data *data)
  561. {
  562. const char *name = node->name, *channel_name;
  563. u32 chan, value, varr[2];
  564. u32 sid = 0;
  565. int ret;
  566. struct device *dev = adc->dev;
  567. ret = of_property_read_u32(node, "reg", &chan);
  568. if (ret) {
  569. dev_err(dev, "invalid channel number %s\n", name);
  570. return ret;
  571. }
  572. /* Value read from "reg" is virtual channel number */
  573. /* virtual channel number = sid << 8 | channel number */
  574. if (adc->data->info == &adc7_info) {
  575. sid = chan >> ADC_CHANNEL_OFFSET;
  576. chan = chan & ADC_CHANNEL_MASK;
  577. }
  578. if (chan > ADC5_PARALLEL_ISENSE_VBAT_IDATA ||
  579. !data->adc_chans[chan].datasheet_name) {
  580. dev_err(dev, "%s invalid channel number %d\n", name, chan);
  581. return -EINVAL;
  582. }
  583. /* the channel has DT description */
  584. prop->channel = chan;
  585. prop->sid = sid;
  586. channel_name = of_get_property(node,
  587. "label", NULL) ? : node->name;
  588. if (!channel_name) {
  589. dev_err(dev, "Invalid channel name\n");
  590. return -EINVAL;
  591. }
  592. prop->datasheet_name = channel_name;
  593. ret = of_property_read_u32(node, "qcom,decimation", &value);
  594. if (!ret) {
  595. ret = adc5_decimation_from_dt(value, data->decimation);
  596. if (ret < 0) {
  597. dev_err(dev, "%02x invalid decimation %d\n",
  598. chan, value);
  599. return ret;
  600. }
  601. prop->decimation = ret;
  602. } else {
  603. prop->decimation = ADC5_DECIMATION_DEFAULT;
  604. }
  605. ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2);
  606. if (!ret) {
  607. ret = adc5_prescaling_from_dt(varr[0], varr[1]);
  608. if (ret < 0) {
  609. dev_err(dev, "%02x invalid pre-scaling <%d %d>\n",
  610. chan, varr[0], varr[1]);
  611. return ret;
  612. }
  613. prop->prescale = ret;
  614. } else {
  615. prop->prescale =
  616. adc->data->adc_chans[prop->channel].prescale_index;
  617. }
  618. ret = of_property_read_u32(node, "qcom,hw-settle-time", &value);
  619. if (!ret) {
  620. u8 dig_version[2];
  621. ret = adc5_read(adc, ADC5_USR_REVISION1, dig_version,
  622. sizeof(dig_version));
  623. if (ret) {
  624. dev_err(dev, "Invalid dig version read %d\n", ret);
  625. return ret;
  626. }
  627. dev_dbg(dev, "dig_ver:minor:%d, major:%d\n", dig_version[0],
  628. dig_version[1]);
  629. /* Digital controller >= 5.3 have hw_settle_2 option */
  630. if ((dig_version[0] >= ADC5_HW_SETTLE_DIFF_MINOR &&
  631. dig_version[1] >= ADC5_HW_SETTLE_DIFF_MAJOR) ||
  632. adc->data->info == &adc7_info)
  633. ret = adc5_hw_settle_time_from_dt(value,
  634. data->hw_settle_2);
  635. else
  636. ret = adc5_hw_settle_time_from_dt(value,
  637. data->hw_settle_1);
  638. if (ret < 0) {
  639. dev_err(dev, "%02x invalid hw-settle-time %d us\n",
  640. chan, value);
  641. return ret;
  642. }
  643. prop->hw_settle_time = ret;
  644. } else {
  645. prop->hw_settle_time = VADC_DEF_HW_SETTLE_TIME;
  646. }
  647. ret = of_property_read_u32(node, "qcom,avg-samples", &value);
  648. if (!ret) {
  649. ret = adc5_avg_samples_from_dt(value);
  650. if (ret < 0) {
  651. dev_err(dev, "%02x invalid avg-samples %d\n",
  652. chan, value);
  653. return ret;
  654. }
  655. prop->avg_samples = ret;
  656. } else {
  657. prop->avg_samples = VADC_DEF_AVG_SAMPLES;
  658. }
  659. if (of_property_read_bool(node, "qcom,ratiometric"))
  660. prop->cal_method = ADC5_RATIOMETRIC_CAL;
  661. else
  662. prop->cal_method = ADC5_ABSOLUTE_CAL;
  663. /*
  664. * Default to using timer calibration. Using a fresh calibration value
  665. * for every conversion will increase the overall time for a request.
  666. */
  667. prop->cal_val = ADC5_TIMER_CAL;
  668. dev_dbg(dev, "%02x name %s\n", chan, name);
  669. return 0;
  670. }
  671. static const struct adc5_data adc5_data_pmic = {
  672. .full_scale_code_volt = 0x70e4,
  673. .full_scale_code_cur = 0x2710,
  674. .adc_chans = adc5_chans_pmic,
  675. .info = &adc5_info,
  676. .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
  677. {250, 420, 840},
  678. .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
  679. {15, 100, 200, 300, 400, 500, 600, 700,
  680. 800, 900, 1, 2, 4, 6, 8, 10},
  681. .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
  682. {15, 100, 200, 300, 400, 500, 600, 700,
  683. 1, 2, 4, 8, 16, 32, 64, 128},
  684. };
  685. static const struct adc5_data adc7_data_pmic = {
  686. .full_scale_code_volt = 0x70e4,
  687. .adc_chans = adc7_chans_pmic,
  688. .info = &adc7_info,
  689. .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
  690. {85, 340, 1360},
  691. .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
  692. {15, 100, 200, 300, 400, 500, 600, 700,
  693. 1000, 2000, 4000, 8000, 16000, 32000,
  694. 64000, 128000},
  695. };
  696. static const struct adc5_data adc5_data_pmic_rev2 = {
  697. .full_scale_code_volt = 0x4000,
  698. .full_scale_code_cur = 0x1800,
  699. .adc_chans = adc5_chans_rev2,
  700. .info = &adc5_info,
  701. .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
  702. {256, 512, 1024},
  703. .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
  704. {0, 100, 200, 300, 400, 500, 600, 700,
  705. 800, 900, 1, 2, 4, 6, 8, 10},
  706. .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
  707. {15, 100, 200, 300, 400, 500, 600, 700,
  708. 1, 2, 4, 8, 16, 32, 64, 128},
  709. };
  710. static const struct of_device_id adc5_match_table[] = {
  711. {
  712. .compatible = "qcom,spmi-adc5",
  713. .data = &adc5_data_pmic,
  714. },
  715. {
  716. .compatible = "qcom,spmi-adc7",
  717. .data = &adc7_data_pmic,
  718. },
  719. {
  720. .compatible = "qcom,spmi-adc-rev2",
  721. .data = &adc5_data_pmic_rev2,
  722. },
  723. { }
  724. };
  725. MODULE_DEVICE_TABLE(of, adc5_match_table);
  726. static int adc5_get_dt_data(struct adc5_chip *adc, struct device_node *node)
  727. {
  728. const struct adc5_channels *adc_chan;
  729. struct iio_chan_spec *iio_chan;
  730. struct adc5_channel_prop prop, *chan_props;
  731. struct device_node *child;
  732. unsigned int index = 0;
  733. const struct of_device_id *id;
  734. const struct adc5_data *data;
  735. int ret;
  736. adc->nchannels = of_get_available_child_count(node);
  737. if (!adc->nchannels)
  738. return -EINVAL;
  739. adc->iio_chans = devm_kcalloc(adc->dev, adc->nchannels,
  740. sizeof(*adc->iio_chans), GFP_KERNEL);
  741. if (!adc->iio_chans)
  742. return -ENOMEM;
  743. adc->chan_props = devm_kcalloc(adc->dev, adc->nchannels,
  744. sizeof(*adc->chan_props), GFP_KERNEL);
  745. if (!adc->chan_props)
  746. return -ENOMEM;
  747. chan_props = adc->chan_props;
  748. iio_chan = adc->iio_chans;
  749. id = of_match_node(adc5_match_table, node);
  750. if (id)
  751. data = id->data;
  752. else
  753. data = &adc5_data_pmic;
  754. adc->data = data;
  755. for_each_available_child_of_node(node, child) {
  756. ret = adc5_get_dt_channel_data(adc, &prop, child, data);
  757. if (ret) {
  758. of_node_put(child);
  759. return ret;
  760. }
  761. prop.scale_fn_type =
  762. data->adc_chans[prop.channel].scale_fn_type;
  763. *chan_props = prop;
  764. adc_chan = &data->adc_chans[prop.channel];
  765. iio_chan->channel = prop.channel;
  766. iio_chan->datasheet_name = prop.datasheet_name;
  767. iio_chan->extend_name = prop.datasheet_name;
  768. iio_chan->info_mask_separate = adc_chan->info_mask;
  769. iio_chan->type = adc_chan->type;
  770. iio_chan->address = index;
  771. iio_chan++;
  772. chan_props++;
  773. index++;
  774. }
  775. return 0;
  776. }
  777. static int adc5_probe(struct platform_device *pdev)
  778. {
  779. struct device_node *node = pdev->dev.of_node;
  780. struct device *dev = &pdev->dev;
  781. struct iio_dev *indio_dev;
  782. struct adc5_chip *adc;
  783. struct regmap *regmap;
  784. int ret, irq_eoc;
  785. u32 reg;
  786. regmap = dev_get_regmap(dev->parent, NULL);
  787. if (!regmap)
  788. return -ENODEV;
  789. ret = of_property_read_u32(node, "reg", &reg);
  790. if (ret < 0)
  791. return ret;
  792. indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
  793. if (!indio_dev)
  794. return -ENOMEM;
  795. adc = iio_priv(indio_dev);
  796. adc->regmap = regmap;
  797. adc->dev = dev;
  798. adc->base = reg;
  799. init_completion(&adc->complete);
  800. mutex_init(&adc->lock);
  801. ret = adc5_get_dt_data(adc, node);
  802. if (ret) {
  803. dev_err(dev, "adc get dt data failed\n");
  804. return ret;
  805. }
  806. irq_eoc = platform_get_irq(pdev, 0);
  807. if (irq_eoc < 0) {
  808. if (irq_eoc == -EPROBE_DEFER || irq_eoc == -EINVAL)
  809. return irq_eoc;
  810. adc->poll_eoc = true;
  811. } else {
  812. ret = devm_request_irq(dev, irq_eoc, adc5_isr, 0,
  813. "pm-adc5", adc);
  814. if (ret)
  815. return ret;
  816. }
  817. indio_dev->name = pdev->name;
  818. indio_dev->modes = INDIO_DIRECT_MODE;
  819. indio_dev->info = adc->data->info;
  820. indio_dev->channels = adc->iio_chans;
  821. indio_dev->num_channels = adc->nchannels;
  822. return devm_iio_device_register(dev, indio_dev);
  823. }
  824. static struct platform_driver adc5_driver = {
  825. .driver = {
  826. .name = "qcom-spmi-adc5",
  827. .of_match_table = adc5_match_table,
  828. },
  829. .probe = adc5_probe,
  830. };
  831. module_platform_driver(adc5_driver);
  832. MODULE_ALIAS("platform:qcom-spmi-adc5");
  833. MODULE_DESCRIPTION("Qualcomm Technologies Inc. PMIC5 ADC driver");
  834. MODULE_LICENSE("GPL v2");