palmas_gpadc.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * palmas-adc.c -- TI PALMAS GPADC.
  4. *
  5. * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
  6. *
  7. * Author: Pradeep Goudagunta <pgoudagunta@nvidia.com>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/err.h>
  11. #include <linux/irq.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/slab.h>
  15. #include <linux/delay.h>
  16. #include <linux/i2c.h>
  17. #include <linux/pm.h>
  18. #include <linux/mfd/palmas.h>
  19. #include <linux/completion.h>
  20. #include <linux/of.h>
  21. #include <linux/of_device.h>
  22. #include <linux/iio/iio.h>
  23. #include <linux/iio/machine.h>
  24. #include <linux/iio/driver.h>
  25. #define MOD_NAME "palmas-gpadc"
  26. #define PALMAS_ADC_CONVERSION_TIMEOUT (msecs_to_jiffies(5000))
  27. #define PALMAS_TO_BE_CALCULATED 0
  28. #define PALMAS_GPADC_TRIMINVALID -1
  29. struct palmas_gpadc_info {
  30. /* calibration codes and regs */
  31. int x1; /* lower ideal code */
  32. int x2; /* higher ideal code */
  33. int v1; /* expected lower volt reading */
  34. int v2; /* expected higher volt reading */
  35. u8 trim1_reg; /* register number for lower trim */
  36. u8 trim2_reg; /* register number for upper trim */
  37. int gain; /* calculated from above (after reading trim regs) */
  38. int offset; /* calculated from above (after reading trim regs) */
  39. int gain_error; /* calculated from above (after reading trim regs) */
  40. bool is_uncalibrated; /* if channel has calibration data */
  41. };
  42. #define PALMAS_ADC_INFO(_chan, _x1, _x2, _v1, _v2, _t1, _t2, _is_uncalibrated) \
  43. [PALMAS_ADC_CH_##_chan] = { \
  44. .x1 = _x1, \
  45. .x2 = _x2, \
  46. .v1 = _v1, \
  47. .v2 = _v2, \
  48. .gain = PALMAS_TO_BE_CALCULATED, \
  49. .offset = PALMAS_TO_BE_CALCULATED, \
  50. .gain_error = PALMAS_TO_BE_CALCULATED, \
  51. .trim1_reg = PALMAS_GPADC_TRIM##_t1, \
  52. .trim2_reg = PALMAS_GPADC_TRIM##_t2, \
  53. .is_uncalibrated = _is_uncalibrated \
  54. }
  55. static struct palmas_gpadc_info palmas_gpadc_info[] = {
  56. PALMAS_ADC_INFO(IN0, 2064, 3112, 630, 950, 1, 2, false),
  57. PALMAS_ADC_INFO(IN1, 2064, 3112, 630, 950, 1, 2, false),
  58. PALMAS_ADC_INFO(IN2, 2064, 3112, 1260, 1900, 3, 4, false),
  59. PALMAS_ADC_INFO(IN3, 2064, 3112, 630, 950, 1, 2, false),
  60. PALMAS_ADC_INFO(IN4, 2064, 3112, 630, 950, 1, 2, false),
  61. PALMAS_ADC_INFO(IN5, 2064, 3112, 630, 950, 1, 2, false),
  62. PALMAS_ADC_INFO(IN6, 2064, 3112, 2520, 3800, 5, 6, false),
  63. PALMAS_ADC_INFO(IN7, 2064, 3112, 2520, 3800, 7, 8, false),
  64. PALMAS_ADC_INFO(IN8, 2064, 3112, 3150, 4750, 9, 10, false),
  65. PALMAS_ADC_INFO(IN9, 2064, 3112, 5670, 8550, 11, 12, false),
  66. PALMAS_ADC_INFO(IN10, 2064, 3112, 3465, 5225, 13, 14, false),
  67. PALMAS_ADC_INFO(IN11, 0, 0, 0, 0, INVALID, INVALID, true),
  68. PALMAS_ADC_INFO(IN12, 0, 0, 0, 0, INVALID, INVALID, true),
  69. PALMAS_ADC_INFO(IN13, 0, 0, 0, 0, INVALID, INVALID, true),
  70. PALMAS_ADC_INFO(IN14, 2064, 3112, 3645, 5225, 15, 16, false),
  71. PALMAS_ADC_INFO(IN15, 0, 0, 0, 0, INVALID, INVALID, true),
  72. };
  73. /*
  74. * struct palmas_gpadc - the palmas_gpadc structure
  75. * @ch0_current: channel 0 current source setting
  76. * 0: 0 uA
  77. * 1: 5 uA
  78. * 2: 15 uA
  79. * 3: 20 uA
  80. * @ch3_current: channel 0 current source setting
  81. * 0: 0 uA
  82. * 1: 10 uA
  83. * 2: 400 uA
  84. * 3: 800 uA
  85. * @extended_delay: enable the gpadc extended delay mode
  86. * @auto_conversion_period: define the auto_conversion_period
  87. *
  88. * This is the palmas_gpadc structure to store run-time information
  89. * and pointers for this driver instance.
  90. */
  91. struct palmas_gpadc {
  92. struct device *dev;
  93. struct palmas *palmas;
  94. u8 ch0_current;
  95. u8 ch3_current;
  96. bool extended_delay;
  97. int irq;
  98. int irq_auto_0;
  99. int irq_auto_1;
  100. struct palmas_gpadc_info *adc_info;
  101. struct completion conv_completion;
  102. struct palmas_adc_wakeup_property wakeup1_data;
  103. struct palmas_adc_wakeup_property wakeup2_data;
  104. bool wakeup1_enable;
  105. bool wakeup2_enable;
  106. int auto_conversion_period;
  107. };
  108. /*
  109. * GPADC lock issue in AUTO mode.
  110. * Impact: In AUTO mode, GPADC conversion can be locked after disabling AUTO
  111. * mode feature.
  112. * Details:
  113. * When the AUTO mode is the only conversion mode enabled, if the AUTO
  114. * mode feature is disabled with bit GPADC_AUTO_CTRL. AUTO_CONV1_EN = 0
  115. * or bit GPADC_AUTO_CTRL. AUTO_CONV0_EN = 0 during a conversion, the
  116. * conversion mechanism can be seen as locked meaning that all following
  117. * conversion will give 0 as a result. Bit GPADC_STATUS.GPADC_AVAILABLE
  118. * will stay at 0 meaning that GPADC is busy. An RT conversion can unlock
  119. * the GPADC.
  120. *
  121. * Workaround(s):
  122. * To avoid the lock mechanism, the workaround to follow before any stop
  123. * conversion request is:
  124. * Force the GPADC state machine to be ON by using the GPADC_CTRL1.
  125. * GPADC_FORCE bit = 1
  126. * Shutdown the GPADC AUTO conversion using
  127. * GPADC_AUTO_CTRL.SHUTDOWN_CONV[01] = 0.
  128. * After 100us, force the GPADC state machine to be OFF by using the
  129. * GPADC_CTRL1. GPADC_FORCE bit = 0
  130. */
  131. static int palmas_disable_auto_conversion(struct palmas_gpadc *adc)
  132. {
  133. int ret;
  134. ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
  135. PALMAS_GPADC_CTRL1,
  136. PALMAS_GPADC_CTRL1_GPADC_FORCE,
  137. PALMAS_GPADC_CTRL1_GPADC_FORCE);
  138. if (ret < 0) {
  139. dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
  140. return ret;
  141. }
  142. ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
  143. PALMAS_GPADC_AUTO_CTRL,
  144. PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 |
  145. PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0,
  146. 0);
  147. if (ret < 0) {
  148. dev_err(adc->dev, "AUTO_CTRL update failed: %d\n", ret);
  149. return ret;
  150. }
  151. udelay(100);
  152. ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
  153. PALMAS_GPADC_CTRL1,
  154. PALMAS_GPADC_CTRL1_GPADC_FORCE, 0);
  155. if (ret < 0)
  156. dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
  157. return ret;
  158. }
  159. static irqreturn_t palmas_gpadc_irq(int irq, void *data)
  160. {
  161. struct palmas_gpadc *adc = data;
  162. complete(&adc->conv_completion);
  163. return IRQ_HANDLED;
  164. }
  165. static irqreturn_t palmas_gpadc_irq_auto(int irq, void *data)
  166. {
  167. struct palmas_gpadc *adc = data;
  168. dev_dbg(adc->dev, "Threshold interrupt %d occurs\n", irq);
  169. palmas_disable_auto_conversion(adc);
  170. return IRQ_HANDLED;
  171. }
  172. static int palmas_gpadc_start_mask_interrupt(struct palmas_gpadc *adc,
  173. bool mask)
  174. {
  175. int ret;
  176. if (!mask)
  177. ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
  178. PALMAS_INT3_MASK,
  179. PALMAS_INT3_MASK_GPADC_EOC_SW, 0);
  180. else
  181. ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
  182. PALMAS_INT3_MASK,
  183. PALMAS_INT3_MASK_GPADC_EOC_SW,
  184. PALMAS_INT3_MASK_GPADC_EOC_SW);
  185. if (ret < 0)
  186. dev_err(adc->dev, "GPADC INT MASK update failed: %d\n", ret);
  187. return ret;
  188. }
  189. static int palmas_gpadc_enable(struct palmas_gpadc *adc, int adc_chan,
  190. int enable)
  191. {
  192. unsigned int mask, val;
  193. int ret;
  194. if (enable) {
  195. val = (adc->extended_delay
  196. << PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT);
  197. ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
  198. PALMAS_GPADC_RT_CTRL,
  199. PALMAS_GPADC_RT_CTRL_EXTEND_DELAY, val);
  200. if (ret < 0) {
  201. dev_err(adc->dev, "RT_CTRL update failed: %d\n", ret);
  202. return ret;
  203. }
  204. mask = (PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK |
  205. PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK |
  206. PALMAS_GPADC_CTRL1_GPADC_FORCE);
  207. val = (adc->ch0_current
  208. << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT);
  209. val |= (adc->ch3_current
  210. << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT);
  211. val |= PALMAS_GPADC_CTRL1_GPADC_FORCE;
  212. ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
  213. PALMAS_GPADC_CTRL1, mask, val);
  214. if (ret < 0) {
  215. dev_err(adc->dev,
  216. "Failed to update current setting: %d\n", ret);
  217. return ret;
  218. }
  219. mask = (PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK |
  220. PALMAS_GPADC_SW_SELECT_SW_CONV_EN);
  221. val = (adc_chan | PALMAS_GPADC_SW_SELECT_SW_CONV_EN);
  222. ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
  223. PALMAS_GPADC_SW_SELECT, mask, val);
  224. if (ret < 0) {
  225. dev_err(adc->dev, "SW_SELECT update failed: %d\n", ret);
  226. return ret;
  227. }
  228. } else {
  229. ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
  230. PALMAS_GPADC_SW_SELECT, 0);
  231. if (ret < 0)
  232. dev_err(adc->dev, "SW_SELECT write failed: %d\n", ret);
  233. ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
  234. PALMAS_GPADC_CTRL1,
  235. PALMAS_GPADC_CTRL1_GPADC_FORCE, 0);
  236. if (ret < 0) {
  237. dev_err(adc->dev, "CTRL1 update failed: %d\n", ret);
  238. return ret;
  239. }
  240. }
  241. return ret;
  242. }
  243. static int palmas_gpadc_read_prepare(struct palmas_gpadc *adc, int adc_chan)
  244. {
  245. int ret;
  246. ret = palmas_gpadc_enable(adc, adc_chan, true);
  247. if (ret < 0)
  248. return ret;
  249. return palmas_gpadc_start_mask_interrupt(adc, 0);
  250. }
  251. static void palmas_gpadc_read_done(struct palmas_gpadc *adc, int adc_chan)
  252. {
  253. palmas_gpadc_start_mask_interrupt(adc, 1);
  254. palmas_gpadc_enable(adc, adc_chan, false);
  255. }
  256. static int palmas_gpadc_calibrate(struct palmas_gpadc *adc, int adc_chan)
  257. {
  258. int k;
  259. int d1;
  260. int d2;
  261. int ret;
  262. int gain;
  263. int x1 = adc->adc_info[adc_chan].x1;
  264. int x2 = adc->adc_info[adc_chan].x2;
  265. int v1 = adc->adc_info[adc_chan].v1;
  266. int v2 = adc->adc_info[adc_chan].v2;
  267. ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
  268. adc->adc_info[adc_chan].trim1_reg, &d1);
  269. if (ret < 0) {
  270. dev_err(adc->dev, "TRIM read failed: %d\n", ret);
  271. goto scrub;
  272. }
  273. ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
  274. adc->adc_info[adc_chan].trim2_reg, &d2);
  275. if (ret < 0) {
  276. dev_err(adc->dev, "TRIM read failed: %d\n", ret);
  277. goto scrub;
  278. }
  279. /* gain error calculation */
  280. k = (1000 + (1000 * (d2 - d1)) / (x2 - x1));
  281. /* gain calculation */
  282. gain = ((v2 - v1) * 1000) / (x2 - x1);
  283. adc->adc_info[adc_chan].gain_error = k;
  284. adc->adc_info[adc_chan].gain = gain;
  285. /* offset Calculation */
  286. adc->adc_info[adc_chan].offset = (d1 * 1000) - ((k - 1000) * x1);
  287. scrub:
  288. return ret;
  289. }
  290. static int palmas_gpadc_start_conversion(struct palmas_gpadc *adc, int adc_chan)
  291. {
  292. unsigned int val;
  293. int ret;
  294. init_completion(&adc->conv_completion);
  295. ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
  296. PALMAS_GPADC_SW_SELECT,
  297. PALMAS_GPADC_SW_SELECT_SW_START_CONV0,
  298. PALMAS_GPADC_SW_SELECT_SW_START_CONV0);
  299. if (ret < 0) {
  300. dev_err(adc->dev, "SELECT_SW_START write failed: %d\n", ret);
  301. return ret;
  302. }
  303. ret = wait_for_completion_timeout(&adc->conv_completion,
  304. PALMAS_ADC_CONVERSION_TIMEOUT);
  305. if (ret == 0) {
  306. dev_err(adc->dev, "conversion not completed\n");
  307. return -ETIMEDOUT;
  308. }
  309. ret = palmas_bulk_read(adc->palmas, PALMAS_GPADC_BASE,
  310. PALMAS_GPADC_SW_CONV0_LSB, &val, 2);
  311. if (ret < 0) {
  312. dev_err(adc->dev, "SW_CONV0_LSB read failed: %d\n", ret);
  313. return ret;
  314. }
  315. ret = val & 0xFFF;
  316. return ret;
  317. }
  318. static int palmas_gpadc_get_calibrated_code(struct palmas_gpadc *adc,
  319. int adc_chan, int val)
  320. {
  321. if (!adc->adc_info[adc_chan].is_uncalibrated)
  322. val = (val*1000 - adc->adc_info[adc_chan].offset) /
  323. adc->adc_info[adc_chan].gain_error;
  324. if (val < 0) {
  325. dev_err(adc->dev, "Mismatch with calibration\n");
  326. return 0;
  327. }
  328. val = (val * adc->adc_info[adc_chan].gain) / 1000;
  329. return val;
  330. }
  331. static int palmas_gpadc_read_raw(struct iio_dev *indio_dev,
  332. struct iio_chan_spec const *chan, int *val, int *val2, long mask)
  333. {
  334. struct palmas_gpadc *adc = iio_priv(indio_dev);
  335. int adc_chan = chan->channel;
  336. int ret = 0;
  337. if (adc_chan > PALMAS_ADC_CH_MAX)
  338. return -EINVAL;
  339. mutex_lock(&indio_dev->mlock);
  340. switch (mask) {
  341. case IIO_CHAN_INFO_RAW:
  342. case IIO_CHAN_INFO_PROCESSED:
  343. ret = palmas_gpadc_read_prepare(adc, adc_chan);
  344. if (ret < 0)
  345. goto out;
  346. ret = palmas_gpadc_start_conversion(adc, adc_chan);
  347. if (ret < 0) {
  348. dev_err(adc->dev,
  349. "ADC start conversion failed\n");
  350. goto out;
  351. }
  352. if (mask == IIO_CHAN_INFO_PROCESSED)
  353. ret = palmas_gpadc_get_calibrated_code(
  354. adc, adc_chan, ret);
  355. *val = ret;
  356. ret = IIO_VAL_INT;
  357. goto out;
  358. }
  359. mutex_unlock(&indio_dev->mlock);
  360. return ret;
  361. out:
  362. palmas_gpadc_read_done(adc, adc_chan);
  363. mutex_unlock(&indio_dev->mlock);
  364. return ret;
  365. }
  366. static const struct iio_info palmas_gpadc_iio_info = {
  367. .read_raw = palmas_gpadc_read_raw,
  368. };
  369. #define PALMAS_ADC_CHAN_IIO(chan, _type, chan_info) \
  370. { \
  371. .datasheet_name = PALMAS_DATASHEET_NAME(chan), \
  372. .type = _type, \
  373. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  374. BIT(chan_info), \
  375. .indexed = 1, \
  376. .channel = PALMAS_ADC_CH_##chan, \
  377. }
  378. static const struct iio_chan_spec palmas_gpadc_iio_channel[] = {
  379. PALMAS_ADC_CHAN_IIO(IN0, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
  380. PALMAS_ADC_CHAN_IIO(IN1, IIO_TEMP, IIO_CHAN_INFO_RAW),
  381. PALMAS_ADC_CHAN_IIO(IN2, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
  382. PALMAS_ADC_CHAN_IIO(IN3, IIO_TEMP, IIO_CHAN_INFO_RAW),
  383. PALMAS_ADC_CHAN_IIO(IN4, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
  384. PALMAS_ADC_CHAN_IIO(IN5, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
  385. PALMAS_ADC_CHAN_IIO(IN6, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
  386. PALMAS_ADC_CHAN_IIO(IN7, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
  387. PALMAS_ADC_CHAN_IIO(IN8, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
  388. PALMAS_ADC_CHAN_IIO(IN9, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
  389. PALMAS_ADC_CHAN_IIO(IN10, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
  390. PALMAS_ADC_CHAN_IIO(IN11, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
  391. PALMAS_ADC_CHAN_IIO(IN12, IIO_TEMP, IIO_CHAN_INFO_RAW),
  392. PALMAS_ADC_CHAN_IIO(IN13, IIO_TEMP, IIO_CHAN_INFO_RAW),
  393. PALMAS_ADC_CHAN_IIO(IN14, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
  394. PALMAS_ADC_CHAN_IIO(IN15, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
  395. };
  396. static int palmas_gpadc_get_adc_dt_data(struct platform_device *pdev,
  397. struct palmas_gpadc_platform_data **gpadc_pdata)
  398. {
  399. struct device_node *np = pdev->dev.of_node;
  400. struct palmas_gpadc_platform_data *gp_data;
  401. int ret;
  402. u32 pval;
  403. gp_data = devm_kzalloc(&pdev->dev, sizeof(*gp_data), GFP_KERNEL);
  404. if (!gp_data)
  405. return -ENOMEM;
  406. ret = of_property_read_u32(np, "ti,channel0-current-microamp", &pval);
  407. if (!ret)
  408. gp_data->ch0_current = pval;
  409. ret = of_property_read_u32(np, "ti,channel3-current-microamp", &pval);
  410. if (!ret)
  411. gp_data->ch3_current = pval;
  412. gp_data->extended_delay = of_property_read_bool(np,
  413. "ti,enable-extended-delay");
  414. *gpadc_pdata = gp_data;
  415. return 0;
  416. }
  417. static int palmas_gpadc_probe(struct platform_device *pdev)
  418. {
  419. struct palmas_gpadc *adc;
  420. struct palmas_platform_data *pdata;
  421. struct palmas_gpadc_platform_data *gpadc_pdata = NULL;
  422. struct iio_dev *indio_dev;
  423. int ret, i;
  424. pdata = dev_get_platdata(pdev->dev.parent);
  425. if (pdata && pdata->gpadc_pdata)
  426. gpadc_pdata = pdata->gpadc_pdata;
  427. if (!gpadc_pdata && pdev->dev.of_node) {
  428. ret = palmas_gpadc_get_adc_dt_data(pdev, &gpadc_pdata);
  429. if (ret < 0)
  430. return ret;
  431. }
  432. if (!gpadc_pdata)
  433. return -EINVAL;
  434. indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
  435. if (!indio_dev) {
  436. dev_err(&pdev->dev, "iio_device_alloc failed\n");
  437. return -ENOMEM;
  438. }
  439. adc = iio_priv(indio_dev);
  440. adc->dev = &pdev->dev;
  441. adc->palmas = dev_get_drvdata(pdev->dev.parent);
  442. adc->adc_info = palmas_gpadc_info;
  443. init_completion(&adc->conv_completion);
  444. dev_set_drvdata(&pdev->dev, indio_dev);
  445. adc->auto_conversion_period = gpadc_pdata->auto_conversion_period_ms;
  446. adc->irq = palmas_irq_get_virq(adc->palmas, PALMAS_GPADC_EOC_SW_IRQ);
  447. if (adc->irq < 0) {
  448. dev_err(adc->dev,
  449. "get virq failed: %d\n", adc->irq);
  450. ret = adc->irq;
  451. goto out;
  452. }
  453. ret = request_threaded_irq(adc->irq, NULL,
  454. palmas_gpadc_irq,
  455. IRQF_ONESHOT, dev_name(adc->dev),
  456. adc);
  457. if (ret < 0) {
  458. dev_err(adc->dev,
  459. "request irq %d failed: %d\n", adc->irq, ret);
  460. goto out;
  461. }
  462. if (gpadc_pdata->adc_wakeup1_data) {
  463. memcpy(&adc->wakeup1_data, gpadc_pdata->adc_wakeup1_data,
  464. sizeof(adc->wakeup1_data));
  465. adc->wakeup1_enable = true;
  466. adc->irq_auto_0 = platform_get_irq(pdev, 1);
  467. ret = request_threaded_irq(adc->irq_auto_0, NULL,
  468. palmas_gpadc_irq_auto,
  469. IRQF_ONESHOT,
  470. "palmas-adc-auto-0", adc);
  471. if (ret < 0) {
  472. dev_err(adc->dev, "request auto0 irq %d failed: %d\n",
  473. adc->irq_auto_0, ret);
  474. goto out_irq_free;
  475. }
  476. }
  477. if (gpadc_pdata->adc_wakeup2_data) {
  478. memcpy(&adc->wakeup2_data, gpadc_pdata->adc_wakeup2_data,
  479. sizeof(adc->wakeup2_data));
  480. adc->wakeup2_enable = true;
  481. adc->irq_auto_1 = platform_get_irq(pdev, 2);
  482. ret = request_threaded_irq(adc->irq_auto_1, NULL,
  483. palmas_gpadc_irq_auto,
  484. IRQF_ONESHOT,
  485. "palmas-adc-auto-1", adc);
  486. if (ret < 0) {
  487. dev_err(adc->dev, "request auto1 irq %d failed: %d\n",
  488. adc->irq_auto_1, ret);
  489. goto out_irq_auto0_free;
  490. }
  491. }
  492. /* set the current source 0 (value 0/5/15/20 uA => 0..3) */
  493. if (gpadc_pdata->ch0_current <= 1)
  494. adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_0;
  495. else if (gpadc_pdata->ch0_current <= 5)
  496. adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_5;
  497. else if (gpadc_pdata->ch0_current <= 15)
  498. adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_15;
  499. else
  500. adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_20;
  501. /* set the current source 3 (value 0/10/400/800 uA => 0..3) */
  502. if (gpadc_pdata->ch3_current <= 1)
  503. adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_0;
  504. else if (gpadc_pdata->ch3_current <= 10)
  505. adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_10;
  506. else if (gpadc_pdata->ch3_current <= 400)
  507. adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_400;
  508. else
  509. adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_800;
  510. adc->extended_delay = gpadc_pdata->extended_delay;
  511. indio_dev->name = MOD_NAME;
  512. indio_dev->info = &palmas_gpadc_iio_info;
  513. indio_dev->modes = INDIO_DIRECT_MODE;
  514. indio_dev->channels = palmas_gpadc_iio_channel;
  515. indio_dev->num_channels = ARRAY_SIZE(palmas_gpadc_iio_channel);
  516. ret = iio_device_register(indio_dev);
  517. if (ret < 0) {
  518. dev_err(adc->dev, "iio_device_register() failed: %d\n", ret);
  519. goto out_irq_auto1_free;
  520. }
  521. device_set_wakeup_capable(&pdev->dev, 1);
  522. for (i = 0; i < PALMAS_ADC_CH_MAX; i++) {
  523. if (!(adc->adc_info[i].is_uncalibrated))
  524. palmas_gpadc_calibrate(adc, i);
  525. }
  526. if (adc->wakeup1_enable || adc->wakeup2_enable)
  527. device_wakeup_enable(&pdev->dev);
  528. return 0;
  529. out_irq_auto1_free:
  530. if (gpadc_pdata->adc_wakeup2_data)
  531. free_irq(adc->irq_auto_1, adc);
  532. out_irq_auto0_free:
  533. if (gpadc_pdata->adc_wakeup1_data)
  534. free_irq(adc->irq_auto_0, adc);
  535. out_irq_free:
  536. free_irq(adc->irq, adc);
  537. out:
  538. return ret;
  539. }
  540. static int palmas_gpadc_remove(struct platform_device *pdev)
  541. {
  542. struct iio_dev *indio_dev = dev_to_iio_dev(&pdev->dev);
  543. struct palmas_gpadc *adc = iio_priv(indio_dev);
  544. if (adc->wakeup1_enable || adc->wakeup2_enable)
  545. device_wakeup_disable(&pdev->dev);
  546. iio_device_unregister(indio_dev);
  547. free_irq(adc->irq, adc);
  548. if (adc->wakeup1_enable)
  549. free_irq(adc->irq_auto_0, adc);
  550. if (adc->wakeup2_enable)
  551. free_irq(adc->irq_auto_1, adc);
  552. return 0;
  553. }
  554. #ifdef CONFIG_PM_SLEEP
  555. static int palmas_adc_wakeup_configure(struct palmas_gpadc *adc)
  556. {
  557. int adc_period, conv;
  558. int i;
  559. int ch0 = 0, ch1 = 0;
  560. int thres;
  561. int ret;
  562. adc_period = adc->auto_conversion_period;
  563. for (i = 0; i < 16; ++i) {
  564. if (((1000 * (1 << i)) / 32) >= adc_period)
  565. break;
  566. }
  567. if (i > 0)
  568. i--;
  569. adc_period = i;
  570. ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
  571. PALMAS_GPADC_AUTO_CTRL,
  572. PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK,
  573. adc_period);
  574. if (ret < 0) {
  575. dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
  576. return ret;
  577. }
  578. conv = 0;
  579. if (adc->wakeup1_enable) {
  580. int polarity;
  581. ch0 = adc->wakeup1_data.adc_channel_number;
  582. conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN;
  583. if (adc->wakeup1_data.adc_high_threshold > 0) {
  584. thres = adc->wakeup1_data.adc_high_threshold;
  585. polarity = 0;
  586. } else {
  587. thres = adc->wakeup1_data.adc_low_threshold;
  588. polarity = PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL;
  589. }
  590. ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
  591. PALMAS_GPADC_THRES_CONV0_LSB, thres & 0xFF);
  592. if (ret < 0) {
  593. dev_err(adc->dev,
  594. "THRES_CONV0_LSB write failed: %d\n", ret);
  595. return ret;
  596. }
  597. ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
  598. PALMAS_GPADC_THRES_CONV0_MSB,
  599. ((thres >> 8) & 0xF) | polarity);
  600. if (ret < 0) {
  601. dev_err(adc->dev,
  602. "THRES_CONV0_MSB write failed: %d\n", ret);
  603. return ret;
  604. }
  605. }
  606. if (adc->wakeup2_enable) {
  607. int polarity;
  608. ch1 = adc->wakeup2_data.adc_channel_number;
  609. conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN;
  610. if (adc->wakeup2_data.adc_high_threshold > 0) {
  611. thres = adc->wakeup2_data.adc_high_threshold;
  612. polarity = 0;
  613. } else {
  614. thres = adc->wakeup2_data.adc_low_threshold;
  615. polarity = PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL;
  616. }
  617. ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
  618. PALMAS_GPADC_THRES_CONV1_LSB, thres & 0xFF);
  619. if (ret < 0) {
  620. dev_err(adc->dev,
  621. "THRES_CONV1_LSB write failed: %d\n", ret);
  622. return ret;
  623. }
  624. ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
  625. PALMAS_GPADC_THRES_CONV1_MSB,
  626. ((thres >> 8) & 0xF) | polarity);
  627. if (ret < 0) {
  628. dev_err(adc->dev,
  629. "THRES_CONV1_MSB write failed: %d\n", ret);
  630. return ret;
  631. }
  632. }
  633. ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
  634. PALMAS_GPADC_AUTO_SELECT, (ch1 << 4) | ch0);
  635. if (ret < 0) {
  636. dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
  637. return ret;
  638. }
  639. ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
  640. PALMAS_GPADC_AUTO_CTRL,
  641. PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN |
  642. PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN, conv);
  643. if (ret < 0)
  644. dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
  645. return ret;
  646. }
  647. static int palmas_adc_wakeup_reset(struct palmas_gpadc *adc)
  648. {
  649. int ret;
  650. ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
  651. PALMAS_GPADC_AUTO_SELECT, 0);
  652. if (ret < 0) {
  653. dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
  654. return ret;
  655. }
  656. ret = palmas_disable_auto_conversion(adc);
  657. if (ret < 0)
  658. dev_err(adc->dev, "Disable auto conversion failed: %d\n", ret);
  659. return ret;
  660. }
  661. static int palmas_gpadc_suspend(struct device *dev)
  662. {
  663. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  664. struct palmas_gpadc *adc = iio_priv(indio_dev);
  665. int wakeup = adc->wakeup1_enable || adc->wakeup2_enable;
  666. int ret;
  667. if (!device_may_wakeup(dev) || !wakeup)
  668. return 0;
  669. ret = palmas_adc_wakeup_configure(adc);
  670. if (ret < 0)
  671. return ret;
  672. if (adc->wakeup1_enable)
  673. enable_irq_wake(adc->irq_auto_0);
  674. if (adc->wakeup2_enable)
  675. enable_irq_wake(adc->irq_auto_1);
  676. return 0;
  677. }
  678. static int palmas_gpadc_resume(struct device *dev)
  679. {
  680. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  681. struct palmas_gpadc *adc = iio_priv(indio_dev);
  682. int wakeup = adc->wakeup1_enable || adc->wakeup2_enable;
  683. int ret;
  684. if (!device_may_wakeup(dev) || !wakeup)
  685. return 0;
  686. ret = palmas_adc_wakeup_reset(adc);
  687. if (ret < 0)
  688. return ret;
  689. if (adc->wakeup1_enable)
  690. disable_irq_wake(adc->irq_auto_0);
  691. if (adc->wakeup2_enable)
  692. disable_irq_wake(adc->irq_auto_1);
  693. return 0;
  694. };
  695. #endif
  696. static const struct dev_pm_ops palmas_pm_ops = {
  697. SET_SYSTEM_SLEEP_PM_OPS(palmas_gpadc_suspend,
  698. palmas_gpadc_resume)
  699. };
  700. static const struct of_device_id of_palmas_gpadc_match_tbl[] = {
  701. { .compatible = "ti,palmas-gpadc", },
  702. { /* end */ }
  703. };
  704. MODULE_DEVICE_TABLE(of, of_palmas_gpadc_match_tbl);
  705. static struct platform_driver palmas_gpadc_driver = {
  706. .probe = palmas_gpadc_probe,
  707. .remove = palmas_gpadc_remove,
  708. .driver = {
  709. .name = MOD_NAME,
  710. .pm = &palmas_pm_ops,
  711. .of_match_table = of_palmas_gpadc_match_tbl,
  712. },
  713. };
  714. module_platform_driver(palmas_gpadc_driver);
  715. MODULE_DESCRIPTION("palmas GPADC driver");
  716. MODULE_AUTHOR("Pradeep Goudagunta<pgoudagunta@nvidia.com>");
  717. MODULE_ALIAS("platform:palmas-gpadc");
  718. MODULE_LICENSE("GPL v2");