npcm_adc.c 7.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2019 Nuvoton Technology corporation.
  3. #include <linux/clk.h>
  4. #include <linux/device.h>
  5. #include <linux/mfd/syscon.h>
  6. #include <linux/io.h>
  7. #include <linux/iio/iio.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/regmap.h>
  13. #include <linux/regulator/consumer.h>
  14. #include <linux/spinlock.h>
  15. #include <linux/uaccess.h>
  16. #include <linux/reset.h>
  17. struct npcm_adc {
  18. bool int_status;
  19. u32 adc_sample_hz;
  20. struct device *dev;
  21. void __iomem *regs;
  22. struct clk *adc_clk;
  23. wait_queue_head_t wq;
  24. struct regulator *vref;
  25. struct reset_control *reset;
  26. };
  27. /* ADC registers */
  28. #define NPCM_ADCCON 0x00
  29. #define NPCM_ADCDATA 0x04
  30. /* ADCCON Register Bits */
  31. #define NPCM_ADCCON_ADC_INT_EN BIT(21)
  32. #define NPCM_ADCCON_REFSEL BIT(19)
  33. #define NPCM_ADCCON_ADC_INT_ST BIT(18)
  34. #define NPCM_ADCCON_ADC_EN BIT(17)
  35. #define NPCM_ADCCON_ADC_RST BIT(16)
  36. #define NPCM_ADCCON_ADC_CONV BIT(13)
  37. #define NPCM_ADCCON_CH_MASK GENMASK(27, 24)
  38. #define NPCM_ADCCON_CH(x) ((x) << 24)
  39. #define NPCM_ADCCON_DIV_SHIFT 1
  40. #define NPCM_ADCCON_DIV_MASK GENMASK(8, 1)
  41. #define NPCM_ADC_DATA_MASK(x) ((x) & GENMASK(9, 0))
  42. #define NPCM_ADC_ENABLE (NPCM_ADCCON_ADC_EN | NPCM_ADCCON_ADC_INT_EN)
  43. /* ADC General Definition */
  44. #define NPCM_RESOLUTION_BITS 10
  45. #define NPCM_INT_VREF_MV 2000
  46. #define NPCM_ADC_CHAN(ch) { \
  47. .type = IIO_VOLTAGE, \
  48. .indexed = 1, \
  49. .channel = ch, \
  50. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  51. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
  52. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  53. }
  54. static const struct iio_chan_spec npcm_adc_iio_channels[] = {
  55. NPCM_ADC_CHAN(0),
  56. NPCM_ADC_CHAN(1),
  57. NPCM_ADC_CHAN(2),
  58. NPCM_ADC_CHAN(3),
  59. NPCM_ADC_CHAN(4),
  60. NPCM_ADC_CHAN(5),
  61. NPCM_ADC_CHAN(6),
  62. NPCM_ADC_CHAN(7),
  63. };
  64. static irqreturn_t npcm_adc_isr(int irq, void *data)
  65. {
  66. u32 regtemp;
  67. struct iio_dev *indio_dev = data;
  68. struct npcm_adc *info = iio_priv(indio_dev);
  69. regtemp = ioread32(info->regs + NPCM_ADCCON);
  70. if (regtemp & NPCM_ADCCON_ADC_INT_ST) {
  71. iowrite32(regtemp, info->regs + NPCM_ADCCON);
  72. wake_up_interruptible(&info->wq);
  73. info->int_status = true;
  74. }
  75. return IRQ_HANDLED;
  76. }
  77. static int npcm_adc_read(struct npcm_adc *info, int *val, u8 channel)
  78. {
  79. int ret;
  80. u32 regtemp;
  81. /* Select ADC channel */
  82. regtemp = ioread32(info->regs + NPCM_ADCCON);
  83. regtemp &= ~NPCM_ADCCON_CH_MASK;
  84. info->int_status = false;
  85. iowrite32(regtemp | NPCM_ADCCON_CH(channel) |
  86. NPCM_ADCCON_ADC_CONV, info->regs + NPCM_ADCCON);
  87. ret = wait_event_interruptible_timeout(info->wq, info->int_status,
  88. msecs_to_jiffies(10));
  89. if (ret == 0) {
  90. regtemp = ioread32(info->regs + NPCM_ADCCON);
  91. if (regtemp & NPCM_ADCCON_ADC_CONV) {
  92. /* if conversion failed - reset ADC module */
  93. reset_control_assert(info->reset);
  94. msleep(100);
  95. reset_control_deassert(info->reset);
  96. msleep(100);
  97. /* Enable ADC and start conversion module */
  98. iowrite32(NPCM_ADC_ENABLE | NPCM_ADCCON_ADC_CONV,
  99. info->regs + NPCM_ADCCON);
  100. dev_err(info->dev, "RESET ADC Complete\n");
  101. }
  102. return -ETIMEDOUT;
  103. }
  104. if (ret < 0)
  105. return ret;
  106. *val = NPCM_ADC_DATA_MASK(ioread32(info->regs + NPCM_ADCDATA));
  107. return 0;
  108. }
  109. static int npcm_adc_read_raw(struct iio_dev *indio_dev,
  110. struct iio_chan_spec const *chan, int *val,
  111. int *val2, long mask)
  112. {
  113. int ret;
  114. int vref_uv;
  115. struct npcm_adc *info = iio_priv(indio_dev);
  116. switch (mask) {
  117. case IIO_CHAN_INFO_RAW:
  118. mutex_lock(&indio_dev->mlock);
  119. ret = npcm_adc_read(info, val, chan->channel);
  120. mutex_unlock(&indio_dev->mlock);
  121. if (ret) {
  122. dev_err(info->dev, "NPCM ADC read failed\n");
  123. return ret;
  124. }
  125. return IIO_VAL_INT;
  126. case IIO_CHAN_INFO_SCALE:
  127. if (!IS_ERR(info->vref)) {
  128. vref_uv = regulator_get_voltage(info->vref);
  129. *val = vref_uv / 1000;
  130. } else {
  131. *val = NPCM_INT_VREF_MV;
  132. }
  133. *val2 = NPCM_RESOLUTION_BITS;
  134. return IIO_VAL_FRACTIONAL_LOG2;
  135. case IIO_CHAN_INFO_SAMP_FREQ:
  136. *val = info->adc_sample_hz;
  137. return IIO_VAL_INT;
  138. default:
  139. return -EINVAL;
  140. }
  141. return 0;
  142. }
  143. static const struct iio_info npcm_adc_iio_info = {
  144. .read_raw = &npcm_adc_read_raw,
  145. };
  146. static const struct of_device_id npcm_adc_match[] = {
  147. { .compatible = "nuvoton,npcm750-adc", },
  148. { /* sentinel */ }
  149. };
  150. MODULE_DEVICE_TABLE(of, npcm_adc_match);
  151. static int npcm_adc_probe(struct platform_device *pdev)
  152. {
  153. int ret;
  154. int irq;
  155. u32 div;
  156. u32 reg_con;
  157. struct npcm_adc *info;
  158. struct iio_dev *indio_dev;
  159. struct device *dev = &pdev->dev;
  160. indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
  161. if (!indio_dev)
  162. return -ENOMEM;
  163. info = iio_priv(indio_dev);
  164. info->dev = &pdev->dev;
  165. info->regs = devm_platform_ioremap_resource(pdev, 0);
  166. if (IS_ERR(info->regs))
  167. return PTR_ERR(info->regs);
  168. info->reset = devm_reset_control_get(&pdev->dev, NULL);
  169. if (IS_ERR(info->reset))
  170. return PTR_ERR(info->reset);
  171. info->adc_clk = devm_clk_get(&pdev->dev, NULL);
  172. if (IS_ERR(info->adc_clk)) {
  173. dev_warn(&pdev->dev, "ADC clock failed: can't read clk\n");
  174. return PTR_ERR(info->adc_clk);
  175. }
  176. /* calculate ADC clock sample rate */
  177. reg_con = ioread32(info->regs + NPCM_ADCCON);
  178. div = reg_con & NPCM_ADCCON_DIV_MASK;
  179. div = div >> NPCM_ADCCON_DIV_SHIFT;
  180. info->adc_sample_hz = clk_get_rate(info->adc_clk) / ((div + 1) * 2);
  181. irq = platform_get_irq(pdev, 0);
  182. if (irq <= 0) {
  183. ret = -EINVAL;
  184. goto err_disable_clk;
  185. }
  186. ret = devm_request_irq(&pdev->dev, irq, npcm_adc_isr, 0,
  187. "NPCM_ADC", indio_dev);
  188. if (ret < 0) {
  189. dev_err(dev, "failed requesting interrupt\n");
  190. goto err_disable_clk;
  191. }
  192. reg_con = ioread32(info->regs + NPCM_ADCCON);
  193. info->vref = devm_regulator_get_optional(&pdev->dev, "vref");
  194. if (!IS_ERR(info->vref)) {
  195. ret = regulator_enable(info->vref);
  196. if (ret) {
  197. dev_err(&pdev->dev, "Can't enable ADC reference voltage\n");
  198. goto err_disable_clk;
  199. }
  200. iowrite32(reg_con & ~NPCM_ADCCON_REFSEL,
  201. info->regs + NPCM_ADCCON);
  202. } else {
  203. /*
  204. * Any error which is not ENODEV indicates the regulator
  205. * has been specified and so is a failure case.
  206. */
  207. if (PTR_ERR(info->vref) != -ENODEV) {
  208. ret = PTR_ERR(info->vref);
  209. goto err_disable_clk;
  210. }
  211. /* Use internal reference */
  212. iowrite32(reg_con | NPCM_ADCCON_REFSEL,
  213. info->regs + NPCM_ADCCON);
  214. }
  215. init_waitqueue_head(&info->wq);
  216. reg_con = ioread32(info->regs + NPCM_ADCCON);
  217. reg_con |= NPCM_ADC_ENABLE;
  218. /* Enable the ADC Module */
  219. iowrite32(reg_con, info->regs + NPCM_ADCCON);
  220. /* Start ADC conversion */
  221. iowrite32(reg_con | NPCM_ADCCON_ADC_CONV, info->regs + NPCM_ADCCON);
  222. platform_set_drvdata(pdev, indio_dev);
  223. indio_dev->name = dev_name(&pdev->dev);
  224. indio_dev->info = &npcm_adc_iio_info;
  225. indio_dev->modes = INDIO_DIRECT_MODE;
  226. indio_dev->channels = npcm_adc_iio_channels;
  227. indio_dev->num_channels = ARRAY_SIZE(npcm_adc_iio_channels);
  228. ret = iio_device_register(indio_dev);
  229. if (ret) {
  230. dev_err(&pdev->dev, "Couldn't register the device.\n");
  231. goto err_iio_register;
  232. }
  233. pr_info("NPCM ADC driver probed\n");
  234. return 0;
  235. err_iio_register:
  236. iowrite32(reg_con & ~NPCM_ADCCON_ADC_EN, info->regs + NPCM_ADCCON);
  237. if (!IS_ERR(info->vref))
  238. regulator_disable(info->vref);
  239. err_disable_clk:
  240. clk_disable_unprepare(info->adc_clk);
  241. return ret;
  242. }
  243. static int npcm_adc_remove(struct platform_device *pdev)
  244. {
  245. struct iio_dev *indio_dev = platform_get_drvdata(pdev);
  246. struct npcm_adc *info = iio_priv(indio_dev);
  247. u32 regtemp;
  248. iio_device_unregister(indio_dev);
  249. regtemp = ioread32(info->regs + NPCM_ADCCON);
  250. iowrite32(regtemp & ~NPCM_ADCCON_ADC_EN, info->regs + NPCM_ADCCON);
  251. if (!IS_ERR(info->vref))
  252. regulator_disable(info->vref);
  253. clk_disable_unprepare(info->adc_clk);
  254. return 0;
  255. }
  256. static struct platform_driver npcm_adc_driver = {
  257. .probe = npcm_adc_probe,
  258. .remove = npcm_adc_remove,
  259. .driver = {
  260. .name = "npcm_adc",
  261. .of_match_table = npcm_adc_match,
  262. },
  263. };
  264. module_platform_driver(npcm_adc_driver);
  265. MODULE_DESCRIPTION("Nuvoton NPCM ADC Driver");
  266. MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
  267. MODULE_LICENSE("GPL v2");