nau7802.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for the Nuvoton NAU7802 ADC
  4. *
  5. * Copyright 2013 Free Electrons
  6. */
  7. #include <linux/delay.h>
  8. #include <linux/i2c.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/module.h>
  11. #include <linux/wait.h>
  12. #include <linux/log2.h>
  13. #include <linux/of.h>
  14. #include <linux/iio/iio.h>
  15. #include <linux/iio/sysfs.h>
  16. #define NAU7802_REG_PUCTRL 0x00
  17. #define NAU7802_PUCTRL_RR(x) (x << 0)
  18. #define NAU7802_PUCTRL_RR_BIT NAU7802_PUCTRL_RR(1)
  19. #define NAU7802_PUCTRL_PUD(x) (x << 1)
  20. #define NAU7802_PUCTRL_PUD_BIT NAU7802_PUCTRL_PUD(1)
  21. #define NAU7802_PUCTRL_PUA(x) (x << 2)
  22. #define NAU7802_PUCTRL_PUA_BIT NAU7802_PUCTRL_PUA(1)
  23. #define NAU7802_PUCTRL_PUR(x) (x << 3)
  24. #define NAU7802_PUCTRL_PUR_BIT NAU7802_PUCTRL_PUR(1)
  25. #define NAU7802_PUCTRL_CS(x) (x << 4)
  26. #define NAU7802_PUCTRL_CS_BIT NAU7802_PUCTRL_CS(1)
  27. #define NAU7802_PUCTRL_CR(x) (x << 5)
  28. #define NAU7802_PUCTRL_CR_BIT NAU7802_PUCTRL_CR(1)
  29. #define NAU7802_PUCTRL_AVDDS(x) (x << 7)
  30. #define NAU7802_PUCTRL_AVDDS_BIT NAU7802_PUCTRL_AVDDS(1)
  31. #define NAU7802_REG_CTRL1 0x01
  32. #define NAU7802_CTRL1_VLDO(x) (x << 3)
  33. #define NAU7802_CTRL1_GAINS(x) (x)
  34. #define NAU7802_CTRL1_GAINS_BITS 0x07
  35. #define NAU7802_REG_CTRL2 0x02
  36. #define NAU7802_CTRL2_CHS(x) (x << 7)
  37. #define NAU7802_CTRL2_CRS(x) (x << 4)
  38. #define NAU7802_SAMP_FREQ_320 0x07
  39. #define NAU7802_CTRL2_CHS_BIT NAU7802_CTRL2_CHS(1)
  40. #define NAU7802_REG_ADC_B2 0x12
  41. #define NAU7802_REG_ADC_B1 0x13
  42. #define NAU7802_REG_ADC_B0 0x14
  43. #define NAU7802_REG_ADC_CTRL 0x15
  44. #define NAU7802_MIN_CONVERSIONS 6
  45. struct nau7802_state {
  46. struct i2c_client *client;
  47. s32 last_value;
  48. struct mutex lock;
  49. struct mutex data_lock;
  50. u32 vref_mv;
  51. u32 conversion_count;
  52. u32 min_conversions;
  53. u8 sample_rate;
  54. u32 scale_avail[8];
  55. struct completion value_ok;
  56. };
  57. #define NAU7802_CHANNEL(chan) { \
  58. .type = IIO_VOLTAGE, \
  59. .indexed = 1, \
  60. .channel = (chan), \
  61. .scan_index = (chan), \
  62. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  63. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
  64. BIT(IIO_CHAN_INFO_SAMP_FREQ) \
  65. }
  66. static const struct iio_chan_spec nau7802_chan_array[] = {
  67. NAU7802_CHANNEL(0),
  68. NAU7802_CHANNEL(1),
  69. };
  70. static const u16 nau7802_sample_freq_avail[] = {10, 20, 40, 80,
  71. 10, 10, 10, 320};
  72. static ssize_t nau7802_show_scales(struct device *dev,
  73. struct device_attribute *attr, char *buf)
  74. {
  75. struct nau7802_state *st = iio_priv(dev_to_iio_dev(dev));
  76. int i, len = 0;
  77. for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
  78. len += scnprintf(buf + len, PAGE_SIZE - len, "0.%09d ",
  79. st->scale_avail[i]);
  80. buf[len-1] = '\n';
  81. return len;
  82. }
  83. static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 40 80 320");
  84. static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO, nau7802_show_scales,
  85. NULL, 0);
  86. static struct attribute *nau7802_attributes[] = {
  87. &iio_const_attr_sampling_frequency_available.dev_attr.attr,
  88. &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
  89. NULL
  90. };
  91. static const struct attribute_group nau7802_attribute_group = {
  92. .attrs = nau7802_attributes,
  93. };
  94. static int nau7802_set_gain(struct nau7802_state *st, int gain)
  95. {
  96. int ret;
  97. mutex_lock(&st->lock);
  98. st->conversion_count = 0;
  99. ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1);
  100. if (ret < 0)
  101. goto nau7802_sysfs_set_gain_out;
  102. ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1,
  103. (ret & (~NAU7802_CTRL1_GAINS_BITS)) |
  104. gain);
  105. nau7802_sysfs_set_gain_out:
  106. mutex_unlock(&st->lock);
  107. return ret;
  108. }
  109. static int nau7802_read_conversion(struct nau7802_state *st)
  110. {
  111. int data;
  112. mutex_lock(&st->data_lock);
  113. data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B2);
  114. if (data < 0)
  115. goto nau7802_read_conversion_out;
  116. st->last_value = data << 16;
  117. data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B1);
  118. if (data < 0)
  119. goto nau7802_read_conversion_out;
  120. st->last_value |= data << 8;
  121. data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B0);
  122. if (data < 0)
  123. goto nau7802_read_conversion_out;
  124. st->last_value |= data;
  125. st->last_value = sign_extend32(st->last_value, 23);
  126. nau7802_read_conversion_out:
  127. mutex_unlock(&st->data_lock);
  128. return data;
  129. }
  130. /*
  131. * Conversions are synchronised on the rising edge of NAU7802_PUCTRL_CS_BIT
  132. */
  133. static int nau7802_sync(struct nau7802_state *st)
  134. {
  135. int ret;
  136. ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
  137. if (ret < 0)
  138. return ret;
  139. ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
  140. ret | NAU7802_PUCTRL_CS_BIT);
  141. return ret;
  142. }
  143. static irqreturn_t nau7802_eoc_trigger(int irq, void *private)
  144. {
  145. struct iio_dev *indio_dev = private;
  146. struct nau7802_state *st = iio_priv(indio_dev);
  147. int status;
  148. status = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
  149. if (status < 0)
  150. return IRQ_HANDLED;
  151. if (!(status & NAU7802_PUCTRL_CR_BIT))
  152. return IRQ_NONE;
  153. if (nau7802_read_conversion(st) < 0)
  154. return IRQ_HANDLED;
  155. /*
  156. * Because there is actually only one ADC for both channels, we have to
  157. * wait for enough conversions to happen before getting a significant
  158. * value when changing channels and the values are far apart.
  159. */
  160. if (st->conversion_count < NAU7802_MIN_CONVERSIONS)
  161. st->conversion_count++;
  162. if (st->conversion_count >= NAU7802_MIN_CONVERSIONS)
  163. complete(&st->value_ok);
  164. return IRQ_HANDLED;
  165. }
  166. static int nau7802_read_irq(struct iio_dev *indio_dev,
  167. struct iio_chan_spec const *chan,
  168. int *val)
  169. {
  170. struct nau7802_state *st = iio_priv(indio_dev);
  171. int ret;
  172. reinit_completion(&st->value_ok);
  173. enable_irq(st->client->irq);
  174. nau7802_sync(st);
  175. /* read registers to ensure we flush everything */
  176. ret = nau7802_read_conversion(st);
  177. if (ret < 0)
  178. goto read_chan_info_failure;
  179. /* Wait for a conversion to finish */
  180. ret = wait_for_completion_interruptible_timeout(&st->value_ok,
  181. msecs_to_jiffies(1000));
  182. if (ret == 0)
  183. ret = -ETIMEDOUT;
  184. if (ret < 0)
  185. goto read_chan_info_failure;
  186. disable_irq(st->client->irq);
  187. *val = st->last_value;
  188. return IIO_VAL_INT;
  189. read_chan_info_failure:
  190. disable_irq(st->client->irq);
  191. return ret;
  192. }
  193. static int nau7802_read_poll(struct iio_dev *indio_dev,
  194. struct iio_chan_spec const *chan,
  195. int *val)
  196. {
  197. struct nau7802_state *st = iio_priv(indio_dev);
  198. int ret;
  199. nau7802_sync(st);
  200. /* read registers to ensure we flush everything */
  201. ret = nau7802_read_conversion(st);
  202. if (ret < 0)
  203. return ret;
  204. /*
  205. * Because there is actually only one ADC for both channels, we have to
  206. * wait for enough conversions to happen before getting a significant
  207. * value when changing channels and the values are far appart.
  208. */
  209. do {
  210. ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
  211. if (ret < 0)
  212. return ret;
  213. while (!(ret & NAU7802_PUCTRL_CR_BIT)) {
  214. if (st->sample_rate != NAU7802_SAMP_FREQ_320)
  215. msleep(20);
  216. else
  217. mdelay(4);
  218. ret = i2c_smbus_read_byte_data(st->client,
  219. NAU7802_REG_PUCTRL);
  220. if (ret < 0)
  221. return ret;
  222. }
  223. ret = nau7802_read_conversion(st);
  224. if (ret < 0)
  225. return ret;
  226. if (st->conversion_count < NAU7802_MIN_CONVERSIONS)
  227. st->conversion_count++;
  228. } while (st->conversion_count < NAU7802_MIN_CONVERSIONS);
  229. *val = st->last_value;
  230. return IIO_VAL_INT;
  231. }
  232. static int nau7802_read_raw(struct iio_dev *indio_dev,
  233. struct iio_chan_spec const *chan,
  234. int *val, int *val2, long mask)
  235. {
  236. struct nau7802_state *st = iio_priv(indio_dev);
  237. int ret;
  238. switch (mask) {
  239. case IIO_CHAN_INFO_RAW:
  240. mutex_lock(&st->lock);
  241. /*
  242. * Select the channel to use
  243. * - Channel 1 is value 0 in the CHS register
  244. * - Channel 2 is value 1 in the CHS register
  245. */
  246. ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL2);
  247. if (ret < 0) {
  248. mutex_unlock(&st->lock);
  249. return ret;
  250. }
  251. if (((ret & NAU7802_CTRL2_CHS_BIT) && !chan->channel) ||
  252. (!(ret & NAU7802_CTRL2_CHS_BIT) &&
  253. chan->channel)) {
  254. st->conversion_count = 0;
  255. ret = i2c_smbus_write_byte_data(st->client,
  256. NAU7802_REG_CTRL2,
  257. NAU7802_CTRL2_CHS(chan->channel) |
  258. NAU7802_CTRL2_CRS(st->sample_rate));
  259. if (ret < 0) {
  260. mutex_unlock(&st->lock);
  261. return ret;
  262. }
  263. }
  264. if (st->client->irq)
  265. ret = nau7802_read_irq(indio_dev, chan, val);
  266. else
  267. ret = nau7802_read_poll(indio_dev, chan, val);
  268. mutex_unlock(&st->lock);
  269. return ret;
  270. case IIO_CHAN_INFO_SCALE:
  271. ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1);
  272. if (ret < 0)
  273. return ret;
  274. /*
  275. * We have 24 bits of signed data, that means 23 bits of data
  276. * plus the sign bit
  277. */
  278. *val = st->vref_mv;
  279. *val2 = 23 + (ret & NAU7802_CTRL1_GAINS_BITS);
  280. return IIO_VAL_FRACTIONAL_LOG2;
  281. case IIO_CHAN_INFO_SAMP_FREQ:
  282. *val = nau7802_sample_freq_avail[st->sample_rate];
  283. *val2 = 0;
  284. return IIO_VAL_INT;
  285. default:
  286. break;
  287. }
  288. return -EINVAL;
  289. }
  290. static int nau7802_write_raw(struct iio_dev *indio_dev,
  291. struct iio_chan_spec const *chan,
  292. int val, int val2, long mask)
  293. {
  294. struct nau7802_state *st = iio_priv(indio_dev);
  295. int i, ret;
  296. switch (mask) {
  297. case IIO_CHAN_INFO_SCALE:
  298. for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
  299. if (val2 == st->scale_avail[i])
  300. return nau7802_set_gain(st, i);
  301. break;
  302. case IIO_CHAN_INFO_SAMP_FREQ:
  303. for (i = 0; i < ARRAY_SIZE(nau7802_sample_freq_avail); i++)
  304. if (val == nau7802_sample_freq_avail[i]) {
  305. mutex_lock(&st->lock);
  306. st->sample_rate = i;
  307. st->conversion_count = 0;
  308. ret = i2c_smbus_write_byte_data(st->client,
  309. NAU7802_REG_CTRL2,
  310. NAU7802_CTRL2_CRS(st->sample_rate));
  311. mutex_unlock(&st->lock);
  312. return ret;
  313. }
  314. break;
  315. default:
  316. break;
  317. }
  318. return -EINVAL;
  319. }
  320. static int nau7802_write_raw_get_fmt(struct iio_dev *indio_dev,
  321. struct iio_chan_spec const *chan,
  322. long mask)
  323. {
  324. return IIO_VAL_INT_PLUS_NANO;
  325. }
  326. static const struct iio_info nau7802_info = {
  327. .read_raw = &nau7802_read_raw,
  328. .write_raw = &nau7802_write_raw,
  329. .write_raw_get_fmt = nau7802_write_raw_get_fmt,
  330. .attrs = &nau7802_attribute_group,
  331. };
  332. static int nau7802_probe(struct i2c_client *client,
  333. const struct i2c_device_id *id)
  334. {
  335. struct iio_dev *indio_dev;
  336. struct nau7802_state *st;
  337. struct device_node *np = client->dev.of_node;
  338. int i, ret;
  339. u8 data;
  340. u32 tmp = 0;
  341. if (!client->dev.of_node) {
  342. dev_err(&client->dev, "No device tree node available.\n");
  343. return -EINVAL;
  344. }
  345. indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st));
  346. if (indio_dev == NULL)
  347. return -ENOMEM;
  348. st = iio_priv(indio_dev);
  349. i2c_set_clientdata(client, indio_dev);
  350. indio_dev->name = dev_name(&client->dev);
  351. indio_dev->modes = INDIO_DIRECT_MODE;
  352. indio_dev->info = &nau7802_info;
  353. st->client = client;
  354. /* Reset the device */
  355. ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
  356. NAU7802_PUCTRL_RR_BIT);
  357. if (ret < 0)
  358. return ret;
  359. /* Enter normal operation mode */
  360. ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
  361. NAU7802_PUCTRL_PUD_BIT);
  362. if (ret < 0)
  363. return ret;
  364. /*
  365. * After about 200 usecs, the device should be ready and then
  366. * the Power Up bit will be set to 1. If not, wait for it.
  367. */
  368. udelay(210);
  369. ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
  370. if (ret < 0)
  371. return ret;
  372. if (!(ret & NAU7802_PUCTRL_PUR_BIT))
  373. return ret;
  374. of_property_read_u32(np, "nuvoton,vldo", &tmp);
  375. st->vref_mv = tmp;
  376. data = NAU7802_PUCTRL_PUD_BIT | NAU7802_PUCTRL_PUA_BIT |
  377. NAU7802_PUCTRL_CS_BIT;
  378. if (tmp >= 2400)
  379. data |= NAU7802_PUCTRL_AVDDS_BIT;
  380. ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL, data);
  381. if (ret < 0)
  382. return ret;
  383. ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_ADC_CTRL, 0x30);
  384. if (ret < 0)
  385. return ret;
  386. if (tmp >= 2400) {
  387. data = NAU7802_CTRL1_VLDO((4500 - tmp) / 300);
  388. ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1,
  389. data);
  390. if (ret < 0)
  391. return ret;
  392. }
  393. /* Populate available ADC input ranges */
  394. for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
  395. st->scale_avail[i] = (((u64)st->vref_mv) * 1000000000ULL)
  396. >> (23 + i);
  397. init_completion(&st->value_ok);
  398. /*
  399. * The ADC fires continuously and we can't do anything about
  400. * it. So we need to have the IRQ disabled by default, and we
  401. * will enable them back when we will need them..
  402. */
  403. if (client->irq) {
  404. ret = request_threaded_irq(client->irq,
  405. NULL,
  406. nau7802_eoc_trigger,
  407. IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
  408. client->dev.driver->name,
  409. indio_dev);
  410. if (ret) {
  411. /*
  412. * What may happen here is that our IRQ controller is
  413. * not able to get level interrupt but this is required
  414. * by this ADC as when going over 40 sample per second,
  415. * the interrupt line may stay high between conversions.
  416. * So, we continue no matter what but we switch to
  417. * polling mode.
  418. */
  419. dev_info(&client->dev,
  420. "Failed to allocate IRQ, using polling mode\n");
  421. client->irq = 0;
  422. } else
  423. disable_irq(client->irq);
  424. }
  425. if (!client->irq) {
  426. /*
  427. * We are polling, use the fastest sample rate by
  428. * default
  429. */
  430. st->sample_rate = NAU7802_SAMP_FREQ_320;
  431. ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL2,
  432. NAU7802_CTRL2_CRS(st->sample_rate));
  433. if (ret)
  434. goto error_free_irq;
  435. }
  436. /* Setup the ADC channels available on the board */
  437. indio_dev->num_channels = ARRAY_SIZE(nau7802_chan_array);
  438. indio_dev->channels = nau7802_chan_array;
  439. mutex_init(&st->lock);
  440. mutex_init(&st->data_lock);
  441. ret = iio_device_register(indio_dev);
  442. if (ret < 0) {
  443. dev_err(&client->dev, "Couldn't register the device.\n");
  444. goto error_device_register;
  445. }
  446. return 0;
  447. error_device_register:
  448. mutex_destroy(&st->lock);
  449. mutex_destroy(&st->data_lock);
  450. error_free_irq:
  451. if (client->irq)
  452. free_irq(client->irq, indio_dev);
  453. return ret;
  454. }
  455. static int nau7802_remove(struct i2c_client *client)
  456. {
  457. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  458. struct nau7802_state *st = iio_priv(indio_dev);
  459. iio_device_unregister(indio_dev);
  460. mutex_destroy(&st->lock);
  461. mutex_destroy(&st->data_lock);
  462. if (client->irq)
  463. free_irq(client->irq, indio_dev);
  464. return 0;
  465. }
  466. static const struct i2c_device_id nau7802_i2c_id[] = {
  467. { "nau7802", 0 },
  468. { }
  469. };
  470. MODULE_DEVICE_TABLE(i2c, nau7802_i2c_id);
  471. static const struct of_device_id nau7802_dt_ids[] = {
  472. { .compatible = "nuvoton,nau7802" },
  473. {},
  474. };
  475. MODULE_DEVICE_TABLE(of, nau7802_dt_ids);
  476. static struct i2c_driver nau7802_driver = {
  477. .probe = nau7802_probe,
  478. .remove = nau7802_remove,
  479. .id_table = nau7802_i2c_id,
  480. .driver = {
  481. .name = "nau7802",
  482. .of_match_table = nau7802_dt_ids,
  483. },
  484. };
  485. module_i2c_driver(nau7802_driver);
  486. MODULE_LICENSE("GPL");
  487. MODULE_DESCRIPTION("Nuvoton NAU7802 ADC Driver");
  488. MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
  489. MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");