mxs-lradc-adc.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Freescale MXS LRADC ADC driver
  4. *
  5. * Copyright (c) 2012 DENX Software Engineering, GmbH.
  6. * Copyright (c) 2017 Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
  7. *
  8. * Authors:
  9. * Marek Vasut <marex@denx.de>
  10. * Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
  11. */
  12. #include <linux/completion.h>
  13. #include <linux/device.h>
  14. #include <linux/err.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/mfd/core.h>
  17. #include <linux/mfd/mxs-lradc.h>
  18. #include <linux/module.h>
  19. #include <linux/of_irq.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/sysfs.h>
  22. #include <linux/iio/buffer.h>
  23. #include <linux/iio/iio.h>
  24. #include <linux/iio/trigger.h>
  25. #include <linux/iio/trigger_consumer.h>
  26. #include <linux/iio/triggered_buffer.h>
  27. #include <linux/iio/sysfs.h>
  28. /*
  29. * Make this runtime configurable if necessary. Currently, if the buffered mode
  30. * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
  31. * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
  32. * seconds. The result is that the samples arrive every 500mS.
  33. */
  34. #define LRADC_DELAY_TIMER_PER 200
  35. #define LRADC_DELAY_TIMER_LOOP 5
  36. #define VREF_MV_BASE 1850
  37. static const char *mx23_lradc_adc_irq_names[] = {
  38. "mxs-lradc-channel0",
  39. "mxs-lradc-channel1",
  40. "mxs-lradc-channel2",
  41. "mxs-lradc-channel3",
  42. "mxs-lradc-channel4",
  43. "mxs-lradc-channel5",
  44. };
  45. static const char *mx28_lradc_adc_irq_names[] = {
  46. "mxs-lradc-thresh0",
  47. "mxs-lradc-thresh1",
  48. "mxs-lradc-channel0",
  49. "mxs-lradc-channel1",
  50. "mxs-lradc-channel2",
  51. "mxs-lradc-channel3",
  52. "mxs-lradc-channel4",
  53. "mxs-lradc-channel5",
  54. "mxs-lradc-button0",
  55. "mxs-lradc-button1",
  56. };
  57. static const u32 mxs_lradc_adc_vref_mv[][LRADC_MAX_TOTAL_CHANS] = {
  58. [IMX23_LRADC] = {
  59. VREF_MV_BASE, /* CH0 */
  60. VREF_MV_BASE, /* CH1 */
  61. VREF_MV_BASE, /* CH2 */
  62. VREF_MV_BASE, /* CH3 */
  63. VREF_MV_BASE, /* CH4 */
  64. VREF_MV_BASE, /* CH5 */
  65. VREF_MV_BASE * 2, /* CH6 VDDIO */
  66. VREF_MV_BASE * 4, /* CH7 VBATT */
  67. VREF_MV_BASE, /* CH8 Temp sense 0 */
  68. VREF_MV_BASE, /* CH9 Temp sense 1 */
  69. VREF_MV_BASE, /* CH10 */
  70. VREF_MV_BASE, /* CH11 */
  71. VREF_MV_BASE, /* CH12 USB_DP */
  72. VREF_MV_BASE, /* CH13 USB_DN */
  73. VREF_MV_BASE, /* CH14 VBG */
  74. VREF_MV_BASE * 4, /* CH15 VDD5V */
  75. },
  76. [IMX28_LRADC] = {
  77. VREF_MV_BASE, /* CH0 */
  78. VREF_MV_BASE, /* CH1 */
  79. VREF_MV_BASE, /* CH2 */
  80. VREF_MV_BASE, /* CH3 */
  81. VREF_MV_BASE, /* CH4 */
  82. VREF_MV_BASE, /* CH5 */
  83. VREF_MV_BASE, /* CH6 */
  84. VREF_MV_BASE * 4, /* CH7 VBATT */
  85. VREF_MV_BASE, /* CH8 Temp sense 0 */
  86. VREF_MV_BASE, /* CH9 Temp sense 1 */
  87. VREF_MV_BASE * 2, /* CH10 VDDIO */
  88. VREF_MV_BASE, /* CH11 VTH */
  89. VREF_MV_BASE * 2, /* CH12 VDDA */
  90. VREF_MV_BASE, /* CH13 VDDD */
  91. VREF_MV_BASE, /* CH14 VBG */
  92. VREF_MV_BASE * 4, /* CH15 VDD5V */
  93. },
  94. };
  95. enum mxs_lradc_divbytwo {
  96. MXS_LRADC_DIV_DISABLED = 0,
  97. MXS_LRADC_DIV_ENABLED,
  98. };
  99. struct mxs_lradc_scale {
  100. unsigned int integer;
  101. unsigned int nano;
  102. };
  103. struct mxs_lradc_adc {
  104. struct mxs_lradc *lradc;
  105. struct device *dev;
  106. void __iomem *base;
  107. /* Maximum of 8 channels + 8 byte ts */
  108. u32 buffer[10] __aligned(8);
  109. struct iio_trigger *trig;
  110. struct completion completion;
  111. spinlock_t lock;
  112. const u32 *vref_mv;
  113. struct mxs_lradc_scale scale_avail[LRADC_MAX_TOTAL_CHANS][2];
  114. unsigned long is_divided;
  115. };
  116. /* Raw I/O operations */
  117. static int mxs_lradc_adc_read_single(struct iio_dev *iio_dev, int chan,
  118. int *val)
  119. {
  120. struct mxs_lradc_adc *adc = iio_priv(iio_dev);
  121. struct mxs_lradc *lradc = adc->lradc;
  122. int ret;
  123. /*
  124. * See if there is no buffered operation in progress. If there is simply
  125. * bail out. This can be improved to support both buffered and raw IO at
  126. * the same time, yet the code becomes horribly complicated. Therefore I
  127. * applied KISS principle here.
  128. */
  129. ret = iio_device_claim_direct_mode(iio_dev);
  130. if (ret)
  131. return ret;
  132. reinit_completion(&adc->completion);
  133. /*
  134. * No buffered operation in progress, map the channel and trigger it.
  135. * Virtual channel 0 is always used here as the others are always not
  136. * used if doing raw sampling.
  137. */
  138. if (lradc->soc == IMX28_LRADC)
  139. writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
  140. adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
  141. writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
  142. /* Enable / disable the divider per requirement */
  143. if (test_bit(chan, &adc->is_divided))
  144. writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
  145. adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET);
  146. else
  147. writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
  148. adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR);
  149. /* Clean the slot's previous content, then set new one. */
  150. writel(LRADC_CTRL4_LRADCSELECT_MASK(0),
  151. adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
  152. writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
  153. writel(0, adc->base + LRADC_CH(0));
  154. /* Enable the IRQ and start sampling the channel. */
  155. writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
  156. adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
  157. writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
  158. /* Wait for completion on the channel, 1 second max. */
  159. ret = wait_for_completion_killable_timeout(&adc->completion, HZ);
  160. if (!ret)
  161. ret = -ETIMEDOUT;
  162. if (ret < 0)
  163. goto err;
  164. /* Read the data. */
  165. *val = readl(adc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
  166. ret = IIO_VAL_INT;
  167. err:
  168. writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
  169. adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
  170. iio_device_release_direct_mode(iio_dev);
  171. return ret;
  172. }
  173. static int mxs_lradc_adc_read_temp(struct iio_dev *iio_dev, int *val)
  174. {
  175. int ret, min, max;
  176. ret = mxs_lradc_adc_read_single(iio_dev, 8, &min);
  177. if (ret != IIO_VAL_INT)
  178. return ret;
  179. ret = mxs_lradc_adc_read_single(iio_dev, 9, &max);
  180. if (ret != IIO_VAL_INT)
  181. return ret;
  182. *val = max - min;
  183. return IIO_VAL_INT;
  184. }
  185. static int mxs_lradc_adc_read_raw(struct iio_dev *iio_dev,
  186. const struct iio_chan_spec *chan,
  187. int *val, int *val2, long m)
  188. {
  189. struct mxs_lradc_adc *adc = iio_priv(iio_dev);
  190. switch (m) {
  191. case IIO_CHAN_INFO_RAW:
  192. if (chan->type == IIO_TEMP)
  193. return mxs_lradc_adc_read_temp(iio_dev, val);
  194. return mxs_lradc_adc_read_single(iio_dev, chan->channel, val);
  195. case IIO_CHAN_INFO_SCALE:
  196. if (chan->type == IIO_TEMP) {
  197. /*
  198. * From the datasheet, we have to multiply by 1.012 and
  199. * divide by 4
  200. */
  201. *val = 0;
  202. *val2 = 253000;
  203. return IIO_VAL_INT_PLUS_MICRO;
  204. }
  205. *val = adc->vref_mv[chan->channel];
  206. *val2 = chan->scan_type.realbits -
  207. test_bit(chan->channel, &adc->is_divided);
  208. return IIO_VAL_FRACTIONAL_LOG2;
  209. case IIO_CHAN_INFO_OFFSET:
  210. if (chan->type == IIO_TEMP) {
  211. /*
  212. * The calculated value from the ADC is in Kelvin, we
  213. * want Celsius for hwmon so the offset is -273.15
  214. * The offset is applied before scaling so it is
  215. * actually -213.15 * 4 / 1.012 = -1079.644268
  216. */
  217. *val = -1079;
  218. *val2 = 644268;
  219. return IIO_VAL_INT_PLUS_MICRO;
  220. }
  221. return -EINVAL;
  222. default:
  223. break;
  224. }
  225. return -EINVAL;
  226. }
  227. static int mxs_lradc_adc_write_raw(struct iio_dev *iio_dev,
  228. const struct iio_chan_spec *chan,
  229. int val, int val2, long m)
  230. {
  231. struct mxs_lradc_adc *adc = iio_priv(iio_dev);
  232. struct mxs_lradc_scale *scale_avail =
  233. adc->scale_avail[chan->channel];
  234. int ret;
  235. ret = iio_device_claim_direct_mode(iio_dev);
  236. if (ret)
  237. return ret;
  238. switch (m) {
  239. case IIO_CHAN_INFO_SCALE:
  240. ret = -EINVAL;
  241. if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
  242. val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
  243. /* divider by two disabled */
  244. clear_bit(chan->channel, &adc->is_divided);
  245. ret = 0;
  246. } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
  247. val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
  248. /* divider by two enabled */
  249. set_bit(chan->channel, &adc->is_divided);
  250. ret = 0;
  251. }
  252. break;
  253. default:
  254. ret = -EINVAL;
  255. break;
  256. }
  257. iio_device_release_direct_mode(iio_dev);
  258. return ret;
  259. }
  260. static int mxs_lradc_adc_write_raw_get_fmt(struct iio_dev *iio_dev,
  261. const struct iio_chan_spec *chan,
  262. long m)
  263. {
  264. return IIO_VAL_INT_PLUS_NANO;
  265. }
  266. static ssize_t mxs_lradc_adc_show_scale_avail(struct device *dev,
  267. struct device_attribute *attr,
  268. char *buf)
  269. {
  270. struct iio_dev *iio = dev_to_iio_dev(dev);
  271. struct mxs_lradc_adc *adc = iio_priv(iio);
  272. struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
  273. int i, ch, len = 0;
  274. ch = iio_attr->address;
  275. for (i = 0; i < ARRAY_SIZE(adc->scale_avail[ch]); i++)
  276. len += sprintf(buf + len, "%u.%09u ",
  277. adc->scale_avail[ch][i].integer,
  278. adc->scale_avail[ch][i].nano);
  279. len += sprintf(buf + len, "\n");
  280. return len;
  281. }
  282. #define SHOW_SCALE_AVAILABLE_ATTR(ch)\
  283. IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, 0444,\
  284. mxs_lradc_adc_show_scale_avail, NULL, ch)
  285. static SHOW_SCALE_AVAILABLE_ATTR(0);
  286. static SHOW_SCALE_AVAILABLE_ATTR(1);
  287. static SHOW_SCALE_AVAILABLE_ATTR(2);
  288. static SHOW_SCALE_AVAILABLE_ATTR(3);
  289. static SHOW_SCALE_AVAILABLE_ATTR(4);
  290. static SHOW_SCALE_AVAILABLE_ATTR(5);
  291. static SHOW_SCALE_AVAILABLE_ATTR(6);
  292. static SHOW_SCALE_AVAILABLE_ATTR(7);
  293. static SHOW_SCALE_AVAILABLE_ATTR(10);
  294. static SHOW_SCALE_AVAILABLE_ATTR(11);
  295. static SHOW_SCALE_AVAILABLE_ATTR(12);
  296. static SHOW_SCALE_AVAILABLE_ATTR(13);
  297. static SHOW_SCALE_AVAILABLE_ATTR(14);
  298. static SHOW_SCALE_AVAILABLE_ATTR(15);
  299. static struct attribute *mxs_lradc_adc_attributes[] = {
  300. &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
  301. &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
  302. &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
  303. &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
  304. &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
  305. &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
  306. &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
  307. &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
  308. &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
  309. &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
  310. &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
  311. &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
  312. &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
  313. &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
  314. NULL
  315. };
  316. static const struct attribute_group mxs_lradc_adc_attribute_group = {
  317. .attrs = mxs_lradc_adc_attributes,
  318. };
  319. static const struct iio_info mxs_lradc_adc_iio_info = {
  320. .read_raw = mxs_lradc_adc_read_raw,
  321. .write_raw = mxs_lradc_adc_write_raw,
  322. .write_raw_get_fmt = mxs_lradc_adc_write_raw_get_fmt,
  323. .attrs = &mxs_lradc_adc_attribute_group,
  324. };
  325. /* IRQ Handling */
  326. static irqreturn_t mxs_lradc_adc_handle_irq(int irq, void *data)
  327. {
  328. struct iio_dev *iio = data;
  329. struct mxs_lradc_adc *adc = iio_priv(iio);
  330. struct mxs_lradc *lradc = adc->lradc;
  331. unsigned long reg = readl(adc->base + LRADC_CTRL1);
  332. unsigned long flags;
  333. if (!(reg & mxs_lradc_irq_mask(lradc)))
  334. return IRQ_NONE;
  335. if (iio_buffer_enabled(iio)) {
  336. if (reg & lradc->buffer_vchans) {
  337. spin_lock_irqsave(&adc->lock, flags);
  338. iio_trigger_poll(iio->trig);
  339. spin_unlock_irqrestore(&adc->lock, flags);
  340. }
  341. } else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) {
  342. complete(&adc->completion);
  343. }
  344. writel(reg & mxs_lradc_irq_mask(lradc),
  345. adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
  346. return IRQ_HANDLED;
  347. }
  348. /* Trigger handling */
  349. static irqreturn_t mxs_lradc_adc_trigger_handler(int irq, void *p)
  350. {
  351. struct iio_poll_func *pf = p;
  352. struct iio_dev *iio = pf->indio_dev;
  353. struct mxs_lradc_adc *adc = iio_priv(iio);
  354. const u32 chan_value = LRADC_CH_ACCUMULATE |
  355. ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
  356. unsigned int i, j = 0;
  357. for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
  358. adc->buffer[j] = readl(adc->base + LRADC_CH(j));
  359. writel(chan_value, adc->base + LRADC_CH(j));
  360. adc->buffer[j] &= LRADC_CH_VALUE_MASK;
  361. adc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
  362. j++;
  363. }
  364. iio_push_to_buffers_with_timestamp(iio, adc->buffer, pf->timestamp);
  365. iio_trigger_notify_done(iio->trig);
  366. return IRQ_HANDLED;
  367. }
  368. static int mxs_lradc_adc_configure_trigger(struct iio_trigger *trig, bool state)
  369. {
  370. struct iio_dev *iio = iio_trigger_get_drvdata(trig);
  371. struct mxs_lradc_adc *adc = iio_priv(iio);
  372. const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
  373. writel(LRADC_DELAY_KICK, adc->base + (LRADC_DELAY(0) + st));
  374. return 0;
  375. }
  376. static const struct iio_trigger_ops mxs_lradc_adc_trigger_ops = {
  377. .set_trigger_state = &mxs_lradc_adc_configure_trigger,
  378. };
  379. static int mxs_lradc_adc_trigger_init(struct iio_dev *iio)
  380. {
  381. int ret;
  382. struct iio_trigger *trig;
  383. struct mxs_lradc_adc *adc = iio_priv(iio);
  384. trig = devm_iio_trigger_alloc(&iio->dev, "%s-dev%i", iio->name,
  385. iio->id);
  386. if (!trig)
  387. return -ENOMEM;
  388. trig->dev.parent = adc->dev;
  389. iio_trigger_set_drvdata(trig, iio);
  390. trig->ops = &mxs_lradc_adc_trigger_ops;
  391. ret = iio_trigger_register(trig);
  392. if (ret)
  393. return ret;
  394. adc->trig = trig;
  395. return 0;
  396. }
  397. static void mxs_lradc_adc_trigger_remove(struct iio_dev *iio)
  398. {
  399. struct mxs_lradc_adc *adc = iio_priv(iio);
  400. iio_trigger_unregister(adc->trig);
  401. }
  402. static int mxs_lradc_adc_buffer_preenable(struct iio_dev *iio)
  403. {
  404. struct mxs_lradc_adc *adc = iio_priv(iio);
  405. struct mxs_lradc *lradc = adc->lradc;
  406. int chan, ofs = 0;
  407. unsigned long enable = 0;
  408. u32 ctrl4_set = 0;
  409. u32 ctrl4_clr = 0;
  410. u32 ctrl1_irq = 0;
  411. const u32 chan_value = LRADC_CH_ACCUMULATE |
  412. ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
  413. if (lradc->soc == IMX28_LRADC)
  414. writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
  415. adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
  416. writel(lradc->buffer_vchans,
  417. adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
  418. for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
  419. ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
  420. ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
  421. ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
  422. writel(chan_value, adc->base + LRADC_CH(ofs));
  423. bitmap_set(&enable, ofs, 1);
  424. ofs++;
  425. }
  426. writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
  427. adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
  428. writel(ctrl4_clr, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
  429. writel(ctrl4_set, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
  430. writel(ctrl1_irq, adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
  431. writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
  432. adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET);
  433. return 0;
  434. }
  435. static int mxs_lradc_adc_buffer_postdisable(struct iio_dev *iio)
  436. {
  437. struct mxs_lradc_adc *adc = iio_priv(iio);
  438. struct mxs_lradc *lradc = adc->lradc;
  439. writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
  440. adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
  441. writel(lradc->buffer_vchans,
  442. adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
  443. if (lradc->soc == IMX28_LRADC)
  444. writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
  445. adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
  446. return 0;
  447. }
  448. static bool mxs_lradc_adc_validate_scan_mask(struct iio_dev *iio,
  449. const unsigned long *mask)
  450. {
  451. struct mxs_lradc_adc *adc = iio_priv(iio);
  452. struct mxs_lradc *lradc = adc->lradc;
  453. const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
  454. int rsvd_chans = 0;
  455. unsigned long rsvd_mask = 0;
  456. if (lradc->use_touchbutton)
  457. rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
  458. if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_4WIRE)
  459. rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
  460. if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_5WIRE)
  461. rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
  462. if (lradc->use_touchbutton)
  463. rsvd_chans++;
  464. if (lradc->touchscreen_wire)
  465. rsvd_chans += 2;
  466. /* Test for attempts to map channels with special mode of operation. */
  467. if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
  468. return false;
  469. /* Test for attempts to map more channels then available slots. */
  470. if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
  471. return false;
  472. return true;
  473. }
  474. static const struct iio_buffer_setup_ops mxs_lradc_adc_buffer_ops = {
  475. .preenable = &mxs_lradc_adc_buffer_preenable,
  476. .postdisable = &mxs_lradc_adc_buffer_postdisable,
  477. .validate_scan_mask = &mxs_lradc_adc_validate_scan_mask,
  478. };
  479. /* Driver initialization */
  480. #define MXS_ADC_CHAN(idx, chan_type, name) { \
  481. .type = (chan_type), \
  482. .indexed = 1, \
  483. .scan_index = (idx), \
  484. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  485. BIT(IIO_CHAN_INFO_SCALE), \
  486. .channel = (idx), \
  487. .address = (idx), \
  488. .scan_type = { \
  489. .sign = 'u', \
  490. .realbits = LRADC_RESOLUTION, \
  491. .storagebits = 32, \
  492. }, \
  493. .datasheet_name = (name), \
  494. }
  495. static const struct iio_chan_spec mx23_lradc_chan_spec[] = {
  496. MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
  497. MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
  498. MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
  499. MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
  500. MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
  501. MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
  502. MXS_ADC_CHAN(6, IIO_VOLTAGE, "VDDIO"),
  503. MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
  504. /* Combined Temperature sensors */
  505. {
  506. .type = IIO_TEMP,
  507. .indexed = 1,
  508. .scan_index = 8,
  509. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
  510. BIT(IIO_CHAN_INFO_OFFSET) |
  511. BIT(IIO_CHAN_INFO_SCALE),
  512. .channel = 8,
  513. .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
  514. .datasheet_name = "TEMP_DIE",
  515. },
  516. /* Hidden channel to keep indexes */
  517. {
  518. .type = IIO_TEMP,
  519. .indexed = 1,
  520. .scan_index = -1,
  521. .channel = 9,
  522. },
  523. MXS_ADC_CHAN(10, IIO_VOLTAGE, NULL),
  524. MXS_ADC_CHAN(11, IIO_VOLTAGE, NULL),
  525. MXS_ADC_CHAN(12, IIO_VOLTAGE, "USB_DP"),
  526. MXS_ADC_CHAN(13, IIO_VOLTAGE, "USB_DN"),
  527. MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
  528. MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
  529. };
  530. static const struct iio_chan_spec mx28_lradc_chan_spec[] = {
  531. MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
  532. MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
  533. MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
  534. MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
  535. MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
  536. MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
  537. MXS_ADC_CHAN(6, IIO_VOLTAGE, "LRADC6"),
  538. MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
  539. /* Combined Temperature sensors */
  540. {
  541. .type = IIO_TEMP,
  542. .indexed = 1,
  543. .scan_index = 8,
  544. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
  545. BIT(IIO_CHAN_INFO_OFFSET) |
  546. BIT(IIO_CHAN_INFO_SCALE),
  547. .channel = 8,
  548. .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
  549. .datasheet_name = "TEMP_DIE",
  550. },
  551. /* Hidden channel to keep indexes */
  552. {
  553. .type = IIO_TEMP,
  554. .indexed = 1,
  555. .scan_index = -1,
  556. .channel = 9,
  557. },
  558. MXS_ADC_CHAN(10, IIO_VOLTAGE, "VDDIO"),
  559. MXS_ADC_CHAN(11, IIO_VOLTAGE, "VTH"),
  560. MXS_ADC_CHAN(12, IIO_VOLTAGE, "VDDA"),
  561. MXS_ADC_CHAN(13, IIO_VOLTAGE, "VDDD"),
  562. MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
  563. MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
  564. };
  565. static void mxs_lradc_adc_hw_init(struct mxs_lradc_adc *adc)
  566. {
  567. /* The ADC always uses DELAY CHANNEL 0. */
  568. const u32 adc_cfg =
  569. (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
  570. (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
  571. /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
  572. writel(adc_cfg, adc->base + LRADC_DELAY(0));
  573. /*
  574. * Start internal temperature sensing by clearing bit
  575. * HW_LRADC_CTRL2_TEMPSENSE_PWD. This bit can be left cleared
  576. * after power up.
  577. */
  578. writel(0, adc->base + LRADC_CTRL2);
  579. }
  580. static void mxs_lradc_adc_hw_stop(struct mxs_lradc_adc *adc)
  581. {
  582. writel(0, adc->base + LRADC_DELAY(0));
  583. }
  584. static int mxs_lradc_adc_probe(struct platform_device *pdev)
  585. {
  586. struct device *dev = &pdev->dev;
  587. struct mxs_lradc *lradc = dev_get_drvdata(dev->parent);
  588. struct mxs_lradc_adc *adc;
  589. struct iio_dev *iio;
  590. struct resource *iores;
  591. int ret, irq, virq, i, s, n;
  592. u64 scale_uv;
  593. const char **irq_name;
  594. /* Allocate the IIO device. */
  595. iio = devm_iio_device_alloc(dev, sizeof(*adc));
  596. if (!iio) {
  597. dev_err(dev, "Failed to allocate IIO device\n");
  598. return -ENOMEM;
  599. }
  600. adc = iio_priv(iio);
  601. adc->lradc = lradc;
  602. adc->dev = dev;
  603. iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  604. if (!iores)
  605. return -EINVAL;
  606. adc->base = devm_ioremap(dev, iores->start, resource_size(iores));
  607. if (!adc->base)
  608. return -ENOMEM;
  609. init_completion(&adc->completion);
  610. spin_lock_init(&adc->lock);
  611. platform_set_drvdata(pdev, iio);
  612. iio->name = pdev->name;
  613. iio->dev.of_node = dev->parent->of_node;
  614. iio->info = &mxs_lradc_adc_iio_info;
  615. iio->modes = INDIO_DIRECT_MODE;
  616. iio->masklength = LRADC_MAX_TOTAL_CHANS;
  617. if (lradc->soc == IMX23_LRADC) {
  618. iio->channels = mx23_lradc_chan_spec;
  619. iio->num_channels = ARRAY_SIZE(mx23_lradc_chan_spec);
  620. irq_name = mx23_lradc_adc_irq_names;
  621. n = ARRAY_SIZE(mx23_lradc_adc_irq_names);
  622. } else {
  623. iio->channels = mx28_lradc_chan_spec;
  624. iio->num_channels = ARRAY_SIZE(mx28_lradc_chan_spec);
  625. irq_name = mx28_lradc_adc_irq_names;
  626. n = ARRAY_SIZE(mx28_lradc_adc_irq_names);
  627. }
  628. ret = stmp_reset_block(adc->base);
  629. if (ret)
  630. return ret;
  631. for (i = 0; i < n; i++) {
  632. irq = platform_get_irq_byname(pdev, irq_name[i]);
  633. if (irq < 0)
  634. return irq;
  635. virq = irq_of_parse_and_map(dev->parent->of_node, irq);
  636. ret = devm_request_irq(dev, virq, mxs_lradc_adc_handle_irq,
  637. 0, irq_name[i], iio);
  638. if (ret)
  639. return ret;
  640. }
  641. ret = mxs_lradc_adc_trigger_init(iio);
  642. if (ret)
  643. goto err_trig;
  644. ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
  645. &mxs_lradc_adc_trigger_handler,
  646. &mxs_lradc_adc_buffer_ops);
  647. if (ret)
  648. return ret;
  649. adc->vref_mv = mxs_lradc_adc_vref_mv[lradc->soc];
  650. /* Populate available ADC input ranges */
  651. for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
  652. for (s = 0; s < ARRAY_SIZE(adc->scale_avail[i]); s++) {
  653. /*
  654. * [s=0] = optional divider by two disabled (default)
  655. * [s=1] = optional divider by two enabled
  656. *
  657. * The scale is calculated by doing:
  658. * Vref >> (realbits - s)
  659. * which multiplies by two on the second component
  660. * of the array.
  661. */
  662. scale_uv = ((u64)adc->vref_mv[i] * 100000000) >>
  663. (LRADC_RESOLUTION - s);
  664. adc->scale_avail[i][s].nano =
  665. do_div(scale_uv, 100000000) * 10;
  666. adc->scale_avail[i][s].integer = scale_uv;
  667. }
  668. }
  669. /* Configure the hardware. */
  670. mxs_lradc_adc_hw_init(adc);
  671. /* Register IIO device. */
  672. ret = iio_device_register(iio);
  673. if (ret) {
  674. dev_err(dev, "Failed to register IIO device\n");
  675. goto err_dev;
  676. }
  677. return 0;
  678. err_dev:
  679. mxs_lradc_adc_hw_stop(adc);
  680. mxs_lradc_adc_trigger_remove(iio);
  681. err_trig:
  682. iio_triggered_buffer_cleanup(iio);
  683. return ret;
  684. }
  685. static int mxs_lradc_adc_remove(struct platform_device *pdev)
  686. {
  687. struct iio_dev *iio = platform_get_drvdata(pdev);
  688. struct mxs_lradc_adc *adc = iio_priv(iio);
  689. iio_device_unregister(iio);
  690. mxs_lradc_adc_hw_stop(adc);
  691. mxs_lradc_adc_trigger_remove(iio);
  692. iio_triggered_buffer_cleanup(iio);
  693. return 0;
  694. }
  695. static struct platform_driver mxs_lradc_adc_driver = {
  696. .driver = {
  697. .name = "mxs-lradc-adc",
  698. },
  699. .probe = mxs_lradc_adc_probe,
  700. .remove = mxs_lradc_adc_remove,
  701. };
  702. module_platform_driver(mxs_lradc_adc_driver);
  703. MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
  704. MODULE_DESCRIPTION("Freescale MXS LRADC driver general purpose ADC driver");
  705. MODULE_LICENSE("GPL");
  706. MODULE_ALIAS("platform:mxs-lradc-adc");