meson_saradc.c 40 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
  4. *
  5. * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
  6. */
  7. #include <linux/bitfield.h>
  8. #include <linux/clk.h>
  9. #include <linux/clk-provider.h>
  10. #include <linux/delay.h>
  11. #include <linux/io.h>
  12. #include <linux/iio/iio.h>
  13. #include <linux/module.h>
  14. #include <linux/nvmem-consumer.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/of.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/of_device.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/regmap.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <linux/mfd/syscon.h>
  23. #define MESON_SAR_ADC_REG0 0x00
  24. #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
  25. #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
  26. #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
  27. #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
  28. #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
  29. #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
  30. #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
  31. #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
  32. #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
  33. #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
  34. #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
  35. #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
  36. #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
  37. #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
  38. #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
  39. #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
  40. #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
  41. #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
  42. #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
  43. #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
  44. #define MESON_SAR_ADC_CHAN_LIST 0x04
  45. #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
  46. #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
  47. (GENMASK(2, 0) << ((_chan) * 3))
  48. #define MESON_SAR_ADC_AVG_CNTL 0x08
  49. #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
  50. (16 + ((_chan) * 2))
  51. #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
  52. (GENMASK(17, 16) << ((_chan) * 2))
  53. #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
  54. (0 + ((_chan) * 2))
  55. #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
  56. (GENMASK(1, 0) << ((_chan) * 2))
  57. #define MESON_SAR_ADC_REG3 0x0c
  58. #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
  59. #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
  60. #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
  61. #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
  62. #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
  63. #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
  64. #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
  65. #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
  66. #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
  67. #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
  68. #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
  69. #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
  70. #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
  71. #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
  72. #define MESON_SAR_ADC_DELAY 0x10
  73. #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
  74. #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
  75. #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
  76. #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
  77. #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
  78. #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
  79. #define MESON_SAR_ADC_LAST_RD 0x14
  80. #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
  81. #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
  82. #define MESON_SAR_ADC_FIFO_RD 0x18
  83. #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
  84. #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
  85. #define MESON_SAR_ADC_AUX_SW 0x1c
  86. #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan) \
  87. (8 + (((_chan) - 2) * 3))
  88. #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
  89. #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
  90. #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
  91. #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
  92. #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
  93. #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
  94. #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
  95. #define MESON_SAR_ADC_CHAN_10_SW 0x20
  96. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
  97. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
  98. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
  99. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
  100. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
  101. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
  102. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
  103. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
  104. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
  105. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
  106. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
  107. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
  108. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
  109. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
  110. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
  111. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
  112. #define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
  113. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
  114. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
  115. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
  116. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
  117. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
  118. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
  119. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
  120. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
  121. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
  122. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
  123. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
  124. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
  125. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
  126. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
  127. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
  128. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
  129. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
  130. #define MESON_SAR_ADC_DELTA_10 0x28
  131. #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
  132. #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
  133. #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
  134. #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
  135. #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
  136. #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
  137. #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
  138. /*
  139. * NOTE: registers from here are undocumented (the vendor Linux kernel driver
  140. * and u-boot source served as reference). These only seem to be relevant on
  141. * GXBB and newer.
  142. */
  143. #define MESON_SAR_ADC_REG11 0x2c
  144. #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
  145. #define MESON_SAR_ADC_REG13 0x34
  146. #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
  147. #define MESON_SAR_ADC_MAX_FIFO_SIZE 32
  148. #define MESON_SAR_ADC_TIMEOUT 100 /* ms */
  149. #define MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL 6
  150. #define MESON_SAR_ADC_TEMP_OFFSET 27
  151. /* temperature sensor calibration information in eFuse */
  152. #define MESON_SAR_ADC_EFUSE_BYTES 4
  153. #define MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL GENMASK(6, 0)
  154. #define MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED BIT(7)
  155. #define MESON_HHI_DPLL_TOP_0 0x318
  156. #define MESON_HHI_DPLL_TOP_0_TSC_BIT4 BIT(9)
  157. /* for use with IIO_VAL_INT_PLUS_MICRO */
  158. #define MILLION 1000000
  159. #define MESON_SAR_ADC_CHAN(_chan) { \
  160. .type = IIO_VOLTAGE, \
  161. .indexed = 1, \
  162. .channel = _chan, \
  163. .address = _chan, \
  164. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  165. BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
  166. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  167. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
  168. BIT(IIO_CHAN_INFO_CALIBSCALE), \
  169. .datasheet_name = "SAR_ADC_CH"#_chan, \
  170. }
  171. #define MESON_SAR_ADC_TEMP_CHAN(_chan) { \
  172. .type = IIO_TEMP, \
  173. .channel = _chan, \
  174. .address = MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL, \
  175. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  176. BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
  177. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | \
  178. BIT(IIO_CHAN_INFO_SCALE), \
  179. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
  180. BIT(IIO_CHAN_INFO_CALIBSCALE), \
  181. .datasheet_name = "TEMP_SENSOR", \
  182. }
  183. static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
  184. MESON_SAR_ADC_CHAN(0),
  185. MESON_SAR_ADC_CHAN(1),
  186. MESON_SAR_ADC_CHAN(2),
  187. MESON_SAR_ADC_CHAN(3),
  188. MESON_SAR_ADC_CHAN(4),
  189. MESON_SAR_ADC_CHAN(5),
  190. MESON_SAR_ADC_CHAN(6),
  191. MESON_SAR_ADC_CHAN(7),
  192. IIO_CHAN_SOFT_TIMESTAMP(8),
  193. };
  194. static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = {
  195. MESON_SAR_ADC_CHAN(0),
  196. MESON_SAR_ADC_CHAN(1),
  197. MESON_SAR_ADC_CHAN(2),
  198. MESON_SAR_ADC_CHAN(3),
  199. MESON_SAR_ADC_CHAN(4),
  200. MESON_SAR_ADC_CHAN(5),
  201. MESON_SAR_ADC_CHAN(6),
  202. MESON_SAR_ADC_CHAN(7),
  203. MESON_SAR_ADC_TEMP_CHAN(8),
  204. IIO_CHAN_SOFT_TIMESTAMP(9),
  205. };
  206. enum meson_sar_adc_avg_mode {
  207. NO_AVERAGING = 0x0,
  208. MEAN_AVERAGING = 0x1,
  209. MEDIAN_AVERAGING = 0x2,
  210. };
  211. enum meson_sar_adc_num_samples {
  212. ONE_SAMPLE = 0x0,
  213. TWO_SAMPLES = 0x1,
  214. FOUR_SAMPLES = 0x2,
  215. EIGHT_SAMPLES = 0x3,
  216. };
  217. enum meson_sar_adc_chan7_mux_sel {
  218. CHAN7_MUX_VSS = 0x0,
  219. CHAN7_MUX_VDD_DIV4 = 0x1,
  220. CHAN7_MUX_VDD_DIV2 = 0x2,
  221. CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
  222. CHAN7_MUX_VDD = 0x4,
  223. CHAN7_MUX_CH7_INPUT = 0x7,
  224. };
  225. struct meson_sar_adc_param {
  226. bool has_bl30_integration;
  227. unsigned long clock_rate;
  228. u32 bandgap_reg;
  229. unsigned int resolution;
  230. const struct regmap_config *regmap_config;
  231. u8 temperature_trimming_bits;
  232. unsigned int temperature_multiplier;
  233. unsigned int temperature_divider;
  234. };
  235. struct meson_sar_adc_data {
  236. const struct meson_sar_adc_param *param;
  237. const char *name;
  238. };
  239. struct meson_sar_adc_priv {
  240. struct regmap *regmap;
  241. struct regulator *vref;
  242. const struct meson_sar_adc_param *param;
  243. struct clk *clkin;
  244. struct clk *core_clk;
  245. struct clk *adc_sel_clk;
  246. struct clk *adc_clk;
  247. struct clk_gate clk_gate;
  248. struct clk *adc_div_clk;
  249. struct clk_divider clk_div;
  250. struct completion done;
  251. int calibbias;
  252. int calibscale;
  253. struct regmap *tsc_regmap;
  254. bool temperature_sensor_calibrated;
  255. u8 temperature_sensor_coefficient;
  256. u16 temperature_sensor_adc_val;
  257. };
  258. static const struct regmap_config meson_sar_adc_regmap_config_gxbb = {
  259. .reg_bits = 8,
  260. .val_bits = 32,
  261. .reg_stride = 4,
  262. .max_register = MESON_SAR_ADC_REG13,
  263. };
  264. static const struct regmap_config meson_sar_adc_regmap_config_meson8 = {
  265. .reg_bits = 8,
  266. .val_bits = 32,
  267. .reg_stride = 4,
  268. .max_register = MESON_SAR_ADC_DELTA_10,
  269. };
  270. static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)
  271. {
  272. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  273. u32 regval;
  274. regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
  275. return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
  276. }
  277. static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val)
  278. {
  279. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  280. int tmp;
  281. /* use val_calib = scale * val_raw + offset calibration function */
  282. tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;
  283. return clamp(tmp, 0, (1 << priv->param->resolution) - 1);
  284. }
  285. static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)
  286. {
  287. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  288. int regval, timeout = 10000;
  289. /*
  290. * NOTE: we need a small delay before reading the status, otherwise
  291. * the sample engine may not have started internally (which would
  292. * seem to us that sampling is already finished).
  293. */
  294. do {
  295. udelay(1);
  296. regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
  297. } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
  298. if (timeout < 0)
  299. return -ETIMEDOUT;
  300. return 0;
  301. }
  302. static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,
  303. const struct iio_chan_spec *chan,
  304. int *val)
  305. {
  306. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  307. int regval, fifo_chan, fifo_val, count;
  308. if(!wait_for_completion_timeout(&priv->done,
  309. msecs_to_jiffies(MESON_SAR_ADC_TIMEOUT)))
  310. return -ETIMEDOUT;
  311. count = meson_sar_adc_get_fifo_count(indio_dev);
  312. if (count != 1) {
  313. dev_err(&indio_dev->dev,
  314. "ADC FIFO has %d element(s) instead of one\n", count);
  315. return -EINVAL;
  316. }
  317. regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &regval);
  318. fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
  319. if (fifo_chan != chan->address) {
  320. dev_err(&indio_dev->dev,
  321. "ADC FIFO entry belongs to channel %d instead of %lu\n",
  322. fifo_chan, chan->address);
  323. return -EINVAL;
  324. }
  325. fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);
  326. fifo_val &= GENMASK(priv->param->resolution - 1, 0);
  327. *val = meson_sar_adc_calib_val(indio_dev, fifo_val);
  328. return 0;
  329. }
  330. static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev,
  331. const struct iio_chan_spec *chan,
  332. enum meson_sar_adc_avg_mode mode,
  333. enum meson_sar_adc_num_samples samples)
  334. {
  335. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  336. int val, address = chan->address;
  337. val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(address);
  338. regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
  339. MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(address),
  340. val);
  341. val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(address);
  342. regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
  343. MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(address), val);
  344. }
  345. static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,
  346. const struct iio_chan_spec *chan)
  347. {
  348. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  349. u32 regval;
  350. /*
  351. * the SAR ADC engine allows sampling multiple channels at the same
  352. * time. to keep it simple we're only working with one *internal*
  353. * channel, which starts counting at index 0 (which means: count = 1).
  354. */
  355. regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
  356. regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
  357. MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
  358. /* map channel index 0 to the channel which we want to read */
  359. regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),
  360. chan->address);
  361. regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
  362. MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
  363. regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
  364. chan->address);
  365. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
  366. MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
  367. regval);
  368. regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
  369. chan->address);
  370. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
  371. MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
  372. regval);
  373. if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) {
  374. if (chan->type == IIO_TEMP)
  375. regval = MESON_SAR_ADC_DELTA_10_TEMP_SEL;
  376. else
  377. regval = 0;
  378. regmap_update_bits(priv->regmap,
  379. MESON_SAR_ADC_DELTA_10,
  380. MESON_SAR_ADC_DELTA_10_TEMP_SEL, regval);
  381. }
  382. }
  383. static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,
  384. enum meson_sar_adc_chan7_mux_sel sel)
  385. {
  386. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  387. u32 regval;
  388. regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
  389. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
  390. MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
  391. usleep_range(10, 20);
  392. }
  393. static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev)
  394. {
  395. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  396. reinit_completion(&priv->done);
  397. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  398. MESON_SAR_ADC_REG0_FIFO_IRQ_EN,
  399. MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
  400. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  401. MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
  402. MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
  403. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  404. MESON_SAR_ADC_REG0_SAMPLING_START,
  405. MESON_SAR_ADC_REG0_SAMPLING_START);
  406. }
  407. static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev)
  408. {
  409. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  410. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  411. MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 0);
  412. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  413. MESON_SAR_ADC_REG0_SAMPLING_STOP,
  414. MESON_SAR_ADC_REG0_SAMPLING_STOP);
  415. /* wait until all modules are stopped */
  416. meson_sar_adc_wait_busy_clear(indio_dev);
  417. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  418. MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
  419. }
  420. static int meson_sar_adc_lock(struct iio_dev *indio_dev)
  421. {
  422. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  423. int val, timeout = 10000;
  424. mutex_lock(&indio_dev->mlock);
  425. if (priv->param->has_bl30_integration) {
  426. /* prevent BL30 from using the SAR ADC while we are using it */
  427. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  428. MESON_SAR_ADC_DELAY_KERNEL_BUSY,
  429. MESON_SAR_ADC_DELAY_KERNEL_BUSY);
  430. /*
  431. * wait until BL30 releases it's lock (so we can use the SAR
  432. * ADC)
  433. */
  434. do {
  435. udelay(1);
  436. regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
  437. } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
  438. if (timeout < 0) {
  439. mutex_unlock(&indio_dev->mlock);
  440. return -ETIMEDOUT;
  441. }
  442. }
  443. return 0;
  444. }
  445. static void meson_sar_adc_unlock(struct iio_dev *indio_dev)
  446. {
  447. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  448. if (priv->param->has_bl30_integration)
  449. /* allow BL30 to use the SAR ADC again */
  450. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  451. MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
  452. mutex_unlock(&indio_dev->mlock);
  453. }
  454. static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)
  455. {
  456. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  457. unsigned int count, tmp;
  458. for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
  459. if (!meson_sar_adc_get_fifo_count(indio_dev))
  460. break;
  461. regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);
  462. }
  463. }
  464. static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,
  465. const struct iio_chan_spec *chan,
  466. enum meson_sar_adc_avg_mode avg_mode,
  467. enum meson_sar_adc_num_samples avg_samples,
  468. int *val)
  469. {
  470. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  471. int ret;
  472. if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated)
  473. return -ENOTSUPP;
  474. ret = meson_sar_adc_lock(indio_dev);
  475. if (ret)
  476. return ret;
  477. /* clear the FIFO to make sure we're not reading old values */
  478. meson_sar_adc_clear_fifo(indio_dev);
  479. meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
  480. meson_sar_adc_enable_channel(indio_dev, chan);
  481. meson_sar_adc_start_sample_engine(indio_dev);
  482. ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val);
  483. meson_sar_adc_stop_sample_engine(indio_dev);
  484. meson_sar_adc_unlock(indio_dev);
  485. if (ret) {
  486. dev_warn(indio_dev->dev.parent,
  487. "failed to read sample for channel %lu: %d\n",
  488. chan->address, ret);
  489. return ret;
  490. }
  491. return IIO_VAL_INT;
  492. }
  493. static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
  494. const struct iio_chan_spec *chan,
  495. int *val, int *val2, long mask)
  496. {
  497. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  498. int ret;
  499. switch (mask) {
  500. case IIO_CHAN_INFO_RAW:
  501. return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING,
  502. ONE_SAMPLE, val);
  503. break;
  504. case IIO_CHAN_INFO_AVERAGE_RAW:
  505. return meson_sar_adc_get_sample(indio_dev, chan,
  506. MEAN_AVERAGING, EIGHT_SAMPLES,
  507. val);
  508. break;
  509. case IIO_CHAN_INFO_SCALE:
  510. if (chan->type == IIO_VOLTAGE) {
  511. ret = regulator_get_voltage(priv->vref);
  512. if (ret < 0) {
  513. dev_err(indio_dev->dev.parent,
  514. "failed to get vref voltage: %d\n",
  515. ret);
  516. return ret;
  517. }
  518. *val = ret / 1000;
  519. *val2 = priv->param->resolution;
  520. return IIO_VAL_FRACTIONAL_LOG2;
  521. } else if (chan->type == IIO_TEMP) {
  522. /* SoC specific multiplier and divider */
  523. *val = priv->param->temperature_multiplier;
  524. *val2 = priv->param->temperature_divider;
  525. /* celsius to millicelsius */
  526. *val *= 1000;
  527. return IIO_VAL_FRACTIONAL;
  528. } else {
  529. return -EINVAL;
  530. }
  531. case IIO_CHAN_INFO_CALIBBIAS:
  532. *val = priv->calibbias;
  533. return IIO_VAL_INT;
  534. case IIO_CHAN_INFO_CALIBSCALE:
  535. *val = priv->calibscale / MILLION;
  536. *val2 = priv->calibscale % MILLION;
  537. return IIO_VAL_INT_PLUS_MICRO;
  538. case IIO_CHAN_INFO_OFFSET:
  539. *val = DIV_ROUND_CLOSEST(MESON_SAR_ADC_TEMP_OFFSET *
  540. priv->param->temperature_divider,
  541. priv->param->temperature_multiplier);
  542. *val -= priv->temperature_sensor_adc_val;
  543. return IIO_VAL_INT;
  544. default:
  545. return -EINVAL;
  546. }
  547. }
  548. static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
  549. void __iomem *base)
  550. {
  551. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  552. struct clk_init_data init;
  553. const char *clk_parents[1];
  554. init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
  555. dev_name(indio_dev->dev.parent));
  556. if (!init.name)
  557. return -ENOMEM;
  558. init.flags = 0;
  559. init.ops = &clk_divider_ops;
  560. clk_parents[0] = __clk_get_name(priv->clkin);
  561. init.parent_names = clk_parents;
  562. init.num_parents = 1;
  563. priv->clk_div.reg = base + MESON_SAR_ADC_REG3;
  564. priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
  565. priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
  566. priv->clk_div.hw.init = &init;
  567. priv->clk_div.flags = 0;
  568. priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
  569. &priv->clk_div.hw);
  570. if (WARN_ON(IS_ERR(priv->adc_div_clk)))
  571. return PTR_ERR(priv->adc_div_clk);
  572. init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
  573. dev_name(indio_dev->dev.parent));
  574. if (!init.name)
  575. return -ENOMEM;
  576. init.flags = CLK_SET_RATE_PARENT;
  577. init.ops = &clk_gate_ops;
  578. clk_parents[0] = __clk_get_name(priv->adc_div_clk);
  579. init.parent_names = clk_parents;
  580. init.num_parents = 1;
  581. priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
  582. priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN);
  583. priv->clk_gate.hw.init = &init;
  584. priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
  585. if (WARN_ON(IS_ERR(priv->adc_clk)))
  586. return PTR_ERR(priv->adc_clk);
  587. return 0;
  588. }
  589. static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev)
  590. {
  591. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  592. u8 *buf, trimming_bits, trimming_mask, upper_adc_val;
  593. struct nvmem_cell *temperature_calib;
  594. size_t read_len;
  595. int ret;
  596. temperature_calib = devm_nvmem_cell_get(indio_dev->dev.parent,
  597. "temperature_calib");
  598. if (IS_ERR(temperature_calib)) {
  599. ret = PTR_ERR(temperature_calib);
  600. /*
  601. * leave the temperature sensor disabled if no calibration data
  602. * was passed via nvmem-cells.
  603. */
  604. if (ret == -ENODEV)
  605. return 0;
  606. return dev_err_probe(indio_dev->dev.parent, ret,
  607. "failed to get temperature_calib cell\n");
  608. }
  609. priv->tsc_regmap =
  610. syscon_regmap_lookup_by_phandle(indio_dev->dev.parent->of_node,
  611. "amlogic,hhi-sysctrl");
  612. if (IS_ERR(priv->tsc_regmap)) {
  613. dev_err(indio_dev->dev.parent,
  614. "failed to get amlogic,hhi-sysctrl regmap\n");
  615. return PTR_ERR(priv->tsc_regmap);
  616. }
  617. read_len = MESON_SAR_ADC_EFUSE_BYTES;
  618. buf = nvmem_cell_read(temperature_calib, &read_len);
  619. if (IS_ERR(buf)) {
  620. dev_err(indio_dev->dev.parent,
  621. "failed to read temperature_calib cell\n");
  622. return PTR_ERR(buf);
  623. } else if (read_len != MESON_SAR_ADC_EFUSE_BYTES) {
  624. kfree(buf);
  625. dev_err(indio_dev->dev.parent,
  626. "invalid read size of temperature_calib cell\n");
  627. return -EINVAL;
  628. }
  629. trimming_bits = priv->param->temperature_trimming_bits;
  630. trimming_mask = BIT(trimming_bits) - 1;
  631. priv->temperature_sensor_calibrated =
  632. buf[3] & MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED;
  633. priv->temperature_sensor_coefficient = buf[2] & trimming_mask;
  634. upper_adc_val = FIELD_GET(MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL,
  635. buf[3]);
  636. priv->temperature_sensor_adc_val = buf[2];
  637. priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE;
  638. priv->temperature_sensor_adc_val >>= trimming_bits;
  639. kfree(buf);
  640. return 0;
  641. }
  642. static int meson_sar_adc_init(struct iio_dev *indio_dev)
  643. {
  644. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  645. int regval, i, ret;
  646. /*
  647. * make sure we start at CH7 input since the other muxes are only used
  648. * for internal calibration.
  649. */
  650. meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
  651. if (priv->param->has_bl30_integration) {
  652. /*
  653. * leave sampling delay and the input clocks as configured by
  654. * BL30 to make sure BL30 gets the values it expects when
  655. * reading the temperature sensor.
  656. */
  657. regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);
  658. if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
  659. return 0;
  660. }
  661. meson_sar_adc_stop_sample_engine(indio_dev);
  662. /*
  663. * disable this bit as seems to be only relevant for Meson6 (based
  664. * on the vendor driver), which we don't support at the moment.
  665. */
  666. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  667. MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL, 0);
  668. /* disable all channels by default */
  669. regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
  670. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
  671. MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
  672. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
  673. MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
  674. MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
  675. /* delay between two samples = (10+1) * 1uS */
  676. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  677. MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
  678. FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
  679. 10));
  680. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  681. MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
  682. FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
  683. 0));
  684. /* delay between two samples = (10+1) * 1uS */
  685. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  686. MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
  687. FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
  688. 10));
  689. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  690. MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
  691. FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
  692. 1));
  693. /*
  694. * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW
  695. * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1)
  696. */
  697. regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0);
  698. regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
  699. MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,
  700. regval);
  701. regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1);
  702. regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
  703. MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
  704. regval);
  705. /*
  706. * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
  707. * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
  708. * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and
  709. * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver.
  710. */
  711. regval = 0;
  712. for (i = 2; i <= 7; i++)
  713. regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i);
  714. regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW;
  715. regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;
  716. regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);
  717. if (priv->temperature_sensor_calibrated) {
  718. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
  719. MESON_SAR_ADC_DELTA_10_TS_REVE1,
  720. MESON_SAR_ADC_DELTA_10_TS_REVE1);
  721. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
  722. MESON_SAR_ADC_DELTA_10_TS_REVE0,
  723. MESON_SAR_ADC_DELTA_10_TS_REVE0);
  724. /*
  725. * set bits [3:0] of the TSC (temperature sensor coefficient)
  726. * to get the correct values when reading the temperature.
  727. */
  728. regval = FIELD_PREP(MESON_SAR_ADC_DELTA_10_TS_C_MASK,
  729. priv->temperature_sensor_coefficient);
  730. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
  731. MESON_SAR_ADC_DELTA_10_TS_C_MASK, regval);
  732. if (priv->param->temperature_trimming_bits == 5) {
  733. if (priv->temperature_sensor_coefficient & BIT(4))
  734. regval = MESON_HHI_DPLL_TOP_0_TSC_BIT4;
  735. else
  736. regval = 0;
  737. /*
  738. * bit [4] (the 5th bit when starting to count at 1)
  739. * of the TSC is located in the HHI register area.
  740. */
  741. regmap_update_bits(priv->tsc_regmap,
  742. MESON_HHI_DPLL_TOP_0,
  743. MESON_HHI_DPLL_TOP_0_TSC_BIT4,
  744. regval);
  745. }
  746. } else {
  747. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
  748. MESON_SAR_ADC_DELTA_10_TS_REVE1, 0);
  749. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
  750. MESON_SAR_ADC_DELTA_10_TS_REVE0, 0);
  751. }
  752. ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
  753. if (ret) {
  754. dev_err(indio_dev->dev.parent,
  755. "failed to set adc parent to clkin\n");
  756. return ret;
  757. }
  758. ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate);
  759. if (ret) {
  760. dev_err(indio_dev->dev.parent,
  761. "failed to set adc clock rate\n");
  762. return ret;
  763. }
  764. return 0;
  765. }
  766. static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off)
  767. {
  768. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  769. const struct meson_sar_adc_param *param = priv->param;
  770. u32 enable_mask;
  771. if (param->bandgap_reg == MESON_SAR_ADC_REG11)
  772. enable_mask = MESON_SAR_ADC_REG11_BANDGAP_EN;
  773. else
  774. enable_mask = MESON_SAR_ADC_DELTA_10_TS_VBG_EN;
  775. regmap_update_bits(priv->regmap, param->bandgap_reg, enable_mask,
  776. on_off ? enable_mask : 0);
  777. }
  778. static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
  779. {
  780. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  781. int ret;
  782. u32 regval;
  783. ret = meson_sar_adc_lock(indio_dev);
  784. if (ret)
  785. goto err_lock;
  786. ret = regulator_enable(priv->vref);
  787. if (ret < 0) {
  788. dev_err(indio_dev->dev.parent,
  789. "failed to enable vref regulator\n");
  790. goto err_vref;
  791. }
  792. ret = clk_prepare_enable(priv->core_clk);
  793. if (ret) {
  794. dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
  795. goto err_core_clk;
  796. }
  797. regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
  798. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  799. MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
  800. meson_sar_adc_set_bandgap(indio_dev, true);
  801. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
  802. MESON_SAR_ADC_REG3_ADC_EN,
  803. MESON_SAR_ADC_REG3_ADC_EN);
  804. udelay(5);
  805. ret = clk_prepare_enable(priv->adc_clk);
  806. if (ret) {
  807. dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
  808. goto err_adc_clk;
  809. }
  810. meson_sar_adc_unlock(indio_dev);
  811. return 0;
  812. err_adc_clk:
  813. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
  814. MESON_SAR_ADC_REG3_ADC_EN, 0);
  815. meson_sar_adc_set_bandgap(indio_dev, false);
  816. clk_disable_unprepare(priv->core_clk);
  817. err_core_clk:
  818. regulator_disable(priv->vref);
  819. err_vref:
  820. meson_sar_adc_unlock(indio_dev);
  821. err_lock:
  822. return ret;
  823. }
  824. static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
  825. {
  826. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  827. int ret;
  828. ret = meson_sar_adc_lock(indio_dev);
  829. if (ret)
  830. return ret;
  831. clk_disable_unprepare(priv->adc_clk);
  832. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
  833. MESON_SAR_ADC_REG3_ADC_EN, 0);
  834. meson_sar_adc_set_bandgap(indio_dev, false);
  835. clk_disable_unprepare(priv->core_clk);
  836. regulator_disable(priv->vref);
  837. meson_sar_adc_unlock(indio_dev);
  838. return 0;
  839. }
  840. static irqreturn_t meson_sar_adc_irq(int irq, void *data)
  841. {
  842. struct iio_dev *indio_dev = data;
  843. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  844. unsigned int cnt, threshold;
  845. u32 regval;
  846. regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
  847. cnt = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
  848. threshold = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
  849. if (cnt < threshold)
  850. return IRQ_NONE;
  851. complete(&priv->done);
  852. return IRQ_HANDLED;
  853. }
  854. static int meson_sar_adc_calib(struct iio_dev *indio_dev)
  855. {
  856. struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
  857. int ret, nominal0, nominal1, value0, value1;
  858. /* use points 25% and 75% for calibration */
  859. nominal0 = (1 << priv->param->resolution) / 4;
  860. nominal1 = (1 << priv->param->resolution) * 3 / 4;
  861. meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_DIV4);
  862. usleep_range(10, 20);
  863. ret = meson_sar_adc_get_sample(indio_dev,
  864. &indio_dev->channels[7],
  865. MEAN_AVERAGING, EIGHT_SAMPLES, &value0);
  866. if (ret < 0)
  867. goto out;
  868. meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_MUL3_DIV4);
  869. usleep_range(10, 20);
  870. ret = meson_sar_adc_get_sample(indio_dev,
  871. &indio_dev->channels[7],
  872. MEAN_AVERAGING, EIGHT_SAMPLES, &value1);
  873. if (ret < 0)
  874. goto out;
  875. if (value1 <= value0) {
  876. ret = -EINVAL;
  877. goto out;
  878. }
  879. priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,
  880. value1 - value0);
  881. priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,
  882. MILLION);
  883. ret = 0;
  884. out:
  885. meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
  886. return ret;
  887. }
  888. static const struct iio_info meson_sar_adc_iio_info = {
  889. .read_raw = meson_sar_adc_iio_info_read_raw,
  890. };
  891. static const struct meson_sar_adc_param meson_sar_adc_meson8_param = {
  892. .has_bl30_integration = false,
  893. .clock_rate = 1150000,
  894. .bandgap_reg = MESON_SAR_ADC_DELTA_10,
  895. .regmap_config = &meson_sar_adc_regmap_config_meson8,
  896. .resolution = 10,
  897. .temperature_trimming_bits = 4,
  898. .temperature_multiplier = 18 * 10000,
  899. .temperature_divider = 1024 * 10 * 85,
  900. };
  901. static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = {
  902. .has_bl30_integration = false,
  903. .clock_rate = 1150000,
  904. .bandgap_reg = MESON_SAR_ADC_DELTA_10,
  905. .regmap_config = &meson_sar_adc_regmap_config_meson8,
  906. .resolution = 10,
  907. .temperature_trimming_bits = 5,
  908. .temperature_multiplier = 10,
  909. .temperature_divider = 32,
  910. };
  911. static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
  912. .has_bl30_integration = true,
  913. .clock_rate = 1200000,
  914. .bandgap_reg = MESON_SAR_ADC_REG11,
  915. .regmap_config = &meson_sar_adc_regmap_config_gxbb,
  916. .resolution = 10,
  917. };
  918. static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
  919. .has_bl30_integration = true,
  920. .clock_rate = 1200000,
  921. .bandgap_reg = MESON_SAR_ADC_REG11,
  922. .regmap_config = &meson_sar_adc_regmap_config_gxbb,
  923. .resolution = 12,
  924. };
  925. static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {
  926. .param = &meson_sar_adc_meson8_param,
  927. .name = "meson-meson8-saradc",
  928. };
  929. static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = {
  930. .param = &meson_sar_adc_meson8b_param,
  931. .name = "meson-meson8b-saradc",
  932. };
  933. static const struct meson_sar_adc_data meson_sar_adc_meson8m2_data = {
  934. .param = &meson_sar_adc_meson8b_param,
  935. .name = "meson-meson8m2-saradc",
  936. };
  937. static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
  938. .param = &meson_sar_adc_gxbb_param,
  939. .name = "meson-gxbb-saradc",
  940. };
  941. static const struct meson_sar_adc_data meson_sar_adc_gxl_data = {
  942. .param = &meson_sar_adc_gxl_param,
  943. .name = "meson-gxl-saradc",
  944. };
  945. static const struct meson_sar_adc_data meson_sar_adc_gxm_data = {
  946. .param = &meson_sar_adc_gxl_param,
  947. .name = "meson-gxm-saradc",
  948. };
  949. static const struct meson_sar_adc_data meson_sar_adc_axg_data = {
  950. .param = &meson_sar_adc_gxl_param,
  951. .name = "meson-axg-saradc",
  952. };
  953. static const struct meson_sar_adc_data meson_sar_adc_g12a_data = {
  954. .param = &meson_sar_adc_gxl_param,
  955. .name = "meson-g12a-saradc",
  956. };
  957. static const struct of_device_id meson_sar_adc_of_match[] = {
  958. {
  959. .compatible = "amlogic,meson8-saradc",
  960. .data = &meson_sar_adc_meson8_data,
  961. }, {
  962. .compatible = "amlogic,meson8b-saradc",
  963. .data = &meson_sar_adc_meson8b_data,
  964. }, {
  965. .compatible = "amlogic,meson8m2-saradc",
  966. .data = &meson_sar_adc_meson8m2_data,
  967. }, {
  968. .compatible = "amlogic,meson-gxbb-saradc",
  969. .data = &meson_sar_adc_gxbb_data,
  970. }, {
  971. .compatible = "amlogic,meson-gxl-saradc",
  972. .data = &meson_sar_adc_gxl_data,
  973. }, {
  974. .compatible = "amlogic,meson-gxm-saradc",
  975. .data = &meson_sar_adc_gxm_data,
  976. }, {
  977. .compatible = "amlogic,meson-axg-saradc",
  978. .data = &meson_sar_adc_axg_data,
  979. }, {
  980. .compatible = "amlogic,meson-g12a-saradc",
  981. .data = &meson_sar_adc_g12a_data,
  982. },
  983. { /* sentinel */ }
  984. };
  985. MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match);
  986. static int meson_sar_adc_probe(struct platform_device *pdev)
  987. {
  988. const struct meson_sar_adc_data *match_data;
  989. struct meson_sar_adc_priv *priv;
  990. struct iio_dev *indio_dev;
  991. void __iomem *base;
  992. int irq, ret;
  993. indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
  994. if (!indio_dev) {
  995. dev_err(&pdev->dev, "failed allocating iio device\n");
  996. return -ENOMEM;
  997. }
  998. priv = iio_priv(indio_dev);
  999. init_completion(&priv->done);
  1000. match_data = of_device_get_match_data(&pdev->dev);
  1001. if (!match_data) {
  1002. dev_err(&pdev->dev, "failed to get match data\n");
  1003. return -ENODEV;
  1004. }
  1005. priv->param = match_data->param;
  1006. indio_dev->name = match_data->name;
  1007. indio_dev->modes = INDIO_DIRECT_MODE;
  1008. indio_dev->info = &meson_sar_adc_iio_info;
  1009. base = devm_platform_ioremap_resource(pdev, 0);
  1010. if (IS_ERR(base))
  1011. return PTR_ERR(base);
  1012. priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
  1013. priv->param->regmap_config);
  1014. if (IS_ERR(priv->regmap))
  1015. return PTR_ERR(priv->regmap);
  1016. irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
  1017. if (!irq)
  1018. return -EINVAL;
  1019. ret = devm_request_irq(&pdev->dev, irq, meson_sar_adc_irq, IRQF_SHARED,
  1020. dev_name(&pdev->dev), indio_dev);
  1021. if (ret)
  1022. return ret;
  1023. priv->clkin = devm_clk_get(&pdev->dev, "clkin");
  1024. if (IS_ERR(priv->clkin)) {
  1025. dev_err(&pdev->dev, "failed to get clkin\n");
  1026. return PTR_ERR(priv->clkin);
  1027. }
  1028. priv->core_clk = devm_clk_get(&pdev->dev, "core");
  1029. if (IS_ERR(priv->core_clk)) {
  1030. dev_err(&pdev->dev, "failed to get core clk\n");
  1031. return PTR_ERR(priv->core_clk);
  1032. }
  1033. priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
  1034. if (IS_ERR(priv->adc_clk)) {
  1035. if (PTR_ERR(priv->adc_clk) == -ENOENT) {
  1036. priv->adc_clk = NULL;
  1037. } else {
  1038. dev_err(&pdev->dev, "failed to get adc clk\n");
  1039. return PTR_ERR(priv->adc_clk);
  1040. }
  1041. }
  1042. priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
  1043. if (IS_ERR(priv->adc_sel_clk)) {
  1044. if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
  1045. priv->adc_sel_clk = NULL;
  1046. } else {
  1047. dev_err(&pdev->dev, "failed to get adc_sel clk\n");
  1048. return PTR_ERR(priv->adc_sel_clk);
  1049. }
  1050. }
  1051. /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
  1052. if (!priv->adc_clk) {
  1053. ret = meson_sar_adc_clk_init(indio_dev, base);
  1054. if (ret)
  1055. return ret;
  1056. }
  1057. priv->vref = devm_regulator_get(&pdev->dev, "vref");
  1058. if (IS_ERR(priv->vref)) {
  1059. dev_err(&pdev->dev, "failed to get vref regulator\n");
  1060. return PTR_ERR(priv->vref);
  1061. }
  1062. priv->calibscale = MILLION;
  1063. if (priv->param->temperature_trimming_bits) {
  1064. ret = meson_sar_adc_temp_sensor_init(indio_dev);
  1065. if (ret)
  1066. return ret;
  1067. }
  1068. if (priv->temperature_sensor_calibrated) {
  1069. indio_dev->channels = meson_sar_adc_and_temp_iio_channels;
  1070. indio_dev->num_channels =
  1071. ARRAY_SIZE(meson_sar_adc_and_temp_iio_channels);
  1072. } else {
  1073. indio_dev->channels = meson_sar_adc_iio_channels;
  1074. indio_dev->num_channels =
  1075. ARRAY_SIZE(meson_sar_adc_iio_channels);
  1076. }
  1077. ret = meson_sar_adc_init(indio_dev);
  1078. if (ret)
  1079. goto err;
  1080. ret = meson_sar_adc_hw_enable(indio_dev);
  1081. if (ret)
  1082. goto err;
  1083. ret = meson_sar_adc_calib(indio_dev);
  1084. if (ret)
  1085. dev_warn(&pdev->dev, "calibration failed\n");
  1086. platform_set_drvdata(pdev, indio_dev);
  1087. ret = iio_device_register(indio_dev);
  1088. if (ret)
  1089. goto err_hw;
  1090. return 0;
  1091. err_hw:
  1092. meson_sar_adc_hw_disable(indio_dev);
  1093. err:
  1094. return ret;
  1095. }
  1096. static int meson_sar_adc_remove(struct platform_device *pdev)
  1097. {
  1098. struct iio_dev *indio_dev = platform_get_drvdata(pdev);
  1099. iio_device_unregister(indio_dev);
  1100. return meson_sar_adc_hw_disable(indio_dev);
  1101. }
  1102. static int __maybe_unused meson_sar_adc_suspend(struct device *dev)
  1103. {
  1104. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  1105. return meson_sar_adc_hw_disable(indio_dev);
  1106. }
  1107. static int __maybe_unused meson_sar_adc_resume(struct device *dev)
  1108. {
  1109. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  1110. return meson_sar_adc_hw_enable(indio_dev);
  1111. }
  1112. static SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
  1113. meson_sar_adc_suspend, meson_sar_adc_resume);
  1114. static struct platform_driver meson_sar_adc_driver = {
  1115. .probe = meson_sar_adc_probe,
  1116. .remove = meson_sar_adc_remove,
  1117. .driver = {
  1118. .name = "meson-saradc",
  1119. .of_match_table = meson_sar_adc_of_match,
  1120. .pm = &meson_sar_adc_pm_ops,
  1121. },
  1122. };
  1123. module_platform_driver(meson_sar_adc_driver);
  1124. MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
  1125. MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
  1126. MODULE_LICENSE("GPL v2");