mcp3911.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for Microchip MCP3911, Two-channel Analog Front End
  4. *
  5. * Copyright (C) 2018 Marcus Folkesson <marcus.folkesson@gmail.com>
  6. * Copyright (C) 2018 Kent Gustavsson <kent@minoris.se>
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/err.h>
  11. #include <linux/iio/iio.h>
  12. #include <linux/module.h>
  13. #include <linux/regulator/consumer.h>
  14. #include <linux/spi/spi.h>
  15. #define MCP3911_REG_CHANNEL0 0x00
  16. #define MCP3911_REG_CHANNEL1 0x03
  17. #define MCP3911_REG_MOD 0x06
  18. #define MCP3911_REG_PHASE 0x07
  19. #define MCP3911_REG_GAIN 0x09
  20. #define MCP3911_REG_STATUSCOM 0x0a
  21. #define MCP3911_STATUSCOM_CH1_24WIDTH BIT(4)
  22. #define MCP3911_STATUSCOM_CH0_24WIDTH BIT(3)
  23. #define MCP3911_STATUSCOM_EN_OFFCAL BIT(2)
  24. #define MCP3911_STATUSCOM_EN_GAINCAL BIT(1)
  25. #define MCP3911_REG_CONFIG 0x0c
  26. #define MCP3911_CONFIG_CLKEXT BIT(1)
  27. #define MCP3911_CONFIG_VREFEXT BIT(2)
  28. #define MCP3911_REG_OFFCAL_CH0 0x0e
  29. #define MCP3911_REG_GAINCAL_CH0 0x11
  30. #define MCP3911_REG_OFFCAL_CH1 0x14
  31. #define MCP3911_REG_GAINCAL_CH1 0x17
  32. #define MCP3911_REG_VREFCAL 0x1a
  33. #define MCP3911_CHANNEL(x) (MCP3911_REG_CHANNEL0 + x * 3)
  34. #define MCP3911_OFFCAL(x) (MCP3911_REG_OFFCAL_CH0 + x * 6)
  35. /* Internal voltage reference in uV */
  36. #define MCP3911_INT_VREF_UV 1200000
  37. #define MCP3911_REG_READ(reg, id) ((((reg) << 1) | ((id) << 5) | (1 << 0)) & 0xff)
  38. #define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 5) | (0 << 0)) & 0xff)
  39. #define MCP3911_NUM_CHANNELS 2
  40. struct mcp3911 {
  41. struct spi_device *spi;
  42. struct mutex lock;
  43. struct regulator *vref;
  44. struct clk *clki;
  45. u32 dev_addr;
  46. };
  47. static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len)
  48. {
  49. int ret;
  50. reg = MCP3911_REG_READ(reg, adc->dev_addr);
  51. ret = spi_write_then_read(adc->spi, &reg, 1, val, len);
  52. if (ret < 0)
  53. return ret;
  54. be32_to_cpus(val);
  55. *val >>= ((4 - len) * 8);
  56. dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%x\n", *val,
  57. reg >> 1);
  58. return ret;
  59. }
  60. static int mcp3911_write(struct mcp3911 *adc, u8 reg, u32 val, u8 len)
  61. {
  62. dev_dbg(&adc->spi->dev, "writing 0x%x to register 0x%x\n", val, reg);
  63. val <<= (3 - len) * 8;
  64. cpu_to_be32s(&val);
  65. val |= MCP3911_REG_WRITE(reg, adc->dev_addr);
  66. return spi_write(adc->spi, &val, len + 1);
  67. }
  68. static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask,
  69. u32 val, u8 len)
  70. {
  71. u32 tmp;
  72. int ret;
  73. ret = mcp3911_read(adc, reg, &tmp, len);
  74. if (ret)
  75. return ret;
  76. val &= mask;
  77. val |= tmp & ~mask;
  78. return mcp3911_write(adc, reg, val, len);
  79. }
  80. static int mcp3911_read_raw(struct iio_dev *indio_dev,
  81. struct iio_chan_spec const *channel, int *val,
  82. int *val2, long mask)
  83. {
  84. struct mcp3911 *adc = iio_priv(indio_dev);
  85. int ret = -EINVAL;
  86. mutex_lock(&adc->lock);
  87. switch (mask) {
  88. case IIO_CHAN_INFO_RAW:
  89. ret = mcp3911_read(adc,
  90. MCP3911_CHANNEL(channel->channel), val, 3);
  91. if (ret)
  92. goto out;
  93. ret = IIO_VAL_INT;
  94. break;
  95. case IIO_CHAN_INFO_OFFSET:
  96. ret = mcp3911_read(adc,
  97. MCP3911_OFFCAL(channel->channel), val, 3);
  98. if (ret)
  99. goto out;
  100. ret = IIO_VAL_INT;
  101. break;
  102. case IIO_CHAN_INFO_SCALE:
  103. if (adc->vref) {
  104. ret = regulator_get_voltage(adc->vref);
  105. if (ret < 0) {
  106. dev_err(indio_dev->dev.parent,
  107. "failed to get vref voltage: %d\n",
  108. ret);
  109. goto out;
  110. }
  111. *val = ret / 1000;
  112. } else {
  113. *val = MCP3911_INT_VREF_UV;
  114. }
  115. *val2 = 24;
  116. ret = IIO_VAL_FRACTIONAL_LOG2;
  117. break;
  118. }
  119. out:
  120. mutex_unlock(&adc->lock);
  121. return ret;
  122. }
  123. static int mcp3911_write_raw(struct iio_dev *indio_dev,
  124. struct iio_chan_spec const *channel, int val,
  125. int val2, long mask)
  126. {
  127. struct mcp3911 *adc = iio_priv(indio_dev);
  128. int ret = -EINVAL;
  129. mutex_lock(&adc->lock);
  130. switch (mask) {
  131. case IIO_CHAN_INFO_OFFSET:
  132. if (val2 != 0) {
  133. ret = -EINVAL;
  134. goto out;
  135. }
  136. /* Write offset */
  137. ret = mcp3911_write(adc, MCP3911_OFFCAL(channel->channel), val,
  138. 3);
  139. if (ret)
  140. goto out;
  141. /* Enable offset*/
  142. ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM,
  143. MCP3911_STATUSCOM_EN_OFFCAL,
  144. MCP3911_STATUSCOM_EN_OFFCAL, 2);
  145. break;
  146. }
  147. out:
  148. mutex_unlock(&adc->lock);
  149. return ret;
  150. }
  151. #define MCP3911_CHAN(idx) { \
  152. .type = IIO_VOLTAGE, \
  153. .indexed = 1, \
  154. .channel = idx, \
  155. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  156. BIT(IIO_CHAN_INFO_OFFSET) | \
  157. BIT(IIO_CHAN_INFO_SCALE), \
  158. }
  159. static const struct iio_chan_spec mcp3911_channels[] = {
  160. MCP3911_CHAN(0),
  161. MCP3911_CHAN(1),
  162. };
  163. static const struct iio_info mcp3911_info = {
  164. .read_raw = mcp3911_read_raw,
  165. .write_raw = mcp3911_write_raw,
  166. };
  167. static int mcp3911_config(struct mcp3911 *adc, struct device_node *of_node)
  168. {
  169. u32 configreg;
  170. int ret;
  171. of_property_read_u32(of_node, "device-addr", &adc->dev_addr);
  172. if (adc->dev_addr > 3) {
  173. dev_err(&adc->spi->dev,
  174. "invalid device address (%i). Must be in range 0-3.\n",
  175. adc->dev_addr);
  176. return -EINVAL;
  177. }
  178. dev_dbg(&adc->spi->dev, "use device address %i\n", adc->dev_addr);
  179. ret = mcp3911_read(adc, MCP3911_REG_CONFIG, &configreg, 2);
  180. if (ret)
  181. return ret;
  182. if (adc->vref) {
  183. dev_dbg(&adc->spi->dev, "use external voltage reference\n");
  184. configreg |= MCP3911_CONFIG_VREFEXT;
  185. } else {
  186. dev_dbg(&adc->spi->dev,
  187. "use internal voltage reference (1.2V)\n");
  188. configreg &= ~MCP3911_CONFIG_VREFEXT;
  189. }
  190. if (adc->clki) {
  191. dev_dbg(&adc->spi->dev, "use external clock as clocksource\n");
  192. configreg |= MCP3911_CONFIG_CLKEXT;
  193. } else {
  194. dev_dbg(&adc->spi->dev,
  195. "use crystal oscillator as clocksource\n");
  196. configreg &= ~MCP3911_CONFIG_CLKEXT;
  197. }
  198. return mcp3911_write(adc, MCP3911_REG_CONFIG, configreg, 2);
  199. }
  200. static int mcp3911_probe(struct spi_device *spi)
  201. {
  202. struct iio_dev *indio_dev;
  203. struct mcp3911 *adc;
  204. int ret;
  205. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
  206. if (!indio_dev)
  207. return -ENOMEM;
  208. adc = iio_priv(indio_dev);
  209. adc->spi = spi;
  210. adc->vref = devm_regulator_get_optional(&adc->spi->dev, "vref");
  211. if (IS_ERR(adc->vref)) {
  212. if (PTR_ERR(adc->vref) == -ENODEV) {
  213. adc->vref = NULL;
  214. } else {
  215. dev_err(&adc->spi->dev,
  216. "failed to get regulator (%ld)\n",
  217. PTR_ERR(adc->vref));
  218. return PTR_ERR(adc->vref);
  219. }
  220. } else {
  221. ret = regulator_enable(adc->vref);
  222. if (ret)
  223. return ret;
  224. }
  225. adc->clki = devm_clk_get(&adc->spi->dev, NULL);
  226. if (IS_ERR(adc->clki)) {
  227. if (PTR_ERR(adc->clki) == -ENOENT) {
  228. adc->clki = NULL;
  229. } else {
  230. dev_err(&adc->spi->dev,
  231. "failed to get adc clk (%ld)\n",
  232. PTR_ERR(adc->clki));
  233. ret = PTR_ERR(adc->clki);
  234. goto reg_disable;
  235. }
  236. } else {
  237. ret = clk_prepare_enable(adc->clki);
  238. if (ret < 0) {
  239. dev_err(&adc->spi->dev,
  240. "Failed to enable clki: %d\n", ret);
  241. goto reg_disable;
  242. }
  243. }
  244. ret = mcp3911_config(adc, spi->dev.of_node);
  245. if (ret)
  246. goto clk_disable;
  247. indio_dev->name = spi_get_device_id(spi)->name;
  248. indio_dev->modes = INDIO_DIRECT_MODE;
  249. indio_dev->info = &mcp3911_info;
  250. spi_set_drvdata(spi, indio_dev);
  251. indio_dev->channels = mcp3911_channels;
  252. indio_dev->num_channels = ARRAY_SIZE(mcp3911_channels);
  253. mutex_init(&adc->lock);
  254. ret = iio_device_register(indio_dev);
  255. if (ret)
  256. goto clk_disable;
  257. return ret;
  258. clk_disable:
  259. clk_disable_unprepare(adc->clki);
  260. reg_disable:
  261. if (adc->vref)
  262. regulator_disable(adc->vref);
  263. return ret;
  264. }
  265. static int mcp3911_remove(struct spi_device *spi)
  266. {
  267. struct iio_dev *indio_dev = spi_get_drvdata(spi);
  268. struct mcp3911 *adc = iio_priv(indio_dev);
  269. iio_device_unregister(indio_dev);
  270. clk_disable_unprepare(adc->clki);
  271. if (adc->vref)
  272. regulator_disable(adc->vref);
  273. return 0;
  274. }
  275. static const struct of_device_id mcp3911_dt_ids[] = {
  276. { .compatible = "microchip,mcp3911" },
  277. { }
  278. };
  279. MODULE_DEVICE_TABLE(of, mcp3911_dt_ids);
  280. static const struct spi_device_id mcp3911_id[] = {
  281. { "mcp3911", 0 },
  282. { }
  283. };
  284. MODULE_DEVICE_TABLE(spi, mcp3911_id);
  285. static struct spi_driver mcp3911_driver = {
  286. .driver = {
  287. .name = "mcp3911",
  288. .of_match_table = mcp3911_dt_ids,
  289. },
  290. .probe = mcp3911_probe,
  291. .remove = mcp3911_remove,
  292. .id_table = mcp3911_id,
  293. };
  294. module_spi_driver(mcp3911_driver);
  295. MODULE_AUTHOR("Marcus Folkesson <marcus.folkesson@gmail.com>");
  296. MODULE_AUTHOR("Kent Gustavsson <kent@minoris.se>");
  297. MODULE_DESCRIPTION("Microchip Technology MCP3911");
  298. MODULE_LICENSE("GPL v2");