max1363.c 49 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * iio/adc/max1363.c
  4. * Copyright (C) 2008-2010 Jonathan Cameron
  5. *
  6. * based on linux/drivers/i2c/chips/max123x
  7. * Copyright (C) 2002-2004 Stefan Eletzhofer
  8. *
  9. * based on linux/drivers/acron/char/pcf8583.c
  10. * Copyright (C) 2000 Russell King
  11. *
  12. * Driver for max1363 and similar chips.
  13. */
  14. #include <linux/interrupt.h>
  15. #include <linux/device.h>
  16. #include <linux/kernel.h>
  17. #include <linux/sysfs.h>
  18. #include <linux/list.h>
  19. #include <linux/i2c.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <linux/slab.h>
  22. #include <linux/err.h>
  23. #include <linux/module.h>
  24. #include <linux/mod_devicetable.h>
  25. #include <linux/property.h>
  26. #include <linux/iio/iio.h>
  27. #include <linux/iio/sysfs.h>
  28. #include <linux/iio/events.h>
  29. #include <linux/iio/buffer.h>
  30. #include <linux/iio/driver.h>
  31. #include <linux/iio/kfifo_buf.h>
  32. #include <linux/iio/trigger_consumer.h>
  33. #include <linux/iio/triggered_buffer.h>
  34. #define MAX1363_SETUP_BYTE(a) ((a) | 0x80)
  35. /* There is a fair bit more defined here than currently
  36. * used, but the intention is to support everything these
  37. * chips do in the long run */
  38. /* see data sheets */
  39. /* max1363 and max1236, max1237, max1238, max1239 */
  40. #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00
  41. #define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20
  42. #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40
  43. #define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60
  44. #define MAX1363_SETUP_POWER_UP_INT_REF 0x10
  45. #define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00
  46. /* think about including max11600 etc - more settings */
  47. #define MAX1363_SETUP_EXT_CLOCK 0x08
  48. #define MAX1363_SETUP_INT_CLOCK 0x00
  49. #define MAX1363_SETUP_UNIPOLAR 0x00
  50. #define MAX1363_SETUP_BIPOLAR 0x04
  51. #define MAX1363_SETUP_RESET 0x00
  52. #define MAX1363_SETUP_NORESET 0x02
  53. /* max1363 only - though don't care on others.
  54. * For now monitor modes are not implemented as the relevant
  55. * line is not connected on my test board.
  56. * The definitions are here as I intend to add this soon.
  57. */
  58. #define MAX1363_SETUP_MONITOR_SETUP 0x01
  59. /* Specific to the max1363 */
  60. #define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4))
  61. #define MAX1363_MON_INT_ENABLE 0x01
  62. /* defined for readability reasons */
  63. /* All chips */
  64. #define MAX1363_CONFIG_BYTE(a) ((a))
  65. #define MAX1363_CONFIG_SE 0x01
  66. #define MAX1363_CONFIG_DE 0x00
  67. #define MAX1363_CONFIG_SCAN_TO_CS 0x00
  68. #define MAX1363_CONFIG_SCAN_SINGLE_8 0x20
  69. #define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40
  70. #define MAX1363_CONFIG_SCAN_SINGLE_1 0x60
  71. /* max123{6-9} only */
  72. #define MAX1236_SCAN_MID_TO_CHANNEL 0x40
  73. /* max1363 only - merely part of channel selects or don't care for others */
  74. #define MAX1363_CONFIG_EN_MON_MODE_READ 0x18
  75. #define MAX1363_CHANNEL_SEL(a) ((a) << 1)
  76. /* max1363 strictly 0x06 - but doesn't matter */
  77. #define MAX1363_CHANNEL_SEL_MASK 0x1E
  78. #define MAX1363_SCAN_MASK 0x60
  79. #define MAX1363_SE_DE_MASK 0x01
  80. #define MAX1363_MAX_CHANNELS 25
  81. /**
  82. * struct max1363_mode - scan mode information
  83. * @conf: The corresponding value of the configuration register
  84. * @modemask: Bit mask corresponding to channels enabled in this mode
  85. */
  86. struct max1363_mode {
  87. int8_t conf;
  88. DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS);
  89. };
  90. /* This must be maintained along side the max1363_mode_table in max1363_core */
  91. enum max1363_modes {
  92. /* Single read of a single channel */
  93. _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
  94. /* Differential single read */
  95. d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
  96. d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
  97. /* Scan to channel and mid to channel where overlapping */
  98. s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6,
  99. s6to7, s0to7, s6to8, s0to8, s6to9,
  100. s0to9, s6to10, s0to10, s6to11, s0to11,
  101. /* Differential scan to channel and mid to channel where overlapping */
  102. d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
  103. d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
  104. d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
  105. d7m6to11m10, d1m0to11m10,
  106. };
  107. /**
  108. * struct max1363_chip_info - chip specifc information
  109. * @info: iio core function callbacks structure
  110. * @channels: channel specification
  111. * @num_channels: number of channels
  112. * @mode_list: array of available scan modes
  113. * @default_mode: the scan mode in which the chip starts up
  114. * @int_vref_mv: the internal reference voltage
  115. * @num_modes: number of modes
  116. * @bits: accuracy of the adc in bits
  117. */
  118. struct max1363_chip_info {
  119. const struct iio_info *info;
  120. const struct iio_chan_spec *channels;
  121. int num_channels;
  122. const enum max1363_modes *mode_list;
  123. enum max1363_modes default_mode;
  124. u16 int_vref_mv;
  125. u8 num_modes;
  126. u8 bits;
  127. };
  128. /**
  129. * struct max1363_state - driver instance specific data
  130. * @client: i2c_client
  131. * @setupbyte: cache of current device setup byte
  132. * @configbyte: cache of current device config byte
  133. * @chip_info: chip model specific constants, available modes, etc.
  134. * @current_mode: the scan mode of this chip
  135. * @requestedmask: a valid requested set of channels
  136. * @reg: supply regulator
  137. * @lock: lock to ensure state is consistent
  138. * @monitor_on: whether monitor mode is enabled
  139. * @monitor_speed: parameter corresponding to device monitor speed setting
  140. * @mask_high: bitmask for enabled high thresholds
  141. * @mask_low: bitmask for enabled low thresholds
  142. * @thresh_high: high threshold values
  143. * @thresh_low: low threshold values
  144. * @vref: Reference voltage regulator
  145. * @vref_uv: Actual (external or internal) reference voltage
  146. * @send: function used to send data to the chip
  147. * @recv: function used to receive data from the chip
  148. */
  149. struct max1363_state {
  150. struct i2c_client *client;
  151. u8 setupbyte;
  152. u8 configbyte;
  153. const struct max1363_chip_info *chip_info;
  154. const struct max1363_mode *current_mode;
  155. u32 requestedmask;
  156. struct regulator *reg;
  157. struct mutex lock;
  158. /* Using monitor modes and buffer at the same time is
  159. currently not supported */
  160. bool monitor_on;
  161. unsigned int monitor_speed:3;
  162. u8 mask_high;
  163. u8 mask_low;
  164. /* 4x unipolar first then the fours bipolar ones */
  165. s16 thresh_high[8];
  166. s16 thresh_low[8];
  167. struct regulator *vref;
  168. u32 vref_uv;
  169. int (*send)(const struct i2c_client *client,
  170. const char *buf, int count);
  171. int (*recv)(const struct i2c_client *client,
  172. char *buf, int count);
  173. };
  174. #define MAX1363_MODE_SINGLE(_num, _mask) { \
  175. .conf = MAX1363_CHANNEL_SEL(_num) \
  176. | MAX1363_CONFIG_SCAN_SINGLE_1 \
  177. | MAX1363_CONFIG_SE, \
  178. .modemask[0] = _mask, \
  179. }
  180. #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
  181. .conf = MAX1363_CHANNEL_SEL(_num) \
  182. | MAX1363_CONFIG_SCAN_TO_CS \
  183. | MAX1363_CONFIG_SE, \
  184. .modemask[0] = _mask, \
  185. }
  186. /* note not available for max1363 hence naming */
  187. #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
  188. .conf = MAX1363_CHANNEL_SEL(_num) \
  189. | MAX1236_SCAN_MID_TO_CHANNEL \
  190. | MAX1363_CONFIG_SE, \
  191. .modemask[0] = _mask \
  192. }
  193. #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
  194. .conf = MAX1363_CHANNEL_SEL(_nump) \
  195. | MAX1363_CONFIG_SCAN_SINGLE_1 \
  196. | MAX1363_CONFIG_DE, \
  197. .modemask[0] = _mask \
  198. }
  199. /* Can't think how to automate naming so specify for now */
  200. #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
  201. .conf = MAX1363_CHANNEL_SEL(_num) \
  202. | MAX1363_CONFIG_SCAN_TO_CS \
  203. | MAX1363_CONFIG_DE, \
  204. .modemask[0] = _mask \
  205. }
  206. /* note only available for max1363 hence naming */
  207. #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
  208. .conf = MAX1363_CHANNEL_SEL(_num) \
  209. | MAX1236_SCAN_MID_TO_CHANNEL \
  210. | MAX1363_CONFIG_SE, \
  211. .modemask[0] = _mask \
  212. }
  213. static const struct max1363_mode max1363_mode_table[] = {
  214. /* All of the single channel options first */
  215. MAX1363_MODE_SINGLE(0, 1 << 0),
  216. MAX1363_MODE_SINGLE(1, 1 << 1),
  217. MAX1363_MODE_SINGLE(2, 1 << 2),
  218. MAX1363_MODE_SINGLE(3, 1 << 3),
  219. MAX1363_MODE_SINGLE(4, 1 << 4),
  220. MAX1363_MODE_SINGLE(5, 1 << 5),
  221. MAX1363_MODE_SINGLE(6, 1 << 6),
  222. MAX1363_MODE_SINGLE(7, 1 << 7),
  223. MAX1363_MODE_SINGLE(8, 1 << 8),
  224. MAX1363_MODE_SINGLE(9, 1 << 9),
  225. MAX1363_MODE_SINGLE(10, 1 << 10),
  226. MAX1363_MODE_SINGLE(11, 1 << 11),
  227. MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
  228. MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
  229. MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
  230. MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
  231. MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
  232. MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
  233. MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
  234. MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
  235. MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
  236. MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
  237. MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
  238. MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
  239. /* The multichannel scans next */
  240. MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
  241. MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
  242. MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
  243. MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
  244. MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
  245. MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
  246. MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
  247. MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
  248. MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
  249. MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
  250. MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
  251. MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
  252. MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
  253. MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
  254. MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
  255. MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
  256. MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
  257. MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
  258. MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
  259. MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
  260. MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
  261. MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
  262. MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
  263. MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
  264. MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
  265. MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
  266. MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
  267. MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
  268. MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
  269. MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
  270. MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
  271. };
  272. static const struct max1363_mode
  273. *max1363_match_mode(const unsigned long *mask,
  274. const struct max1363_chip_info *ci)
  275. {
  276. int i;
  277. if (mask)
  278. for (i = 0; i < ci->num_modes; i++)
  279. if (bitmap_subset(mask,
  280. max1363_mode_table[ci->mode_list[i]].
  281. modemask,
  282. MAX1363_MAX_CHANNELS))
  283. return &max1363_mode_table[ci->mode_list[i]];
  284. return NULL;
  285. }
  286. static int max1363_smbus_send(const struct i2c_client *client, const char *buf,
  287. int count)
  288. {
  289. int i, err;
  290. for (i = err = 0; err == 0 && i < count; ++i)
  291. err = i2c_smbus_write_byte(client, buf[i]);
  292. return err ? err : count;
  293. }
  294. static int max1363_smbus_recv(const struct i2c_client *client, char *buf,
  295. int count)
  296. {
  297. int i, ret;
  298. for (i = 0; i < count; ++i) {
  299. ret = i2c_smbus_read_byte(client);
  300. if (ret < 0)
  301. return ret;
  302. buf[i] = ret;
  303. }
  304. return count;
  305. }
  306. static int max1363_write_basic_config(struct max1363_state *st)
  307. {
  308. u8 tx_buf[2] = { st->setupbyte, st->configbyte };
  309. return st->send(st->client, tx_buf, 2);
  310. }
  311. static int max1363_set_scan_mode(struct max1363_state *st)
  312. {
  313. st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
  314. | MAX1363_SCAN_MASK
  315. | MAX1363_SE_DE_MASK);
  316. st->configbyte |= st->current_mode->conf;
  317. return max1363_write_basic_config(st);
  318. }
  319. static int max1363_read_single_chan(struct iio_dev *indio_dev,
  320. struct iio_chan_spec const *chan,
  321. int *val,
  322. long m)
  323. {
  324. int ret = 0;
  325. s32 data;
  326. u8 rxbuf[2];
  327. struct max1363_state *st = iio_priv(indio_dev);
  328. struct i2c_client *client = st->client;
  329. ret = iio_device_claim_direct_mode(indio_dev);
  330. if (ret)
  331. return ret;
  332. mutex_lock(&st->lock);
  333. /*
  334. * If monitor mode is enabled, the method for reading a single
  335. * channel will have to be rather different and has not yet
  336. * been implemented.
  337. *
  338. * Also, cannot read directly if buffered capture enabled.
  339. */
  340. if (st->monitor_on) {
  341. ret = -EBUSY;
  342. goto error_ret;
  343. }
  344. /* Check to see if current scan mode is correct */
  345. if (st->current_mode != &max1363_mode_table[chan->address]) {
  346. /* Update scan mode if needed */
  347. st->current_mode = &max1363_mode_table[chan->address];
  348. ret = max1363_set_scan_mode(st);
  349. if (ret < 0)
  350. goto error_ret;
  351. }
  352. if (st->chip_info->bits != 8) {
  353. /* Get reading */
  354. data = st->recv(client, rxbuf, 2);
  355. if (data < 0) {
  356. ret = data;
  357. goto error_ret;
  358. }
  359. data = (rxbuf[1] | rxbuf[0] << 8) &
  360. ((1 << st->chip_info->bits) - 1);
  361. } else {
  362. /* Get reading */
  363. data = st->recv(client, rxbuf, 1);
  364. if (data < 0) {
  365. ret = data;
  366. goto error_ret;
  367. }
  368. data = rxbuf[0];
  369. }
  370. *val = data;
  371. error_ret:
  372. mutex_unlock(&st->lock);
  373. iio_device_release_direct_mode(indio_dev);
  374. return ret;
  375. }
  376. static int max1363_read_raw(struct iio_dev *indio_dev,
  377. struct iio_chan_spec const *chan,
  378. int *val,
  379. int *val2,
  380. long m)
  381. {
  382. struct max1363_state *st = iio_priv(indio_dev);
  383. int ret;
  384. switch (m) {
  385. case IIO_CHAN_INFO_RAW:
  386. ret = max1363_read_single_chan(indio_dev, chan, val, m);
  387. if (ret < 0)
  388. return ret;
  389. return IIO_VAL_INT;
  390. case IIO_CHAN_INFO_SCALE:
  391. *val = st->vref_uv / 1000;
  392. *val2 = st->chip_info->bits;
  393. return IIO_VAL_FRACTIONAL_LOG2;
  394. default:
  395. return -EINVAL;
  396. }
  397. return 0;
  398. }
  399. /* Applies to max1363 */
  400. static const enum max1363_modes max1363_mode_list[] = {
  401. _s0, _s1, _s2, _s3,
  402. s0to1, s0to2, s0to3,
  403. d0m1, d2m3, d1m0, d3m2,
  404. d0m1to2m3, d1m0to3m2,
  405. };
  406. static const struct iio_event_spec max1363_events[] = {
  407. {
  408. .type = IIO_EV_TYPE_THRESH,
  409. .dir = IIO_EV_DIR_RISING,
  410. .mask_separate = BIT(IIO_EV_INFO_VALUE) |
  411. BIT(IIO_EV_INFO_ENABLE),
  412. }, {
  413. .type = IIO_EV_TYPE_THRESH,
  414. .dir = IIO_EV_DIR_FALLING,
  415. .mask_separate = BIT(IIO_EV_INFO_VALUE) |
  416. BIT(IIO_EV_INFO_ENABLE),
  417. },
  418. };
  419. #define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec) \
  420. { \
  421. .type = IIO_VOLTAGE, \
  422. .indexed = 1, \
  423. .channel = num, \
  424. .address = addr, \
  425. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  426. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  427. .datasheet_name = "AIN"#num, \
  428. .scan_type = { \
  429. .sign = 'u', \
  430. .realbits = bits, \
  431. .storagebits = (bits > 8) ? 16 : 8, \
  432. .endianness = IIO_BE, \
  433. }, \
  434. .scan_index = si, \
  435. .event_spec = ev_spec, \
  436. .num_event_specs = num_ev_spec, \
  437. }
  438. /* bipolar channel */
  439. #define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \
  440. { \
  441. .type = IIO_VOLTAGE, \
  442. .differential = 1, \
  443. .indexed = 1, \
  444. .channel = num, \
  445. .channel2 = num2, \
  446. .address = addr, \
  447. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  448. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  449. .datasheet_name = "AIN"#num"-AIN"#num2, \
  450. .scan_type = { \
  451. .sign = 's', \
  452. .realbits = bits, \
  453. .storagebits = (bits > 8) ? 16 : 8, \
  454. .endianness = IIO_BE, \
  455. }, \
  456. .scan_index = si, \
  457. .event_spec = ev_spec, \
  458. .num_event_specs = num_ev_spec, \
  459. }
  460. #define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) { \
  461. MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec), \
  462. MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec), \
  463. MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec), \
  464. MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec), \
  465. MAX1363_CHAN_B(0, 1, d0m1, 4, bits, ev_spec, num_ev_spec), \
  466. MAX1363_CHAN_B(2, 3, d2m3, 5, bits, ev_spec, num_ev_spec), \
  467. MAX1363_CHAN_B(1, 0, d1m0, 6, bits, ev_spec, num_ev_spec), \
  468. MAX1363_CHAN_B(3, 2, d3m2, 7, bits, ev_spec, num_ev_spec), \
  469. IIO_CHAN_SOFT_TIMESTAMP(8) \
  470. }
  471. static const struct iio_chan_spec max1036_channels[] =
  472. MAX1363_4X_CHANS(8, NULL, 0);
  473. static const struct iio_chan_spec max1136_channels[] =
  474. MAX1363_4X_CHANS(10, NULL, 0);
  475. static const struct iio_chan_spec max1236_channels[] =
  476. MAX1363_4X_CHANS(12, NULL, 0);
  477. static const struct iio_chan_spec max1361_channels[] =
  478. MAX1363_4X_CHANS(10, max1363_events, ARRAY_SIZE(max1363_events));
  479. static const struct iio_chan_spec max1363_channels[] =
  480. MAX1363_4X_CHANS(12, max1363_events, ARRAY_SIZE(max1363_events));
  481. /* Applies to max1236, max1237 */
  482. static const enum max1363_modes max1236_mode_list[] = {
  483. _s0, _s1, _s2, _s3,
  484. s0to1, s0to2, s0to3,
  485. d0m1, d2m3, d1m0, d3m2,
  486. d0m1to2m3, d1m0to3m2,
  487. s2to3,
  488. };
  489. /* Applies to max1238, max1239 */
  490. static const enum max1363_modes max1238_mode_list[] = {
  491. _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
  492. s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
  493. s0to7, s0to8, s0to9, s0to10, s0to11,
  494. d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
  495. d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
  496. d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
  497. d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
  498. s6to7, s6to8, s6to9, s6to10, s6to11,
  499. d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
  500. };
  501. #define MAX1363_12X_CHANS(bits) { \
  502. MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
  503. MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
  504. MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
  505. MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
  506. MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
  507. MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
  508. MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
  509. MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
  510. MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0), \
  511. MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0), \
  512. MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0), \
  513. MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0), \
  514. MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \
  515. MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \
  516. MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \
  517. MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \
  518. MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0), \
  519. MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0), \
  520. MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \
  521. MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \
  522. MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \
  523. MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \
  524. MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0), \
  525. MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0), \
  526. IIO_CHAN_SOFT_TIMESTAMP(24) \
  527. }
  528. static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
  529. static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
  530. static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
  531. static const enum max1363_modes max11607_mode_list[] = {
  532. _s0, _s1, _s2, _s3,
  533. s0to1, s0to2, s0to3,
  534. s2to3,
  535. d0m1, d2m3, d1m0, d3m2,
  536. d0m1to2m3, d1m0to3m2,
  537. };
  538. static const enum max1363_modes max11608_mode_list[] = {
  539. _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
  540. s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
  541. s6to7,
  542. d0m1, d2m3, d4m5, d6m7,
  543. d1m0, d3m2, d5m4, d7m6,
  544. d0m1to2m3, d0m1to4m5, d0m1to6m7,
  545. d1m0to3m2, d1m0to5m4, d1m0to7m6,
  546. };
  547. #define MAX1363_8X_CHANS(bits) { \
  548. MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
  549. MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
  550. MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
  551. MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
  552. MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
  553. MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
  554. MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
  555. MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
  556. MAX1363_CHAN_B(0, 1, d0m1, 8, bits, NULL, 0), \
  557. MAX1363_CHAN_B(2, 3, d2m3, 9, bits, NULL, 0), \
  558. MAX1363_CHAN_B(4, 5, d4m5, 10, bits, NULL, 0), \
  559. MAX1363_CHAN_B(6, 7, d6m7, 11, bits, NULL, 0), \
  560. MAX1363_CHAN_B(1, 0, d1m0, 12, bits, NULL, 0), \
  561. MAX1363_CHAN_B(3, 2, d3m2, 13, bits, NULL, 0), \
  562. MAX1363_CHAN_B(5, 4, d5m4, 14, bits, NULL, 0), \
  563. MAX1363_CHAN_B(7, 6, d7m6, 15, bits, NULL, 0), \
  564. IIO_CHAN_SOFT_TIMESTAMP(16) \
  565. }
  566. static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
  567. static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
  568. static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
  569. static const enum max1363_modes max11644_mode_list[] = {
  570. _s0, _s1, s0to1, d0m1, d1m0,
  571. };
  572. #define MAX1363_2X_CHANS(bits) { \
  573. MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
  574. MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
  575. MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0), \
  576. MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0), \
  577. IIO_CHAN_SOFT_TIMESTAMP(4) \
  578. }
  579. static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
  580. static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
  581. enum { max1361,
  582. max1362,
  583. max1363,
  584. max1364,
  585. max1036,
  586. max1037,
  587. max1038,
  588. max1039,
  589. max1136,
  590. max1137,
  591. max1138,
  592. max1139,
  593. max1236,
  594. max1237,
  595. max1238,
  596. max1239,
  597. max11600,
  598. max11601,
  599. max11602,
  600. max11603,
  601. max11604,
  602. max11605,
  603. max11606,
  604. max11607,
  605. max11608,
  606. max11609,
  607. max11610,
  608. max11611,
  609. max11612,
  610. max11613,
  611. max11614,
  612. max11615,
  613. max11616,
  614. max11617,
  615. max11644,
  616. max11645,
  617. max11646,
  618. max11647
  619. };
  620. static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
  621. 8300, 4200, 2000, 1000 };
  622. static ssize_t max1363_monitor_show_freq(struct device *dev,
  623. struct device_attribute *attr,
  624. char *buf)
  625. {
  626. struct max1363_state *st = iio_priv(dev_to_iio_dev(dev));
  627. return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
  628. }
  629. static ssize_t max1363_monitor_store_freq(struct device *dev,
  630. struct device_attribute *attr,
  631. const char *buf,
  632. size_t len)
  633. {
  634. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  635. struct max1363_state *st = iio_priv(indio_dev);
  636. int i, ret;
  637. unsigned long val;
  638. bool found = false;
  639. ret = kstrtoul(buf, 10, &val);
  640. if (ret)
  641. return -EINVAL;
  642. for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
  643. if (val == max1363_monitor_speeds[i]) {
  644. found = true;
  645. break;
  646. }
  647. if (!found)
  648. return -EINVAL;
  649. mutex_lock(&st->lock);
  650. st->monitor_speed = i;
  651. mutex_unlock(&st->lock);
  652. return 0;
  653. }
  654. static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
  655. max1363_monitor_show_freq,
  656. max1363_monitor_store_freq);
  657. static IIO_CONST_ATTR(sampling_frequency_available,
  658. "133000 665000 33300 16600 8300 4200 2000 1000");
  659. static int max1363_read_thresh(struct iio_dev *indio_dev,
  660. const struct iio_chan_spec *chan, enum iio_event_type type,
  661. enum iio_event_direction dir, enum iio_event_info info, int *val,
  662. int *val2)
  663. {
  664. struct max1363_state *st = iio_priv(indio_dev);
  665. if (dir == IIO_EV_DIR_FALLING)
  666. *val = st->thresh_low[chan->channel];
  667. else
  668. *val = st->thresh_high[chan->channel];
  669. return IIO_VAL_INT;
  670. }
  671. static int max1363_write_thresh(struct iio_dev *indio_dev,
  672. const struct iio_chan_spec *chan, enum iio_event_type type,
  673. enum iio_event_direction dir, enum iio_event_info info, int val,
  674. int val2)
  675. {
  676. struct max1363_state *st = iio_priv(indio_dev);
  677. /* make it handle signed correctly as well */
  678. switch (st->chip_info->bits) {
  679. case 10:
  680. if (val > 0x3FF)
  681. return -EINVAL;
  682. break;
  683. case 12:
  684. if (val > 0xFFF)
  685. return -EINVAL;
  686. break;
  687. }
  688. switch (dir) {
  689. case IIO_EV_DIR_FALLING:
  690. st->thresh_low[chan->channel] = val;
  691. break;
  692. case IIO_EV_DIR_RISING:
  693. st->thresh_high[chan->channel] = val;
  694. break;
  695. default:
  696. return -EINVAL;
  697. }
  698. return 0;
  699. }
  700. static const u64 max1363_event_codes[] = {
  701. IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
  702. IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
  703. IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
  704. IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
  705. IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
  706. IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
  707. IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
  708. IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
  709. IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
  710. IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
  711. IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
  712. IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
  713. IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
  714. IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
  715. IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
  716. IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
  717. };
  718. static irqreturn_t max1363_event_handler(int irq, void *private)
  719. {
  720. struct iio_dev *indio_dev = private;
  721. struct max1363_state *st = iio_priv(indio_dev);
  722. s64 timestamp = iio_get_time_ns(indio_dev);
  723. unsigned long mask, loc;
  724. u8 rx;
  725. u8 tx[2] = { st->setupbyte,
  726. MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
  727. st->recv(st->client, &rx, 1);
  728. mask = rx;
  729. for_each_set_bit(loc, &mask, 8)
  730. iio_push_event(indio_dev, max1363_event_codes[loc], timestamp);
  731. st->send(st->client, tx, 2);
  732. return IRQ_HANDLED;
  733. }
  734. static int max1363_read_event_config(struct iio_dev *indio_dev,
  735. const struct iio_chan_spec *chan, enum iio_event_type type,
  736. enum iio_event_direction dir)
  737. {
  738. struct max1363_state *st = iio_priv(indio_dev);
  739. int val;
  740. int number = chan->channel;
  741. mutex_lock(&st->lock);
  742. if (dir == IIO_EV_DIR_FALLING)
  743. val = (1 << number) & st->mask_low;
  744. else
  745. val = (1 << number) & st->mask_high;
  746. mutex_unlock(&st->lock);
  747. return val;
  748. }
  749. static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
  750. {
  751. u8 *tx_buf;
  752. int ret, i = 3, j;
  753. unsigned long numelements;
  754. int len;
  755. const long *modemask;
  756. if (!enabled) {
  757. /* transition to buffered capture is not currently supported */
  758. st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
  759. st->configbyte &= ~MAX1363_SCAN_MASK;
  760. st->monitor_on = false;
  761. return max1363_write_basic_config(st);
  762. }
  763. /* Ensure we are in the relevant mode */
  764. st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
  765. st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
  766. | MAX1363_SCAN_MASK
  767. | MAX1363_SE_DE_MASK);
  768. st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
  769. if ((st->mask_low | st->mask_high) & 0x0F) {
  770. st->configbyte |= max1363_mode_table[s0to3].conf;
  771. modemask = max1363_mode_table[s0to3].modemask;
  772. } else if ((st->mask_low | st->mask_high) & 0x30) {
  773. st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
  774. modemask = max1363_mode_table[d0m1to2m3].modemask;
  775. } else {
  776. st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
  777. modemask = max1363_mode_table[d1m0to3m2].modemask;
  778. }
  779. numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS);
  780. len = 3 * numelements + 3;
  781. tx_buf = kmalloc(len, GFP_KERNEL);
  782. if (!tx_buf) {
  783. ret = -ENOMEM;
  784. goto error_ret;
  785. }
  786. tx_buf[0] = st->configbyte;
  787. tx_buf[1] = st->setupbyte;
  788. tx_buf[2] = (st->monitor_speed << 1);
  789. /*
  790. * So we need to do yet another bit of nefarious scan mode
  791. * setup to match what we need.
  792. */
  793. for (j = 0; j < 8; j++)
  794. if (test_bit(j, modemask)) {
  795. /* Establish the mode is in the scan */
  796. if (st->mask_low & (1 << j)) {
  797. tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
  798. tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
  799. } else if (j < 4) {
  800. tx_buf[i] = 0;
  801. tx_buf[i + 1] = 0;
  802. } else {
  803. tx_buf[i] = 0x80;
  804. tx_buf[i + 1] = 0;
  805. }
  806. if (st->mask_high & (1 << j)) {
  807. tx_buf[i + 1] |=
  808. (st->thresh_high[j] >> 8) & 0x0F;
  809. tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
  810. } else if (j < 4) {
  811. tx_buf[i + 1] |= 0x0F;
  812. tx_buf[i + 2] = 0xFF;
  813. } else {
  814. tx_buf[i + 1] |= 0x07;
  815. tx_buf[i + 2] = 0xFF;
  816. }
  817. i += 3;
  818. }
  819. ret = st->send(st->client, tx_buf, len);
  820. if (ret < 0)
  821. goto error_ret;
  822. if (ret != len) {
  823. ret = -EIO;
  824. goto error_ret;
  825. }
  826. /*
  827. * Now that we hopefully have sensible thresholds in place it is
  828. * time to turn the interrupts on.
  829. * It is unclear from the data sheet if this should be necessary
  830. * (i.e. whether monitor mode setup is atomic) but it appears to
  831. * be in practice.
  832. */
  833. tx_buf[0] = st->setupbyte;
  834. tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
  835. ret = st->send(st->client, tx_buf, 2);
  836. if (ret < 0)
  837. goto error_ret;
  838. if (ret != 2) {
  839. ret = -EIO;
  840. goto error_ret;
  841. }
  842. ret = 0;
  843. st->monitor_on = true;
  844. error_ret:
  845. kfree(tx_buf);
  846. return ret;
  847. }
  848. /*
  849. * To keep this manageable we always use one of 3 scan modes.
  850. * Scan 0...3, 0-1,2-3 and 1-0,3-2
  851. */
  852. static inline int __max1363_check_event_mask(int thismask, int checkmask)
  853. {
  854. int ret = 0;
  855. /* Is it unipolar */
  856. if (thismask < 4) {
  857. if (checkmask & ~0x0F) {
  858. ret = -EBUSY;
  859. goto error_ret;
  860. }
  861. } else if (thismask < 6) {
  862. if (checkmask & ~0x30) {
  863. ret = -EBUSY;
  864. goto error_ret;
  865. }
  866. } else if (checkmask & ~0xC0)
  867. ret = -EBUSY;
  868. error_ret:
  869. return ret;
  870. }
  871. static int max1363_write_event_config(struct iio_dev *indio_dev,
  872. const struct iio_chan_spec *chan, enum iio_event_type type,
  873. enum iio_event_direction dir, int state)
  874. {
  875. int ret = 0;
  876. struct max1363_state *st = iio_priv(indio_dev);
  877. u16 unifiedmask;
  878. int number = chan->channel;
  879. ret = iio_device_claim_direct_mode(indio_dev);
  880. if (ret)
  881. return ret;
  882. mutex_lock(&st->lock);
  883. unifiedmask = st->mask_low | st->mask_high;
  884. if (dir == IIO_EV_DIR_FALLING) {
  885. if (state == 0)
  886. st->mask_low &= ~(1 << number);
  887. else {
  888. ret = __max1363_check_event_mask((1 << number),
  889. unifiedmask);
  890. if (ret)
  891. goto error_ret;
  892. st->mask_low |= (1 << number);
  893. }
  894. } else {
  895. if (state == 0)
  896. st->mask_high &= ~(1 << number);
  897. else {
  898. ret = __max1363_check_event_mask((1 << number),
  899. unifiedmask);
  900. if (ret)
  901. goto error_ret;
  902. st->mask_high |= (1 << number);
  903. }
  904. }
  905. max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
  906. error_ret:
  907. mutex_unlock(&st->lock);
  908. iio_device_release_direct_mode(indio_dev);
  909. return ret;
  910. }
  911. /*
  912. * As with scan_elements, only certain sets of these can
  913. * be combined.
  914. */
  915. static struct attribute *max1363_event_attributes[] = {
  916. &iio_dev_attr_sampling_frequency.dev_attr.attr,
  917. &iio_const_attr_sampling_frequency_available.dev_attr.attr,
  918. NULL,
  919. };
  920. static const struct attribute_group max1363_event_attribute_group = {
  921. .attrs = max1363_event_attributes,
  922. };
  923. static int max1363_update_scan_mode(struct iio_dev *indio_dev,
  924. const unsigned long *scan_mask)
  925. {
  926. struct max1363_state *st = iio_priv(indio_dev);
  927. /*
  928. * Need to figure out the current mode based upon the requested
  929. * scan mask in iio_dev
  930. */
  931. st->current_mode = max1363_match_mode(scan_mask, st->chip_info);
  932. if (!st->current_mode)
  933. return -EINVAL;
  934. max1363_set_scan_mode(st);
  935. return 0;
  936. }
  937. static const struct iio_info max1238_info = {
  938. .read_raw = &max1363_read_raw,
  939. .update_scan_mode = &max1363_update_scan_mode,
  940. };
  941. static const struct iio_info max1363_info = {
  942. .read_event_value = &max1363_read_thresh,
  943. .write_event_value = &max1363_write_thresh,
  944. .read_event_config = &max1363_read_event_config,
  945. .write_event_config = &max1363_write_event_config,
  946. .read_raw = &max1363_read_raw,
  947. .update_scan_mode = &max1363_update_scan_mode,
  948. .event_attrs = &max1363_event_attribute_group,
  949. };
  950. /* max1363 and max1368 tested - rest from data sheet */
  951. static const struct max1363_chip_info max1363_chip_info_tbl[] = {
  952. [max1361] = {
  953. .bits = 10,
  954. .int_vref_mv = 2048,
  955. .mode_list = max1363_mode_list,
  956. .num_modes = ARRAY_SIZE(max1363_mode_list),
  957. .default_mode = s0to3,
  958. .channels = max1361_channels,
  959. .num_channels = ARRAY_SIZE(max1361_channels),
  960. .info = &max1363_info,
  961. },
  962. [max1362] = {
  963. .bits = 10,
  964. .int_vref_mv = 4096,
  965. .mode_list = max1363_mode_list,
  966. .num_modes = ARRAY_SIZE(max1363_mode_list),
  967. .default_mode = s0to3,
  968. .channels = max1361_channels,
  969. .num_channels = ARRAY_SIZE(max1361_channels),
  970. .info = &max1363_info,
  971. },
  972. [max1363] = {
  973. .bits = 12,
  974. .int_vref_mv = 2048,
  975. .mode_list = max1363_mode_list,
  976. .num_modes = ARRAY_SIZE(max1363_mode_list),
  977. .default_mode = s0to3,
  978. .channels = max1363_channels,
  979. .num_channels = ARRAY_SIZE(max1363_channels),
  980. .info = &max1363_info,
  981. },
  982. [max1364] = {
  983. .bits = 12,
  984. .int_vref_mv = 4096,
  985. .mode_list = max1363_mode_list,
  986. .num_modes = ARRAY_SIZE(max1363_mode_list),
  987. .default_mode = s0to3,
  988. .channels = max1363_channels,
  989. .num_channels = ARRAY_SIZE(max1363_channels),
  990. .info = &max1363_info,
  991. },
  992. [max1036] = {
  993. .bits = 8,
  994. .int_vref_mv = 4096,
  995. .mode_list = max1236_mode_list,
  996. .num_modes = ARRAY_SIZE(max1236_mode_list),
  997. .default_mode = s0to3,
  998. .info = &max1238_info,
  999. .channels = max1036_channels,
  1000. .num_channels = ARRAY_SIZE(max1036_channels),
  1001. },
  1002. [max1037] = {
  1003. .bits = 8,
  1004. .int_vref_mv = 2048,
  1005. .mode_list = max1236_mode_list,
  1006. .num_modes = ARRAY_SIZE(max1236_mode_list),
  1007. .default_mode = s0to3,
  1008. .info = &max1238_info,
  1009. .channels = max1036_channels,
  1010. .num_channels = ARRAY_SIZE(max1036_channels),
  1011. },
  1012. [max1038] = {
  1013. .bits = 8,
  1014. .int_vref_mv = 4096,
  1015. .mode_list = max1238_mode_list,
  1016. .num_modes = ARRAY_SIZE(max1238_mode_list),
  1017. .default_mode = s0to11,
  1018. .info = &max1238_info,
  1019. .channels = max1038_channels,
  1020. .num_channels = ARRAY_SIZE(max1038_channels),
  1021. },
  1022. [max1039] = {
  1023. .bits = 8,
  1024. .int_vref_mv = 2048,
  1025. .mode_list = max1238_mode_list,
  1026. .num_modes = ARRAY_SIZE(max1238_mode_list),
  1027. .default_mode = s0to11,
  1028. .info = &max1238_info,
  1029. .channels = max1038_channels,
  1030. .num_channels = ARRAY_SIZE(max1038_channels),
  1031. },
  1032. [max1136] = {
  1033. .bits = 10,
  1034. .int_vref_mv = 4096,
  1035. .mode_list = max1236_mode_list,
  1036. .num_modes = ARRAY_SIZE(max1236_mode_list),
  1037. .default_mode = s0to3,
  1038. .info = &max1238_info,
  1039. .channels = max1136_channels,
  1040. .num_channels = ARRAY_SIZE(max1136_channels),
  1041. },
  1042. [max1137] = {
  1043. .bits = 10,
  1044. .int_vref_mv = 2048,
  1045. .mode_list = max1236_mode_list,
  1046. .num_modes = ARRAY_SIZE(max1236_mode_list),
  1047. .default_mode = s0to3,
  1048. .info = &max1238_info,
  1049. .channels = max1136_channels,
  1050. .num_channels = ARRAY_SIZE(max1136_channels),
  1051. },
  1052. [max1138] = {
  1053. .bits = 10,
  1054. .int_vref_mv = 4096,
  1055. .mode_list = max1238_mode_list,
  1056. .num_modes = ARRAY_SIZE(max1238_mode_list),
  1057. .default_mode = s0to11,
  1058. .info = &max1238_info,
  1059. .channels = max1138_channels,
  1060. .num_channels = ARRAY_SIZE(max1138_channels),
  1061. },
  1062. [max1139] = {
  1063. .bits = 10,
  1064. .int_vref_mv = 2048,
  1065. .mode_list = max1238_mode_list,
  1066. .num_modes = ARRAY_SIZE(max1238_mode_list),
  1067. .default_mode = s0to11,
  1068. .info = &max1238_info,
  1069. .channels = max1138_channels,
  1070. .num_channels = ARRAY_SIZE(max1138_channels),
  1071. },
  1072. [max1236] = {
  1073. .bits = 12,
  1074. .int_vref_mv = 4096,
  1075. .mode_list = max1236_mode_list,
  1076. .num_modes = ARRAY_SIZE(max1236_mode_list),
  1077. .default_mode = s0to3,
  1078. .info = &max1238_info,
  1079. .channels = max1236_channels,
  1080. .num_channels = ARRAY_SIZE(max1236_channels),
  1081. },
  1082. [max1237] = {
  1083. .bits = 12,
  1084. .int_vref_mv = 2048,
  1085. .mode_list = max1236_mode_list,
  1086. .num_modes = ARRAY_SIZE(max1236_mode_list),
  1087. .default_mode = s0to3,
  1088. .info = &max1238_info,
  1089. .channels = max1236_channels,
  1090. .num_channels = ARRAY_SIZE(max1236_channels),
  1091. },
  1092. [max1238] = {
  1093. .bits = 12,
  1094. .int_vref_mv = 4096,
  1095. .mode_list = max1238_mode_list,
  1096. .num_modes = ARRAY_SIZE(max1238_mode_list),
  1097. .default_mode = s0to11,
  1098. .info = &max1238_info,
  1099. .channels = max1238_channels,
  1100. .num_channels = ARRAY_SIZE(max1238_channels),
  1101. },
  1102. [max1239] = {
  1103. .bits = 12,
  1104. .int_vref_mv = 2048,
  1105. .mode_list = max1238_mode_list,
  1106. .num_modes = ARRAY_SIZE(max1238_mode_list),
  1107. .default_mode = s0to11,
  1108. .info = &max1238_info,
  1109. .channels = max1238_channels,
  1110. .num_channels = ARRAY_SIZE(max1238_channels),
  1111. },
  1112. [max11600] = {
  1113. .bits = 8,
  1114. .int_vref_mv = 4096,
  1115. .mode_list = max11607_mode_list,
  1116. .num_modes = ARRAY_SIZE(max11607_mode_list),
  1117. .default_mode = s0to3,
  1118. .info = &max1238_info,
  1119. .channels = max1036_channels,
  1120. .num_channels = ARRAY_SIZE(max1036_channels),
  1121. },
  1122. [max11601] = {
  1123. .bits = 8,
  1124. .int_vref_mv = 2048,
  1125. .mode_list = max11607_mode_list,
  1126. .num_modes = ARRAY_SIZE(max11607_mode_list),
  1127. .default_mode = s0to3,
  1128. .info = &max1238_info,
  1129. .channels = max1036_channels,
  1130. .num_channels = ARRAY_SIZE(max1036_channels),
  1131. },
  1132. [max11602] = {
  1133. .bits = 8,
  1134. .int_vref_mv = 4096,
  1135. .mode_list = max11608_mode_list,
  1136. .num_modes = ARRAY_SIZE(max11608_mode_list),
  1137. .default_mode = s0to7,
  1138. .info = &max1238_info,
  1139. .channels = max11602_channels,
  1140. .num_channels = ARRAY_SIZE(max11602_channels),
  1141. },
  1142. [max11603] = {
  1143. .bits = 8,
  1144. .int_vref_mv = 2048,
  1145. .mode_list = max11608_mode_list,
  1146. .num_modes = ARRAY_SIZE(max11608_mode_list),
  1147. .default_mode = s0to7,
  1148. .info = &max1238_info,
  1149. .channels = max11602_channels,
  1150. .num_channels = ARRAY_SIZE(max11602_channels),
  1151. },
  1152. [max11604] = {
  1153. .bits = 8,
  1154. .int_vref_mv = 4096,
  1155. .mode_list = max1238_mode_list,
  1156. .num_modes = ARRAY_SIZE(max1238_mode_list),
  1157. .default_mode = s0to11,
  1158. .info = &max1238_info,
  1159. .channels = max1038_channels,
  1160. .num_channels = ARRAY_SIZE(max1038_channels),
  1161. },
  1162. [max11605] = {
  1163. .bits = 8,
  1164. .int_vref_mv = 2048,
  1165. .mode_list = max1238_mode_list,
  1166. .num_modes = ARRAY_SIZE(max1238_mode_list),
  1167. .default_mode = s0to11,
  1168. .info = &max1238_info,
  1169. .channels = max1038_channels,
  1170. .num_channels = ARRAY_SIZE(max1038_channels),
  1171. },
  1172. [max11606] = {
  1173. .bits = 10,
  1174. .int_vref_mv = 4096,
  1175. .mode_list = max11607_mode_list,
  1176. .num_modes = ARRAY_SIZE(max11607_mode_list),
  1177. .default_mode = s0to3,
  1178. .info = &max1238_info,
  1179. .channels = max1136_channels,
  1180. .num_channels = ARRAY_SIZE(max1136_channels),
  1181. },
  1182. [max11607] = {
  1183. .bits = 10,
  1184. .int_vref_mv = 2048,
  1185. .mode_list = max11607_mode_list,
  1186. .num_modes = ARRAY_SIZE(max11607_mode_list),
  1187. .default_mode = s0to3,
  1188. .info = &max1238_info,
  1189. .channels = max1136_channels,
  1190. .num_channels = ARRAY_SIZE(max1136_channels),
  1191. },
  1192. [max11608] = {
  1193. .bits = 10,
  1194. .int_vref_mv = 4096,
  1195. .mode_list = max11608_mode_list,
  1196. .num_modes = ARRAY_SIZE(max11608_mode_list),
  1197. .default_mode = s0to7,
  1198. .info = &max1238_info,
  1199. .channels = max11608_channels,
  1200. .num_channels = ARRAY_SIZE(max11608_channels),
  1201. },
  1202. [max11609] = {
  1203. .bits = 10,
  1204. .int_vref_mv = 2048,
  1205. .mode_list = max11608_mode_list,
  1206. .num_modes = ARRAY_SIZE(max11608_mode_list),
  1207. .default_mode = s0to7,
  1208. .info = &max1238_info,
  1209. .channels = max11608_channels,
  1210. .num_channels = ARRAY_SIZE(max11608_channels),
  1211. },
  1212. [max11610] = {
  1213. .bits = 10,
  1214. .int_vref_mv = 4096,
  1215. .mode_list = max1238_mode_list,
  1216. .num_modes = ARRAY_SIZE(max1238_mode_list),
  1217. .default_mode = s0to11,
  1218. .info = &max1238_info,
  1219. .channels = max1138_channels,
  1220. .num_channels = ARRAY_SIZE(max1138_channels),
  1221. },
  1222. [max11611] = {
  1223. .bits = 10,
  1224. .int_vref_mv = 2048,
  1225. .mode_list = max1238_mode_list,
  1226. .num_modes = ARRAY_SIZE(max1238_mode_list),
  1227. .default_mode = s0to11,
  1228. .info = &max1238_info,
  1229. .channels = max1138_channels,
  1230. .num_channels = ARRAY_SIZE(max1138_channels),
  1231. },
  1232. [max11612] = {
  1233. .bits = 12,
  1234. .int_vref_mv = 4096,
  1235. .mode_list = max11607_mode_list,
  1236. .num_modes = ARRAY_SIZE(max11607_mode_list),
  1237. .default_mode = s0to3,
  1238. .info = &max1238_info,
  1239. .channels = max1363_channels,
  1240. .num_channels = ARRAY_SIZE(max1363_channels),
  1241. },
  1242. [max11613] = {
  1243. .bits = 12,
  1244. .int_vref_mv = 2048,
  1245. .mode_list = max11607_mode_list,
  1246. .num_modes = ARRAY_SIZE(max11607_mode_list),
  1247. .default_mode = s0to3,
  1248. .info = &max1238_info,
  1249. .channels = max1363_channels,
  1250. .num_channels = ARRAY_SIZE(max1363_channels),
  1251. },
  1252. [max11614] = {
  1253. .bits = 12,
  1254. .int_vref_mv = 4096,
  1255. .mode_list = max11608_mode_list,
  1256. .num_modes = ARRAY_SIZE(max11608_mode_list),
  1257. .default_mode = s0to7,
  1258. .info = &max1238_info,
  1259. .channels = max11614_channels,
  1260. .num_channels = ARRAY_SIZE(max11614_channels),
  1261. },
  1262. [max11615] = {
  1263. .bits = 12,
  1264. .int_vref_mv = 2048,
  1265. .mode_list = max11608_mode_list,
  1266. .num_modes = ARRAY_SIZE(max11608_mode_list),
  1267. .default_mode = s0to7,
  1268. .info = &max1238_info,
  1269. .channels = max11614_channels,
  1270. .num_channels = ARRAY_SIZE(max11614_channels),
  1271. },
  1272. [max11616] = {
  1273. .bits = 12,
  1274. .int_vref_mv = 4096,
  1275. .mode_list = max1238_mode_list,
  1276. .num_modes = ARRAY_SIZE(max1238_mode_list),
  1277. .default_mode = s0to11,
  1278. .info = &max1238_info,
  1279. .channels = max1238_channels,
  1280. .num_channels = ARRAY_SIZE(max1238_channels),
  1281. },
  1282. [max11617] = {
  1283. .bits = 12,
  1284. .int_vref_mv = 2048,
  1285. .mode_list = max1238_mode_list,
  1286. .num_modes = ARRAY_SIZE(max1238_mode_list),
  1287. .default_mode = s0to11,
  1288. .info = &max1238_info,
  1289. .channels = max1238_channels,
  1290. .num_channels = ARRAY_SIZE(max1238_channels),
  1291. },
  1292. [max11644] = {
  1293. .bits = 12,
  1294. .int_vref_mv = 4096,
  1295. .mode_list = max11644_mode_list,
  1296. .num_modes = ARRAY_SIZE(max11644_mode_list),
  1297. .default_mode = s0to1,
  1298. .info = &max1238_info,
  1299. .channels = max11644_channels,
  1300. .num_channels = ARRAY_SIZE(max11644_channels),
  1301. },
  1302. [max11645] = {
  1303. .bits = 12,
  1304. .int_vref_mv = 2048,
  1305. .mode_list = max11644_mode_list,
  1306. .num_modes = ARRAY_SIZE(max11644_mode_list),
  1307. .default_mode = s0to1,
  1308. .info = &max1238_info,
  1309. .channels = max11644_channels,
  1310. .num_channels = ARRAY_SIZE(max11644_channels),
  1311. },
  1312. [max11646] = {
  1313. .bits = 10,
  1314. .int_vref_mv = 4096,
  1315. .mode_list = max11644_mode_list,
  1316. .num_modes = ARRAY_SIZE(max11644_mode_list),
  1317. .default_mode = s0to1,
  1318. .info = &max1238_info,
  1319. .channels = max11646_channels,
  1320. .num_channels = ARRAY_SIZE(max11646_channels),
  1321. },
  1322. [max11647] = {
  1323. .bits = 10,
  1324. .int_vref_mv = 2048,
  1325. .mode_list = max11644_mode_list,
  1326. .num_modes = ARRAY_SIZE(max11644_mode_list),
  1327. .default_mode = s0to1,
  1328. .info = &max1238_info,
  1329. .channels = max11646_channels,
  1330. .num_channels = ARRAY_SIZE(max11646_channels),
  1331. },
  1332. };
  1333. static int max1363_initial_setup(struct max1363_state *st)
  1334. {
  1335. st->setupbyte = MAX1363_SETUP_INT_CLOCK
  1336. | MAX1363_SETUP_UNIPOLAR
  1337. | MAX1363_SETUP_NORESET;
  1338. if (st->vref)
  1339. st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF;
  1340. else
  1341. st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF
  1342. | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT;
  1343. /* Set scan mode writes the config anyway so wait until then */
  1344. st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
  1345. st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
  1346. st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
  1347. return max1363_set_scan_mode(st);
  1348. }
  1349. static int max1363_alloc_scan_masks(struct iio_dev *indio_dev)
  1350. {
  1351. struct max1363_state *st = iio_priv(indio_dev);
  1352. unsigned long *masks;
  1353. int i;
  1354. masks = devm_kzalloc(&indio_dev->dev,
  1355. array3_size(BITS_TO_LONGS(MAX1363_MAX_CHANNELS),
  1356. sizeof(long),
  1357. st->chip_info->num_modes + 1),
  1358. GFP_KERNEL);
  1359. if (!masks)
  1360. return -ENOMEM;
  1361. for (i = 0; i < st->chip_info->num_modes; i++)
  1362. bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i,
  1363. max1363_mode_table[st->chip_info->mode_list[i]]
  1364. .modemask, MAX1363_MAX_CHANNELS);
  1365. indio_dev->available_scan_masks = masks;
  1366. return 0;
  1367. }
  1368. static irqreturn_t max1363_trigger_handler(int irq, void *p)
  1369. {
  1370. struct iio_poll_func *pf = p;
  1371. struct iio_dev *indio_dev = pf->indio_dev;
  1372. struct max1363_state *st = iio_priv(indio_dev);
  1373. __u8 *rxbuf;
  1374. int b_sent;
  1375. size_t d_size;
  1376. unsigned long numvals = bitmap_weight(st->current_mode->modemask,
  1377. MAX1363_MAX_CHANNELS);
  1378. /* Ensure the timestamp is 8 byte aligned */
  1379. if (st->chip_info->bits != 8)
  1380. d_size = numvals*2;
  1381. else
  1382. d_size = numvals;
  1383. if (indio_dev->scan_timestamp) {
  1384. d_size += sizeof(s64);
  1385. if (d_size % sizeof(s64))
  1386. d_size += sizeof(s64) - (d_size % sizeof(s64));
  1387. }
  1388. /* Monitor mode prevents reading. Whilst not currently implemented
  1389. * might as well have this test in here in the meantime as it does
  1390. * no harm.
  1391. */
  1392. if (numvals == 0)
  1393. goto done;
  1394. rxbuf = kmalloc(d_size, GFP_KERNEL);
  1395. if (rxbuf == NULL)
  1396. goto done;
  1397. if (st->chip_info->bits != 8)
  1398. b_sent = st->recv(st->client, rxbuf, numvals * 2);
  1399. else
  1400. b_sent = st->recv(st->client, rxbuf, numvals);
  1401. if (b_sent < 0)
  1402. goto done_free;
  1403. iio_push_to_buffers_with_timestamp(indio_dev, rxbuf,
  1404. iio_get_time_ns(indio_dev));
  1405. done_free:
  1406. kfree(rxbuf);
  1407. done:
  1408. iio_trigger_notify_done(indio_dev->trig);
  1409. return IRQ_HANDLED;
  1410. }
  1411. #define MAX1363_COMPATIBLE(of_compatible, cfg) { \
  1412. .compatible = of_compatible, \
  1413. .data = &max1363_chip_info_tbl[cfg], \
  1414. }
  1415. static const struct of_device_id max1363_of_match[] = {
  1416. MAX1363_COMPATIBLE("maxim,max1361", max1361),
  1417. MAX1363_COMPATIBLE("maxim,max1362", max1362),
  1418. MAX1363_COMPATIBLE("maxim,max1363", max1363),
  1419. MAX1363_COMPATIBLE("maxim,max1364", max1364),
  1420. MAX1363_COMPATIBLE("maxim,max1036", max1036),
  1421. MAX1363_COMPATIBLE("maxim,max1037", max1037),
  1422. MAX1363_COMPATIBLE("maxim,max1038", max1038),
  1423. MAX1363_COMPATIBLE("maxim,max1039", max1039),
  1424. MAX1363_COMPATIBLE("maxim,max1136", max1136),
  1425. MAX1363_COMPATIBLE("maxim,max1137", max1137),
  1426. MAX1363_COMPATIBLE("maxim,max1138", max1138),
  1427. MAX1363_COMPATIBLE("maxim,max1139", max1139),
  1428. MAX1363_COMPATIBLE("maxim,max1236", max1236),
  1429. MAX1363_COMPATIBLE("maxim,max1237", max1237),
  1430. MAX1363_COMPATIBLE("maxim,max1238", max1238),
  1431. MAX1363_COMPATIBLE("maxim,max1239", max1239),
  1432. MAX1363_COMPATIBLE("maxim,max11600", max11600),
  1433. MAX1363_COMPATIBLE("maxim,max11601", max11601),
  1434. MAX1363_COMPATIBLE("maxim,max11602", max11602),
  1435. MAX1363_COMPATIBLE("maxim,max11603", max11603),
  1436. MAX1363_COMPATIBLE("maxim,max11604", max11604),
  1437. MAX1363_COMPATIBLE("maxim,max11605", max11605),
  1438. MAX1363_COMPATIBLE("maxim,max11606", max11606),
  1439. MAX1363_COMPATIBLE("maxim,max11607", max11607),
  1440. MAX1363_COMPATIBLE("maxim,max11608", max11608),
  1441. MAX1363_COMPATIBLE("maxim,max11609", max11609),
  1442. MAX1363_COMPATIBLE("maxim,max11610", max11610),
  1443. MAX1363_COMPATIBLE("maxim,max11611", max11611),
  1444. MAX1363_COMPATIBLE("maxim,max11612", max11612),
  1445. MAX1363_COMPATIBLE("maxim,max11613", max11613),
  1446. MAX1363_COMPATIBLE("maxim,max11614", max11614),
  1447. MAX1363_COMPATIBLE("maxim,max11615", max11615),
  1448. MAX1363_COMPATIBLE("maxim,max11616", max11616),
  1449. MAX1363_COMPATIBLE("maxim,max11617", max11617),
  1450. MAX1363_COMPATIBLE("maxim,max11644", max11644),
  1451. MAX1363_COMPATIBLE("maxim,max11645", max11645),
  1452. MAX1363_COMPATIBLE("maxim,max11646", max11646),
  1453. MAX1363_COMPATIBLE("maxim,max11647", max11647),
  1454. { /* sentinel */ }
  1455. };
  1456. MODULE_DEVICE_TABLE(of, max1363_of_match);
  1457. static int max1363_probe(struct i2c_client *client,
  1458. const struct i2c_device_id *id)
  1459. {
  1460. int ret;
  1461. struct max1363_state *st;
  1462. struct iio_dev *indio_dev;
  1463. struct regulator *vref;
  1464. indio_dev = devm_iio_device_alloc(&client->dev,
  1465. sizeof(struct max1363_state));
  1466. if (!indio_dev)
  1467. return -ENOMEM;
  1468. ret = iio_map_array_register(indio_dev, client->dev.platform_data);
  1469. if (ret < 0)
  1470. return ret;
  1471. st = iio_priv(indio_dev);
  1472. mutex_init(&st->lock);
  1473. st->reg = devm_regulator_get(&client->dev, "vcc");
  1474. if (IS_ERR(st->reg)) {
  1475. ret = PTR_ERR(st->reg);
  1476. goto error_unregister_map;
  1477. }
  1478. ret = regulator_enable(st->reg);
  1479. if (ret)
  1480. goto error_unregister_map;
  1481. /* this is only used for device removal purposes */
  1482. i2c_set_clientdata(client, indio_dev);
  1483. st->chip_info = device_get_match_data(&client->dev);
  1484. if (!st->chip_info)
  1485. st->chip_info = &max1363_chip_info_tbl[id->driver_data];
  1486. st->client = client;
  1487. st->vref_uv = st->chip_info->int_vref_mv * 1000;
  1488. vref = devm_regulator_get_optional(&client->dev, "vref");
  1489. if (!IS_ERR(vref)) {
  1490. int vref_uv;
  1491. ret = regulator_enable(vref);
  1492. if (ret)
  1493. goto error_disable_reg;
  1494. st->vref = vref;
  1495. vref_uv = regulator_get_voltage(vref);
  1496. if (vref_uv <= 0) {
  1497. ret = -EINVAL;
  1498. goto error_disable_reg;
  1499. }
  1500. st->vref_uv = vref_uv;
  1501. }
  1502. if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
  1503. st->send = i2c_master_send;
  1504. st->recv = i2c_master_recv;
  1505. } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE)
  1506. && st->chip_info->bits == 8) {
  1507. st->send = max1363_smbus_send;
  1508. st->recv = max1363_smbus_recv;
  1509. } else {
  1510. ret = -EOPNOTSUPP;
  1511. goto error_disable_reg;
  1512. }
  1513. ret = max1363_alloc_scan_masks(indio_dev);
  1514. if (ret)
  1515. goto error_disable_reg;
  1516. indio_dev->name = id->name;
  1517. indio_dev->channels = st->chip_info->channels;
  1518. indio_dev->num_channels = st->chip_info->num_channels;
  1519. indio_dev->info = st->chip_info->info;
  1520. indio_dev->modes = INDIO_DIRECT_MODE;
  1521. ret = max1363_initial_setup(st);
  1522. if (ret < 0)
  1523. goto error_disable_reg;
  1524. ret = iio_triggered_buffer_setup(indio_dev, NULL,
  1525. &max1363_trigger_handler, NULL);
  1526. if (ret)
  1527. goto error_disable_reg;
  1528. if (client->irq) {
  1529. ret = devm_request_threaded_irq(&client->dev, st->client->irq,
  1530. NULL,
  1531. &max1363_event_handler,
  1532. IRQF_TRIGGER_RISING | IRQF_ONESHOT,
  1533. "max1363_event",
  1534. indio_dev);
  1535. if (ret)
  1536. goto error_uninit_buffer;
  1537. }
  1538. ret = iio_device_register(indio_dev);
  1539. if (ret < 0)
  1540. goto error_uninit_buffer;
  1541. return 0;
  1542. error_uninit_buffer:
  1543. iio_triggered_buffer_cleanup(indio_dev);
  1544. error_disable_reg:
  1545. if (st->vref)
  1546. regulator_disable(st->vref);
  1547. regulator_disable(st->reg);
  1548. error_unregister_map:
  1549. iio_map_array_unregister(indio_dev);
  1550. return ret;
  1551. }
  1552. static int max1363_remove(struct i2c_client *client)
  1553. {
  1554. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  1555. struct max1363_state *st = iio_priv(indio_dev);
  1556. iio_device_unregister(indio_dev);
  1557. iio_triggered_buffer_cleanup(indio_dev);
  1558. if (st->vref)
  1559. regulator_disable(st->vref);
  1560. regulator_disable(st->reg);
  1561. iio_map_array_unregister(indio_dev);
  1562. return 0;
  1563. }
  1564. static const struct i2c_device_id max1363_id[] = {
  1565. { "max1361", max1361 },
  1566. { "max1362", max1362 },
  1567. { "max1363", max1363 },
  1568. { "max1364", max1364 },
  1569. { "max1036", max1036 },
  1570. { "max1037", max1037 },
  1571. { "max1038", max1038 },
  1572. { "max1039", max1039 },
  1573. { "max1136", max1136 },
  1574. { "max1137", max1137 },
  1575. { "max1138", max1138 },
  1576. { "max1139", max1139 },
  1577. { "max1236", max1236 },
  1578. { "max1237", max1237 },
  1579. { "max1238", max1238 },
  1580. { "max1239", max1239 },
  1581. { "max11600", max11600 },
  1582. { "max11601", max11601 },
  1583. { "max11602", max11602 },
  1584. { "max11603", max11603 },
  1585. { "max11604", max11604 },
  1586. { "max11605", max11605 },
  1587. { "max11606", max11606 },
  1588. { "max11607", max11607 },
  1589. { "max11608", max11608 },
  1590. { "max11609", max11609 },
  1591. { "max11610", max11610 },
  1592. { "max11611", max11611 },
  1593. { "max11612", max11612 },
  1594. { "max11613", max11613 },
  1595. { "max11614", max11614 },
  1596. { "max11615", max11615 },
  1597. { "max11616", max11616 },
  1598. { "max11617", max11617 },
  1599. { "max11644", max11644 },
  1600. { "max11645", max11645 },
  1601. { "max11646", max11646 },
  1602. { "max11647", max11647 },
  1603. {}
  1604. };
  1605. MODULE_DEVICE_TABLE(i2c, max1363_id);
  1606. static struct i2c_driver max1363_driver = {
  1607. .driver = {
  1608. .name = "max1363",
  1609. .of_match_table = max1363_of_match,
  1610. },
  1611. .probe = max1363_probe,
  1612. .remove = max1363_remove,
  1613. .id_table = max1363_id,
  1614. };
  1615. module_i2c_driver(max1363_driver);
  1616. MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
  1617. MODULE_DESCRIPTION("Maxim 1363 ADC");
  1618. MODULE_LICENSE("GPL v2");