max1027.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * iio/adc/max1027.c
  4. * Copyright (C) 2014 Philippe Reynes
  5. *
  6. * based on linux/drivers/iio/ad7923.c
  7. * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
  8. * Copyright 2012 CS Systemes d'Information
  9. *
  10. * max1027.c
  11. *
  12. * Partial support for max1027 and similar chips.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/mod_devicetable.h>
  17. #include <linux/spi/spi.h>
  18. #include <linux/delay.h>
  19. #include <linux/iio/iio.h>
  20. #include <linux/iio/buffer.h>
  21. #include <linux/iio/trigger.h>
  22. #include <linux/iio/trigger_consumer.h>
  23. #include <linux/iio/triggered_buffer.h>
  24. #define MAX1027_CONV_REG BIT(7)
  25. #define MAX1027_SETUP_REG BIT(6)
  26. #define MAX1027_AVG_REG BIT(5)
  27. #define MAX1027_RST_REG BIT(4)
  28. /* conversion register */
  29. #define MAX1027_TEMP BIT(0)
  30. #define MAX1027_SCAN_0_N (0x00 << 1)
  31. #define MAX1027_SCAN_N_M (0x01 << 1)
  32. #define MAX1027_SCAN_N (0x02 << 1)
  33. #define MAX1027_NOSCAN (0x03 << 1)
  34. #define MAX1027_CHAN(n) ((n) << 3)
  35. /* setup register */
  36. #define MAX1027_UNIPOLAR 0x02
  37. #define MAX1027_BIPOLAR 0x03
  38. #define MAX1027_REF_MODE0 (0x00 << 2)
  39. #define MAX1027_REF_MODE1 (0x01 << 2)
  40. #define MAX1027_REF_MODE2 (0x02 << 2)
  41. #define MAX1027_REF_MODE3 (0x03 << 2)
  42. #define MAX1027_CKS_MODE0 (0x00 << 4)
  43. #define MAX1027_CKS_MODE1 (0x01 << 4)
  44. #define MAX1027_CKS_MODE2 (0x02 << 4)
  45. #define MAX1027_CKS_MODE3 (0x03 << 4)
  46. /* averaging register */
  47. #define MAX1027_NSCAN_4 0x00
  48. #define MAX1027_NSCAN_8 0x01
  49. #define MAX1027_NSCAN_12 0x02
  50. #define MAX1027_NSCAN_16 0x03
  51. #define MAX1027_NAVG_4 (0x00 << 2)
  52. #define MAX1027_NAVG_8 (0x01 << 2)
  53. #define MAX1027_NAVG_16 (0x02 << 2)
  54. #define MAX1027_NAVG_32 (0x03 << 2)
  55. #define MAX1027_AVG_EN BIT(4)
  56. enum max1027_id {
  57. max1027,
  58. max1029,
  59. max1031,
  60. max1227,
  61. max1229,
  62. max1231,
  63. };
  64. static const struct spi_device_id max1027_id[] = {
  65. {"max1027", max1027},
  66. {"max1029", max1029},
  67. {"max1031", max1031},
  68. {"max1227", max1227},
  69. {"max1229", max1229},
  70. {"max1231", max1231},
  71. {}
  72. };
  73. MODULE_DEVICE_TABLE(spi, max1027_id);
  74. static const struct of_device_id max1027_adc_dt_ids[] = {
  75. { .compatible = "maxim,max1027" },
  76. { .compatible = "maxim,max1029" },
  77. { .compatible = "maxim,max1031" },
  78. { .compatible = "maxim,max1227" },
  79. { .compatible = "maxim,max1229" },
  80. { .compatible = "maxim,max1231" },
  81. {},
  82. };
  83. MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids);
  84. #define MAX1027_V_CHAN(index, depth) \
  85. { \
  86. .type = IIO_VOLTAGE, \
  87. .indexed = 1, \
  88. .channel = index, \
  89. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  90. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  91. .scan_index = index + 1, \
  92. .scan_type = { \
  93. .sign = 'u', \
  94. .realbits = depth, \
  95. .storagebits = 16, \
  96. .shift = (depth == 10) ? 2 : 0, \
  97. .endianness = IIO_BE, \
  98. }, \
  99. }
  100. #define MAX1027_T_CHAN \
  101. { \
  102. .type = IIO_TEMP, \
  103. .channel = 0, \
  104. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  105. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  106. .scan_index = 0, \
  107. .scan_type = { \
  108. .sign = 'u', \
  109. .realbits = 12, \
  110. .storagebits = 16, \
  111. .endianness = IIO_BE, \
  112. }, \
  113. }
  114. #define MAX1X27_CHANNELS(depth) \
  115. MAX1027_T_CHAN, \
  116. MAX1027_V_CHAN(0, depth), \
  117. MAX1027_V_CHAN(1, depth), \
  118. MAX1027_V_CHAN(2, depth), \
  119. MAX1027_V_CHAN(3, depth), \
  120. MAX1027_V_CHAN(4, depth), \
  121. MAX1027_V_CHAN(5, depth), \
  122. MAX1027_V_CHAN(6, depth), \
  123. MAX1027_V_CHAN(7, depth)
  124. #define MAX1X29_CHANNELS(depth) \
  125. MAX1X27_CHANNELS(depth), \
  126. MAX1027_V_CHAN(8, depth), \
  127. MAX1027_V_CHAN(9, depth), \
  128. MAX1027_V_CHAN(10, depth), \
  129. MAX1027_V_CHAN(11, depth)
  130. #define MAX1X31_CHANNELS(depth) \
  131. MAX1X29_CHANNELS(depth), \
  132. MAX1027_V_CHAN(12, depth), \
  133. MAX1027_V_CHAN(13, depth), \
  134. MAX1027_V_CHAN(14, depth), \
  135. MAX1027_V_CHAN(15, depth)
  136. static const struct iio_chan_spec max1027_channels[] = {
  137. MAX1X27_CHANNELS(10),
  138. };
  139. static const struct iio_chan_spec max1029_channels[] = {
  140. MAX1X29_CHANNELS(10),
  141. };
  142. static const struct iio_chan_spec max1031_channels[] = {
  143. MAX1X31_CHANNELS(10),
  144. };
  145. static const struct iio_chan_spec max1227_channels[] = {
  146. MAX1X27_CHANNELS(12),
  147. };
  148. static const struct iio_chan_spec max1229_channels[] = {
  149. MAX1X29_CHANNELS(12),
  150. };
  151. static const struct iio_chan_spec max1231_channels[] = {
  152. MAX1X31_CHANNELS(12),
  153. };
  154. static const unsigned long max1027_available_scan_masks[] = {
  155. 0x000001ff,
  156. 0x00000000,
  157. };
  158. static const unsigned long max1029_available_scan_masks[] = {
  159. 0x00001fff,
  160. 0x00000000,
  161. };
  162. static const unsigned long max1031_available_scan_masks[] = {
  163. 0x0001ffff,
  164. 0x00000000,
  165. };
  166. struct max1027_chip_info {
  167. const struct iio_chan_spec *channels;
  168. unsigned int num_channels;
  169. const unsigned long *available_scan_masks;
  170. };
  171. static const struct max1027_chip_info max1027_chip_info_tbl[] = {
  172. [max1027] = {
  173. .channels = max1027_channels,
  174. .num_channels = ARRAY_SIZE(max1027_channels),
  175. .available_scan_masks = max1027_available_scan_masks,
  176. },
  177. [max1029] = {
  178. .channels = max1029_channels,
  179. .num_channels = ARRAY_SIZE(max1029_channels),
  180. .available_scan_masks = max1029_available_scan_masks,
  181. },
  182. [max1031] = {
  183. .channels = max1031_channels,
  184. .num_channels = ARRAY_SIZE(max1031_channels),
  185. .available_scan_masks = max1031_available_scan_masks,
  186. },
  187. [max1227] = {
  188. .channels = max1227_channels,
  189. .num_channels = ARRAY_SIZE(max1227_channels),
  190. .available_scan_masks = max1027_available_scan_masks,
  191. },
  192. [max1229] = {
  193. .channels = max1229_channels,
  194. .num_channels = ARRAY_SIZE(max1229_channels),
  195. .available_scan_masks = max1029_available_scan_masks,
  196. },
  197. [max1231] = {
  198. .channels = max1231_channels,
  199. .num_channels = ARRAY_SIZE(max1231_channels),
  200. .available_scan_masks = max1031_available_scan_masks,
  201. },
  202. };
  203. struct max1027_state {
  204. const struct max1027_chip_info *info;
  205. struct spi_device *spi;
  206. struct iio_trigger *trig;
  207. __be16 *buffer;
  208. struct mutex lock;
  209. u8 reg ____cacheline_aligned;
  210. };
  211. static int max1027_read_single_value(struct iio_dev *indio_dev,
  212. struct iio_chan_spec const *chan,
  213. int *val)
  214. {
  215. int ret;
  216. struct max1027_state *st = iio_priv(indio_dev);
  217. if (iio_buffer_enabled(indio_dev)) {
  218. dev_warn(&indio_dev->dev, "trigger mode already enabled");
  219. return -EBUSY;
  220. }
  221. /* Start acquisition on conversion register write */
  222. st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2 | MAX1027_CKS_MODE2;
  223. ret = spi_write(st->spi, &st->reg, 1);
  224. if (ret < 0) {
  225. dev_err(&indio_dev->dev,
  226. "Failed to configure setup register\n");
  227. return ret;
  228. }
  229. /* Configure conversion register with the requested chan */
  230. st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) |
  231. MAX1027_NOSCAN;
  232. if (chan->type == IIO_TEMP)
  233. st->reg |= MAX1027_TEMP;
  234. ret = spi_write(st->spi, &st->reg, 1);
  235. if (ret < 0) {
  236. dev_err(&indio_dev->dev,
  237. "Failed to configure conversion register\n");
  238. return ret;
  239. }
  240. /*
  241. * For an unknown reason, when we use the mode "10" (write
  242. * conversion register), the interrupt doesn't occur every time.
  243. * So we just wait 1 ms.
  244. */
  245. mdelay(1);
  246. /* Read result */
  247. ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2);
  248. if (ret < 0)
  249. return ret;
  250. *val = be16_to_cpu(st->buffer[0]);
  251. return IIO_VAL_INT;
  252. }
  253. static int max1027_read_raw(struct iio_dev *indio_dev,
  254. struct iio_chan_spec const *chan,
  255. int *val, int *val2, long mask)
  256. {
  257. int ret = 0;
  258. struct max1027_state *st = iio_priv(indio_dev);
  259. mutex_lock(&st->lock);
  260. switch (mask) {
  261. case IIO_CHAN_INFO_RAW:
  262. ret = max1027_read_single_value(indio_dev, chan, val);
  263. break;
  264. case IIO_CHAN_INFO_SCALE:
  265. switch (chan->type) {
  266. case IIO_TEMP:
  267. *val = 1;
  268. *val2 = 8;
  269. ret = IIO_VAL_FRACTIONAL;
  270. break;
  271. case IIO_VOLTAGE:
  272. *val = 2500;
  273. *val2 = chan->scan_type.realbits;
  274. ret = IIO_VAL_FRACTIONAL_LOG2;
  275. break;
  276. default:
  277. ret = -EINVAL;
  278. break;
  279. }
  280. break;
  281. default:
  282. ret = -EINVAL;
  283. break;
  284. }
  285. mutex_unlock(&st->lock);
  286. return ret;
  287. }
  288. static int max1027_debugfs_reg_access(struct iio_dev *indio_dev,
  289. unsigned reg, unsigned writeval,
  290. unsigned *readval)
  291. {
  292. struct max1027_state *st = iio_priv(indio_dev);
  293. u8 *val = (u8 *)st->buffer;
  294. if (readval) {
  295. int ret = spi_read(st->spi, val, 2);
  296. *readval = be16_to_cpu(st->buffer[0]);
  297. return ret;
  298. }
  299. *val = (u8)writeval;
  300. return spi_write(st->spi, val, 1);
  301. }
  302. static int max1027_validate_trigger(struct iio_dev *indio_dev,
  303. struct iio_trigger *trig)
  304. {
  305. struct max1027_state *st = iio_priv(indio_dev);
  306. if (st->trig != trig)
  307. return -EINVAL;
  308. return 0;
  309. }
  310. static int max1027_set_trigger_state(struct iio_trigger *trig, bool state)
  311. {
  312. struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
  313. struct max1027_state *st = iio_priv(indio_dev);
  314. int ret;
  315. if (state) {
  316. /* Start acquisition on cnvst */
  317. st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE0 |
  318. MAX1027_REF_MODE2;
  319. ret = spi_write(st->spi, &st->reg, 1);
  320. if (ret < 0)
  321. return ret;
  322. /* Scan from 0 to max */
  323. st->reg = MAX1027_CONV_REG | MAX1027_CHAN(0) |
  324. MAX1027_SCAN_N_M | MAX1027_TEMP;
  325. ret = spi_write(st->spi, &st->reg, 1);
  326. if (ret < 0)
  327. return ret;
  328. } else {
  329. /* Start acquisition on conversion register write */
  330. st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE2 |
  331. MAX1027_REF_MODE2;
  332. ret = spi_write(st->spi, &st->reg, 1);
  333. if (ret < 0)
  334. return ret;
  335. }
  336. return 0;
  337. }
  338. static irqreturn_t max1027_trigger_handler(int irq, void *private)
  339. {
  340. struct iio_poll_func *pf = private;
  341. struct iio_dev *indio_dev = pf->indio_dev;
  342. struct max1027_state *st = iio_priv(indio_dev);
  343. pr_debug("%s(irq=%d, private=0x%p)\n", __func__, irq, private);
  344. /* fill buffer with all channel */
  345. spi_read(st->spi, st->buffer, indio_dev->masklength * 2);
  346. iio_push_to_buffers(indio_dev, st->buffer);
  347. iio_trigger_notify_done(indio_dev->trig);
  348. return IRQ_HANDLED;
  349. }
  350. static const struct iio_trigger_ops max1027_trigger_ops = {
  351. .validate_device = &iio_trigger_validate_own_device,
  352. .set_trigger_state = &max1027_set_trigger_state,
  353. };
  354. static const struct iio_info max1027_info = {
  355. .read_raw = &max1027_read_raw,
  356. .validate_trigger = &max1027_validate_trigger,
  357. .debugfs_reg_access = &max1027_debugfs_reg_access,
  358. };
  359. static int max1027_probe(struct spi_device *spi)
  360. {
  361. int ret;
  362. struct iio_dev *indio_dev;
  363. struct max1027_state *st;
  364. pr_debug("%s: probe(spi = 0x%p)\n", __func__, spi);
  365. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  366. if (indio_dev == NULL) {
  367. pr_err("Can't allocate iio device\n");
  368. return -ENOMEM;
  369. }
  370. spi_set_drvdata(spi, indio_dev);
  371. st = iio_priv(indio_dev);
  372. st->spi = spi;
  373. st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data];
  374. mutex_init(&st->lock);
  375. indio_dev->name = spi_get_device_id(spi)->name;
  376. indio_dev->info = &max1027_info;
  377. indio_dev->modes = INDIO_DIRECT_MODE;
  378. indio_dev->channels = st->info->channels;
  379. indio_dev->num_channels = st->info->num_channels;
  380. indio_dev->available_scan_masks = st->info->available_scan_masks;
  381. st->buffer = devm_kmalloc_array(&indio_dev->dev,
  382. indio_dev->num_channels, 2,
  383. GFP_KERNEL);
  384. if (st->buffer == NULL) {
  385. dev_err(&indio_dev->dev, "Can't allocate buffer\n");
  386. return -ENOMEM;
  387. }
  388. if (spi->irq) {
  389. ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
  390. &iio_pollfunc_store_time,
  391. &max1027_trigger_handler,
  392. NULL);
  393. if (ret < 0) {
  394. dev_err(&indio_dev->dev, "Failed to setup buffer\n");
  395. return ret;
  396. }
  397. st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger",
  398. indio_dev->name);
  399. if (st->trig == NULL) {
  400. ret = -ENOMEM;
  401. dev_err(&indio_dev->dev,
  402. "Failed to allocate iio trigger\n");
  403. return ret;
  404. }
  405. st->trig->ops = &max1027_trigger_ops;
  406. st->trig->dev.parent = &spi->dev;
  407. iio_trigger_set_drvdata(st->trig, indio_dev);
  408. ret = devm_iio_trigger_register(&indio_dev->dev,
  409. st->trig);
  410. if (ret < 0) {
  411. dev_err(&indio_dev->dev,
  412. "Failed to register iio trigger\n");
  413. return ret;
  414. }
  415. ret = devm_request_threaded_irq(&spi->dev, spi->irq,
  416. iio_trigger_generic_data_rdy_poll,
  417. NULL,
  418. IRQF_TRIGGER_FALLING,
  419. spi->dev.driver->name,
  420. st->trig);
  421. if (ret < 0) {
  422. dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n");
  423. return ret;
  424. }
  425. }
  426. /* Internal reset */
  427. st->reg = MAX1027_RST_REG;
  428. ret = spi_write(st->spi, &st->reg, 1);
  429. if (ret < 0) {
  430. dev_err(&indio_dev->dev, "Failed to reset the ADC\n");
  431. return ret;
  432. }
  433. /* Disable averaging */
  434. st->reg = MAX1027_AVG_REG;
  435. ret = spi_write(st->spi, &st->reg, 1);
  436. if (ret < 0) {
  437. dev_err(&indio_dev->dev, "Failed to configure averaging register\n");
  438. return ret;
  439. }
  440. return devm_iio_device_register(&spi->dev, indio_dev);
  441. }
  442. static struct spi_driver max1027_driver = {
  443. .driver = {
  444. .name = "max1027",
  445. .of_match_table = max1027_adc_dt_ids,
  446. },
  447. .probe = max1027_probe,
  448. .id_table = max1027_id,
  449. };
  450. module_spi_driver(max1027_driver);
  451. MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>");
  452. MODULE_DESCRIPTION("MAX1X27/MAX1X29/MAX1X31 ADC");
  453. MODULE_LICENSE("GPL v2");