lpc32xx_adc.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * lpc32xx_adc.c - Support for ADC in LPC32XX
  4. *
  5. * 3-channel, 10-bit ADC
  6. *
  7. * Copyright (C) 2011, 2012 Roland Stigge <stigge@antcom.de>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/completion.h>
  11. #include <linux/err.h>
  12. #include <linux/iio/iio.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/module.h>
  16. #include <linux/mod_devicetable.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/regulator/consumer.h>
  19. /*
  20. * LPC32XX registers definitions
  21. */
  22. #define LPC32XXAD_SELECT(x) ((x) + 0x04)
  23. #define LPC32XXAD_CTRL(x) ((x) + 0x08)
  24. #define LPC32XXAD_VALUE(x) ((x) + 0x48)
  25. /* Bit definitions for LPC32XXAD_SELECT: */
  26. /* constant, always write this value! */
  27. #define LPC32XXAD_REFm 0x00000200
  28. /* constant, always write this value! */
  29. #define LPC32XXAD_REFp 0x00000080
  30. /* multiple of this is the channel number: 0, 1, 2 */
  31. #define LPC32XXAD_IN 0x00000010
  32. /* constant, always write this value! */
  33. #define LPC32XXAD_INTERNAL 0x00000004
  34. /* Bit definitions for LPC32XXAD_CTRL: */
  35. #define LPC32XXAD_STROBE 0x00000002
  36. #define LPC32XXAD_PDN_CTRL 0x00000004
  37. /* Bit definitions for LPC32XXAD_VALUE: */
  38. #define LPC32XXAD_VALUE_MASK 0x000003FF
  39. #define LPC32XXAD_NAME "lpc32xx-adc"
  40. struct lpc32xx_adc_state {
  41. void __iomem *adc_base;
  42. struct clk *clk;
  43. struct completion completion;
  44. struct regulator *vref;
  45. u32 value;
  46. };
  47. static int lpc32xx_read_raw(struct iio_dev *indio_dev,
  48. struct iio_chan_spec const *chan,
  49. int *val,
  50. int *val2,
  51. long mask)
  52. {
  53. struct lpc32xx_adc_state *st = iio_priv(indio_dev);
  54. int ret;
  55. switch (mask) {
  56. case IIO_CHAN_INFO_RAW:
  57. mutex_lock(&indio_dev->mlock);
  58. ret = clk_prepare_enable(st->clk);
  59. if (ret) {
  60. mutex_unlock(&indio_dev->mlock);
  61. return ret;
  62. }
  63. /* Measurement setup */
  64. __raw_writel(LPC32XXAD_INTERNAL | (chan->address) |
  65. LPC32XXAD_REFp | LPC32XXAD_REFm,
  66. LPC32XXAD_SELECT(st->adc_base));
  67. /* Trigger conversion */
  68. __raw_writel(LPC32XXAD_PDN_CTRL | LPC32XXAD_STROBE,
  69. LPC32XXAD_CTRL(st->adc_base));
  70. wait_for_completion(&st->completion); /* set by ISR */
  71. clk_disable_unprepare(st->clk);
  72. *val = st->value;
  73. mutex_unlock(&indio_dev->mlock);
  74. return IIO_VAL_INT;
  75. case IIO_CHAN_INFO_SCALE:
  76. *val = regulator_get_voltage(st->vref) / 1000;
  77. *val2 = 10;
  78. return IIO_VAL_FRACTIONAL_LOG2;
  79. default:
  80. return -EINVAL;
  81. }
  82. }
  83. static const struct iio_info lpc32xx_adc_iio_info = {
  84. .read_raw = &lpc32xx_read_raw,
  85. };
  86. #define LPC32XX_ADC_CHANNEL_BASE(_index) \
  87. .type = IIO_VOLTAGE, \
  88. .indexed = 1, \
  89. .channel = _index, \
  90. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  91. .address = LPC32XXAD_IN * _index, \
  92. .scan_index = _index,
  93. #define LPC32XX_ADC_CHANNEL(_index) { \
  94. LPC32XX_ADC_CHANNEL_BASE(_index) \
  95. }
  96. #define LPC32XX_ADC_SCALE_CHANNEL(_index) { \
  97. LPC32XX_ADC_CHANNEL_BASE(_index) \
  98. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
  99. }
  100. static const struct iio_chan_spec lpc32xx_adc_iio_channels[] = {
  101. LPC32XX_ADC_CHANNEL(0),
  102. LPC32XX_ADC_CHANNEL(1),
  103. LPC32XX_ADC_CHANNEL(2),
  104. };
  105. static const struct iio_chan_spec lpc32xx_adc_iio_scale_channels[] = {
  106. LPC32XX_ADC_SCALE_CHANNEL(0),
  107. LPC32XX_ADC_SCALE_CHANNEL(1),
  108. LPC32XX_ADC_SCALE_CHANNEL(2),
  109. };
  110. static irqreturn_t lpc32xx_adc_isr(int irq, void *dev_id)
  111. {
  112. struct lpc32xx_adc_state *st = dev_id;
  113. /* Read value and clear irq */
  114. st->value = __raw_readl(LPC32XXAD_VALUE(st->adc_base)) &
  115. LPC32XXAD_VALUE_MASK;
  116. complete(&st->completion);
  117. return IRQ_HANDLED;
  118. }
  119. static int lpc32xx_adc_probe(struct platform_device *pdev)
  120. {
  121. struct lpc32xx_adc_state *st = NULL;
  122. struct resource *res;
  123. int retval = -ENODEV;
  124. struct iio_dev *iodev = NULL;
  125. int irq;
  126. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  127. if (!res) {
  128. dev_err(&pdev->dev, "failed to get platform I/O memory\n");
  129. return -ENXIO;
  130. }
  131. iodev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
  132. if (!iodev)
  133. return -ENOMEM;
  134. st = iio_priv(iodev);
  135. st->adc_base = devm_ioremap(&pdev->dev, res->start,
  136. resource_size(res));
  137. if (!st->adc_base) {
  138. dev_err(&pdev->dev, "failed mapping memory\n");
  139. return -EBUSY;
  140. }
  141. st->clk = devm_clk_get(&pdev->dev, NULL);
  142. if (IS_ERR(st->clk)) {
  143. dev_err(&pdev->dev, "failed getting clock\n");
  144. return PTR_ERR(st->clk);
  145. }
  146. irq = platform_get_irq(pdev, 0);
  147. if (irq <= 0)
  148. return -ENXIO;
  149. retval = devm_request_irq(&pdev->dev, irq, lpc32xx_adc_isr, 0,
  150. LPC32XXAD_NAME, st);
  151. if (retval < 0) {
  152. dev_err(&pdev->dev, "failed requesting interrupt\n");
  153. return retval;
  154. }
  155. st->vref = devm_regulator_get(&pdev->dev, "vref");
  156. if (IS_ERR(st->vref)) {
  157. iodev->channels = lpc32xx_adc_iio_channels;
  158. dev_info(&pdev->dev,
  159. "Missing vref regulator: No scaling available\n");
  160. } else {
  161. iodev->channels = lpc32xx_adc_iio_scale_channels;
  162. }
  163. platform_set_drvdata(pdev, iodev);
  164. init_completion(&st->completion);
  165. iodev->name = LPC32XXAD_NAME;
  166. iodev->info = &lpc32xx_adc_iio_info;
  167. iodev->modes = INDIO_DIRECT_MODE;
  168. iodev->num_channels = ARRAY_SIZE(lpc32xx_adc_iio_channels);
  169. retval = devm_iio_device_register(&pdev->dev, iodev);
  170. if (retval)
  171. return retval;
  172. dev_info(&pdev->dev, "LPC32XX ADC driver loaded, IRQ %d\n", irq);
  173. return 0;
  174. }
  175. static const struct of_device_id lpc32xx_adc_match[] = {
  176. { .compatible = "nxp,lpc3220-adc" },
  177. {},
  178. };
  179. MODULE_DEVICE_TABLE(of, lpc32xx_adc_match);
  180. static struct platform_driver lpc32xx_adc_driver = {
  181. .probe = lpc32xx_adc_probe,
  182. .driver = {
  183. .name = LPC32XXAD_NAME,
  184. .of_match_table = lpc32xx_adc_match,
  185. },
  186. };
  187. module_platform_driver(lpc32xx_adc_driver);
  188. MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
  189. MODULE_DESCRIPTION("LPC32XX ADC driver");
  190. MODULE_LICENSE("GPL");