intel_mrfld_adc.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * ADC driver for Basin Cove PMIC
  4. *
  5. * Copyright (C) 2012 Intel Corporation
  6. * Author: Bin Yang <bin.yang@intel.com>
  7. *
  8. * Rewritten for upstream by:
  9. * Vincent Pelletier <plr.vincent@gmail.com>
  10. * Andy Shevchenko <andriy.shevchenko@linux.intel.com>
  11. */
  12. #include <linux/bitops.h>
  13. #include <linux/completion.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/mfd/intel_soc_pmic.h>
  16. #include <linux/mfd/intel_soc_pmic_mrfld.h>
  17. #include <linux/module.h>
  18. #include <linux/mutex.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/regmap.h>
  21. #include <linux/iio/driver.h>
  22. #include <linux/iio/iio.h>
  23. #include <linux/iio/machine.h>
  24. #include <asm/unaligned.h>
  25. #define BCOVE_GPADCREQ 0xDC
  26. #define BCOVE_GPADCREQ_BUSY BIT(0)
  27. #define BCOVE_GPADCREQ_IRQEN BIT(1)
  28. #define BCOVE_ADCIRQ_ALL ( \
  29. BCOVE_ADCIRQ_BATTEMP | \
  30. BCOVE_ADCIRQ_SYSTEMP | \
  31. BCOVE_ADCIRQ_BATTID | \
  32. BCOVE_ADCIRQ_VIBATT | \
  33. BCOVE_ADCIRQ_CCTICK)
  34. #define BCOVE_ADC_TIMEOUT msecs_to_jiffies(1000)
  35. static const u8 mrfld_adc_requests[] = {
  36. BCOVE_ADCIRQ_VIBATT,
  37. BCOVE_ADCIRQ_BATTID,
  38. BCOVE_ADCIRQ_VIBATT,
  39. BCOVE_ADCIRQ_SYSTEMP,
  40. BCOVE_ADCIRQ_BATTEMP,
  41. BCOVE_ADCIRQ_BATTEMP,
  42. BCOVE_ADCIRQ_SYSTEMP,
  43. BCOVE_ADCIRQ_SYSTEMP,
  44. BCOVE_ADCIRQ_SYSTEMP,
  45. };
  46. struct mrfld_adc {
  47. struct regmap *regmap;
  48. struct completion completion;
  49. /* Lock to protect the IPC transfers */
  50. struct mutex lock;
  51. };
  52. static irqreturn_t mrfld_adc_thread_isr(int irq, void *data)
  53. {
  54. struct iio_dev *indio_dev = data;
  55. struct mrfld_adc *adc = iio_priv(indio_dev);
  56. complete(&adc->completion);
  57. return IRQ_HANDLED;
  58. }
  59. static int mrfld_adc_single_conv(struct iio_dev *indio_dev,
  60. struct iio_chan_spec const *chan,
  61. int *result)
  62. {
  63. struct mrfld_adc *adc = iio_priv(indio_dev);
  64. struct regmap *regmap = adc->regmap;
  65. unsigned int req;
  66. long timeout;
  67. __be16 value;
  68. int ret;
  69. reinit_completion(&adc->completion);
  70. regmap_update_bits(regmap, BCOVE_MADCIRQ, BCOVE_ADCIRQ_ALL, 0);
  71. regmap_update_bits(regmap, BCOVE_MIRQLVL1, BCOVE_LVL1_ADC, 0);
  72. ret = regmap_read_poll_timeout(regmap, BCOVE_GPADCREQ, req,
  73. !(req & BCOVE_GPADCREQ_BUSY),
  74. 2000, 1000000);
  75. if (ret)
  76. goto done;
  77. req = mrfld_adc_requests[chan->channel];
  78. ret = regmap_write(regmap, BCOVE_GPADCREQ, BCOVE_GPADCREQ_IRQEN | req);
  79. if (ret)
  80. goto done;
  81. timeout = wait_for_completion_interruptible_timeout(&adc->completion,
  82. BCOVE_ADC_TIMEOUT);
  83. if (timeout < 0) {
  84. ret = timeout;
  85. goto done;
  86. }
  87. if (timeout == 0) {
  88. ret = -ETIMEDOUT;
  89. goto done;
  90. }
  91. ret = regmap_bulk_read(regmap, chan->address, &value, sizeof(value));
  92. if (ret)
  93. goto done;
  94. *result = be16_to_cpu(value);
  95. ret = IIO_VAL_INT;
  96. done:
  97. regmap_update_bits(regmap, BCOVE_MIRQLVL1, BCOVE_LVL1_ADC, 0xff);
  98. regmap_update_bits(regmap, BCOVE_MADCIRQ, BCOVE_ADCIRQ_ALL, 0xff);
  99. return ret;
  100. }
  101. static int mrfld_adc_read_raw(struct iio_dev *indio_dev,
  102. struct iio_chan_spec const *chan,
  103. int *val, int *val2, long mask)
  104. {
  105. struct mrfld_adc *adc = iio_priv(indio_dev);
  106. int ret;
  107. switch (mask) {
  108. case IIO_CHAN_INFO_RAW:
  109. mutex_lock(&adc->lock);
  110. ret = mrfld_adc_single_conv(indio_dev, chan, val);
  111. mutex_unlock(&adc->lock);
  112. return ret;
  113. default:
  114. return -EINVAL;
  115. }
  116. }
  117. static const struct iio_info mrfld_adc_iio_info = {
  118. .read_raw = &mrfld_adc_read_raw,
  119. };
  120. #define BCOVE_ADC_CHANNEL(_type, _channel, _datasheet_name, _address) \
  121. { \
  122. .indexed = 1, \
  123. .type = _type, \
  124. .channel = _channel, \
  125. .address = _address, \
  126. .datasheet_name = _datasheet_name, \
  127. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  128. }
  129. static const struct iio_chan_spec mrfld_adc_channels[] = {
  130. BCOVE_ADC_CHANNEL(IIO_VOLTAGE, 0, "CH0", 0xE9),
  131. BCOVE_ADC_CHANNEL(IIO_RESISTANCE, 1, "CH1", 0xEB),
  132. BCOVE_ADC_CHANNEL(IIO_CURRENT, 2, "CH2", 0xED),
  133. BCOVE_ADC_CHANNEL(IIO_TEMP, 3, "CH3", 0xCC),
  134. BCOVE_ADC_CHANNEL(IIO_TEMP, 4, "CH4", 0xC8),
  135. BCOVE_ADC_CHANNEL(IIO_TEMP, 5, "CH5", 0xCA),
  136. BCOVE_ADC_CHANNEL(IIO_TEMP, 6, "CH6", 0xC2),
  137. BCOVE_ADC_CHANNEL(IIO_TEMP, 7, "CH7", 0xC4),
  138. BCOVE_ADC_CHANNEL(IIO_TEMP, 8, "CH8", 0xC6),
  139. };
  140. static struct iio_map iio_maps[] = {
  141. IIO_MAP("CH0", "bcove-battery", "VBATRSLT"),
  142. IIO_MAP("CH1", "bcove-battery", "BATTID"),
  143. IIO_MAP("CH2", "bcove-battery", "IBATRSLT"),
  144. IIO_MAP("CH3", "bcove-temp", "PMICTEMP"),
  145. IIO_MAP("CH4", "bcove-temp", "BATTEMP0"),
  146. IIO_MAP("CH5", "bcove-temp", "BATTEMP1"),
  147. IIO_MAP("CH6", "bcove-temp", "SYSTEMP0"),
  148. IIO_MAP("CH7", "bcove-temp", "SYSTEMP1"),
  149. IIO_MAP("CH8", "bcove-temp", "SYSTEMP2"),
  150. {}
  151. };
  152. static int mrfld_adc_probe(struct platform_device *pdev)
  153. {
  154. struct device *dev = &pdev->dev;
  155. struct intel_soc_pmic *pmic = dev_get_drvdata(dev->parent);
  156. struct iio_dev *indio_dev;
  157. struct mrfld_adc *adc;
  158. int irq;
  159. int ret;
  160. indio_dev = devm_iio_device_alloc(dev, sizeof(struct mrfld_adc));
  161. if (!indio_dev)
  162. return -ENOMEM;
  163. adc = iio_priv(indio_dev);
  164. mutex_init(&adc->lock);
  165. init_completion(&adc->completion);
  166. adc->regmap = pmic->regmap;
  167. irq = platform_get_irq(pdev, 0);
  168. if (irq < 0)
  169. return irq;
  170. ret = devm_request_threaded_irq(dev, irq, NULL, mrfld_adc_thread_isr,
  171. IRQF_ONESHOT | IRQF_SHARED, pdev->name,
  172. indio_dev);
  173. if (ret)
  174. return ret;
  175. platform_set_drvdata(pdev, indio_dev);
  176. indio_dev->name = pdev->name;
  177. indio_dev->channels = mrfld_adc_channels;
  178. indio_dev->num_channels = ARRAY_SIZE(mrfld_adc_channels);
  179. indio_dev->info = &mrfld_adc_iio_info;
  180. indio_dev->modes = INDIO_DIRECT_MODE;
  181. ret = iio_map_array_register(indio_dev, iio_maps);
  182. if (ret)
  183. return ret;
  184. ret = devm_iio_device_register(dev, indio_dev);
  185. if (ret < 0)
  186. goto err_array_unregister;
  187. return 0;
  188. err_array_unregister:
  189. iio_map_array_unregister(indio_dev);
  190. return ret;
  191. }
  192. static int mrfld_adc_remove(struct platform_device *pdev)
  193. {
  194. struct iio_dev *indio_dev = platform_get_drvdata(pdev);
  195. iio_map_array_unregister(indio_dev);
  196. return 0;
  197. }
  198. static const struct platform_device_id mrfld_adc_id_table[] = {
  199. { .name = "mrfld_bcove_adc" },
  200. {}
  201. };
  202. MODULE_DEVICE_TABLE(platform, mrfld_adc_id_table);
  203. static struct platform_driver mrfld_adc_driver = {
  204. .driver = {
  205. .name = "mrfld_bcove_adc",
  206. },
  207. .probe = mrfld_adc_probe,
  208. .remove = mrfld_adc_remove,
  209. .id_table = mrfld_adc_id_table,
  210. };
  211. module_platform_driver(mrfld_adc_driver);
  212. MODULE_AUTHOR("Bin Yang <bin.yang@intel.com>");
  213. MODULE_AUTHOR("Vincent Pelletier <plr.vincent@gmail.com>");
  214. MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
  215. MODULE_DESCRIPTION("ADC driver for Basin Cove PMIC");
  216. MODULE_LICENSE("GPL v2");