ingenic-adc.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * ADC driver for the Ingenic JZ47xx SoCs
  4. * Copyright (c) 2019 Artur Rojek <contact@artur-rojek.eu>
  5. *
  6. * based on drivers/mfd/jz4740-adc.c
  7. */
  8. #include <dt-bindings/iio/adc/ingenic,adc.h>
  9. #include <linux/clk.h>
  10. #include <linux/iio/buffer.h>
  11. #include <linux/iio/iio.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/iopoll.h>
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/mod_devicetable.h>
  18. #include <linux/mutex.h>
  19. #include <linux/platform_device.h>
  20. #define JZ_ADC_REG_ENABLE 0x00
  21. #define JZ_ADC_REG_CFG 0x04
  22. #define JZ_ADC_REG_CTRL 0x08
  23. #define JZ_ADC_REG_STATUS 0x0c
  24. #define JZ_ADC_REG_ADSAME 0x10
  25. #define JZ_ADC_REG_ADWAIT 0x14
  26. #define JZ_ADC_REG_ADTCH 0x18
  27. #define JZ_ADC_REG_ADBDAT 0x1c
  28. #define JZ_ADC_REG_ADSDAT 0x20
  29. #define JZ_ADC_REG_ADCMD 0x24
  30. #define JZ_ADC_REG_ADCLK 0x28
  31. #define JZ_ADC_REG_ENABLE_PD BIT(7)
  32. #define JZ_ADC_REG_CFG_AUX_MD (BIT(0) | BIT(1))
  33. #define JZ_ADC_REG_CFG_BAT_MD BIT(4)
  34. #define JZ_ADC_REG_CFG_SAMPLE_NUM(n) ((n) << 10)
  35. #define JZ_ADC_REG_CFG_PULL_UP(n) ((n) << 16)
  36. #define JZ_ADC_REG_CFG_CMD_SEL BIT(22)
  37. #define JZ_ADC_REG_CFG_TOUCH_OPS_MASK (BIT(31) | GENMASK(23, 10))
  38. #define JZ_ADC_REG_ADCLK_CLKDIV_LSB 0
  39. #define JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB 16
  40. #define JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB 8
  41. #define JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB 16
  42. #define JZ_ADC_REG_ADCMD_YNADC BIT(7)
  43. #define JZ_ADC_REG_ADCMD_YPADC BIT(8)
  44. #define JZ_ADC_REG_ADCMD_XNADC BIT(9)
  45. #define JZ_ADC_REG_ADCMD_XPADC BIT(10)
  46. #define JZ_ADC_REG_ADCMD_VREFPYP BIT(11)
  47. #define JZ_ADC_REG_ADCMD_VREFPXP BIT(12)
  48. #define JZ_ADC_REG_ADCMD_VREFPXN BIT(13)
  49. #define JZ_ADC_REG_ADCMD_VREFPAUX BIT(14)
  50. #define JZ_ADC_REG_ADCMD_VREFPVDD33 BIT(15)
  51. #define JZ_ADC_REG_ADCMD_VREFNYN BIT(16)
  52. #define JZ_ADC_REG_ADCMD_VREFNXP BIT(17)
  53. #define JZ_ADC_REG_ADCMD_VREFNXN BIT(18)
  54. #define JZ_ADC_REG_ADCMD_VREFAUX BIT(19)
  55. #define JZ_ADC_REG_ADCMD_YNGRU BIT(20)
  56. #define JZ_ADC_REG_ADCMD_XNGRU BIT(21)
  57. #define JZ_ADC_REG_ADCMD_XPGRU BIT(22)
  58. #define JZ_ADC_REG_ADCMD_YPSUP BIT(23)
  59. #define JZ_ADC_REG_ADCMD_XNSUP BIT(24)
  60. #define JZ_ADC_REG_ADCMD_XPSUP BIT(25)
  61. #define JZ_ADC_AUX_VREF 3300
  62. #define JZ_ADC_AUX_VREF_BITS 12
  63. #define JZ_ADC_BATTERY_LOW_VREF 2500
  64. #define JZ_ADC_BATTERY_LOW_VREF_BITS 12
  65. #define JZ4725B_ADC_BATTERY_HIGH_VREF 7500
  66. #define JZ4725B_ADC_BATTERY_HIGH_VREF_BITS 10
  67. #define JZ4740_ADC_BATTERY_HIGH_VREF (7500 * 0.986)
  68. #define JZ4740_ADC_BATTERY_HIGH_VREF_BITS 12
  69. #define JZ4770_ADC_BATTERY_VREF 1200
  70. #define JZ4770_ADC_BATTERY_VREF_BITS 12
  71. #define JZ_ADC_IRQ_AUX BIT(0)
  72. #define JZ_ADC_IRQ_BATTERY BIT(1)
  73. #define JZ_ADC_IRQ_TOUCH BIT(2)
  74. #define JZ_ADC_IRQ_PEN_DOWN BIT(3)
  75. #define JZ_ADC_IRQ_PEN_UP BIT(4)
  76. #define JZ_ADC_IRQ_PEN_DOWN_SLEEP BIT(5)
  77. #define JZ_ADC_IRQ_SLEEP BIT(7)
  78. struct ingenic_adc;
  79. struct ingenic_adc_soc_data {
  80. unsigned int battery_high_vref;
  81. unsigned int battery_high_vref_bits;
  82. const int *battery_raw_avail;
  83. size_t battery_raw_avail_size;
  84. const int *battery_scale_avail;
  85. size_t battery_scale_avail_size;
  86. unsigned int battery_vref_mode: 1;
  87. unsigned int has_aux2: 1;
  88. const struct iio_chan_spec *channels;
  89. unsigned int num_channels;
  90. int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc);
  91. };
  92. struct ingenic_adc {
  93. void __iomem *base;
  94. struct clk *clk;
  95. struct mutex lock;
  96. struct mutex aux_lock;
  97. const struct ingenic_adc_soc_data *soc_data;
  98. bool low_vref_mode;
  99. };
  100. static void ingenic_adc_set_adcmd(struct iio_dev *iio_dev, unsigned long mask)
  101. {
  102. struct ingenic_adc *adc = iio_priv(iio_dev);
  103. mutex_lock(&adc->lock);
  104. /* Init ADCMD */
  105. readl(adc->base + JZ_ADC_REG_ADCMD);
  106. if (mask & 0x3) {
  107. /* Second channel (INGENIC_ADC_TOUCH_YP): sample YP vs. GND */
  108. writel(JZ_ADC_REG_ADCMD_XNGRU
  109. | JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
  110. | JZ_ADC_REG_ADCMD_YPADC,
  111. adc->base + JZ_ADC_REG_ADCMD);
  112. /* First channel (INGENIC_ADC_TOUCH_XP): sample XP vs. GND */
  113. writel(JZ_ADC_REG_ADCMD_YNGRU
  114. | JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
  115. | JZ_ADC_REG_ADCMD_XPADC,
  116. adc->base + JZ_ADC_REG_ADCMD);
  117. }
  118. if (mask & 0xc) {
  119. /* Fourth channel (INGENIC_ADC_TOUCH_YN): sample YN vs. GND */
  120. writel(JZ_ADC_REG_ADCMD_XNGRU
  121. | JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
  122. | JZ_ADC_REG_ADCMD_YNADC,
  123. adc->base + JZ_ADC_REG_ADCMD);
  124. /* Third channel (INGENIC_ADC_TOUCH_XN): sample XN vs. GND */
  125. writel(JZ_ADC_REG_ADCMD_YNGRU
  126. | JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
  127. | JZ_ADC_REG_ADCMD_XNADC,
  128. adc->base + JZ_ADC_REG_ADCMD);
  129. }
  130. if (mask & 0x30) {
  131. /* Sixth channel (INGENIC_ADC_TOUCH_YD): sample YP vs. YN */
  132. writel(JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
  133. | JZ_ADC_REG_ADCMD_YPADC,
  134. adc->base + JZ_ADC_REG_ADCMD);
  135. /* Fifth channel (INGENIC_ADC_TOUCH_XD): sample XP vs. XN */
  136. writel(JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
  137. | JZ_ADC_REG_ADCMD_XPADC,
  138. adc->base + JZ_ADC_REG_ADCMD);
  139. }
  140. /* We're done */
  141. writel(0, adc->base + JZ_ADC_REG_ADCMD);
  142. mutex_unlock(&adc->lock);
  143. }
  144. static void ingenic_adc_set_config(struct ingenic_adc *adc,
  145. uint32_t mask,
  146. uint32_t val)
  147. {
  148. uint32_t cfg;
  149. mutex_lock(&adc->lock);
  150. cfg = readl(adc->base + JZ_ADC_REG_CFG) & ~mask;
  151. cfg |= val;
  152. writel(cfg, adc->base + JZ_ADC_REG_CFG);
  153. mutex_unlock(&adc->lock);
  154. }
  155. static void ingenic_adc_enable_unlocked(struct ingenic_adc *adc,
  156. int engine,
  157. bool enabled)
  158. {
  159. u8 val;
  160. val = readb(adc->base + JZ_ADC_REG_ENABLE);
  161. if (enabled)
  162. val |= BIT(engine);
  163. else
  164. val &= ~BIT(engine);
  165. writeb(val, adc->base + JZ_ADC_REG_ENABLE);
  166. }
  167. static void ingenic_adc_enable(struct ingenic_adc *adc,
  168. int engine,
  169. bool enabled)
  170. {
  171. mutex_lock(&adc->lock);
  172. ingenic_adc_enable_unlocked(adc, engine, enabled);
  173. mutex_unlock(&adc->lock);
  174. }
  175. static int ingenic_adc_capture(struct ingenic_adc *adc,
  176. int engine)
  177. {
  178. u32 cfg;
  179. u8 val;
  180. int ret;
  181. /*
  182. * Disable CMD_SEL temporarily, because it causes wrong VBAT readings,
  183. * probably due to the switch of VREF. We must keep the lock here to
  184. * avoid races with the buffer enable/disable functions.
  185. */
  186. mutex_lock(&adc->lock);
  187. cfg = readl(adc->base + JZ_ADC_REG_CFG);
  188. writel(cfg & ~JZ_ADC_REG_CFG_CMD_SEL, adc->base + JZ_ADC_REG_CFG);
  189. ingenic_adc_enable_unlocked(adc, engine, true);
  190. ret = readb_poll_timeout(adc->base + JZ_ADC_REG_ENABLE, val,
  191. !(val & BIT(engine)), 250, 1000);
  192. if (ret)
  193. ingenic_adc_enable_unlocked(adc, engine, false);
  194. writel(cfg, adc->base + JZ_ADC_REG_CFG);
  195. mutex_unlock(&adc->lock);
  196. return ret;
  197. }
  198. static int ingenic_adc_write_raw(struct iio_dev *iio_dev,
  199. struct iio_chan_spec const *chan,
  200. int val,
  201. int val2,
  202. long m)
  203. {
  204. struct ingenic_adc *adc = iio_priv(iio_dev);
  205. struct device *dev = iio_dev->dev.parent;
  206. int ret;
  207. switch (m) {
  208. case IIO_CHAN_INFO_SCALE:
  209. switch (chan->channel) {
  210. case INGENIC_ADC_BATTERY:
  211. if (!adc->soc_data->battery_vref_mode)
  212. return -EINVAL;
  213. ret = clk_enable(adc->clk);
  214. if (ret) {
  215. dev_err(dev, "Failed to enable clock: %d\n",
  216. ret);
  217. return ret;
  218. }
  219. if (val > JZ_ADC_BATTERY_LOW_VREF) {
  220. ingenic_adc_set_config(adc,
  221. JZ_ADC_REG_CFG_BAT_MD,
  222. 0);
  223. adc->low_vref_mode = false;
  224. } else {
  225. ingenic_adc_set_config(adc,
  226. JZ_ADC_REG_CFG_BAT_MD,
  227. JZ_ADC_REG_CFG_BAT_MD);
  228. adc->low_vref_mode = true;
  229. }
  230. clk_disable(adc->clk);
  231. return 0;
  232. default:
  233. return -EINVAL;
  234. }
  235. default:
  236. return -EINVAL;
  237. }
  238. }
  239. static const int jz4725b_adc_battery_raw_avail[] = {
  240. 0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
  241. };
  242. static const int jz4725b_adc_battery_scale_avail[] = {
  243. JZ4725B_ADC_BATTERY_HIGH_VREF, JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
  244. JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
  245. };
  246. static const int jz4740_adc_battery_raw_avail[] = {
  247. 0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
  248. };
  249. static const int jz4740_adc_battery_scale_avail[] = {
  250. JZ4740_ADC_BATTERY_HIGH_VREF, JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
  251. JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
  252. };
  253. static const int jz4770_adc_battery_raw_avail[] = {
  254. 0, 1, (1 << JZ4770_ADC_BATTERY_VREF_BITS) - 1,
  255. };
  256. static const int jz4770_adc_battery_scale_avail[] = {
  257. JZ4770_ADC_BATTERY_VREF, JZ4770_ADC_BATTERY_VREF_BITS,
  258. };
  259. static int jz4725b_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
  260. {
  261. struct clk *parent_clk;
  262. unsigned long parent_rate, rate;
  263. unsigned int div_main, div_10us;
  264. parent_clk = clk_get_parent(adc->clk);
  265. if (!parent_clk) {
  266. dev_err(dev, "ADC clock has no parent\n");
  267. return -ENODEV;
  268. }
  269. parent_rate = clk_get_rate(parent_clk);
  270. /*
  271. * The JZ4725B ADC works at 500 kHz to 8 MHz.
  272. * We pick the highest rate possible.
  273. * In practice we typically get 6 MHz, half of the 12 MHz EXT clock.
  274. */
  275. div_main = DIV_ROUND_UP(parent_rate, 8000000);
  276. div_main = clamp(div_main, 1u, 64u);
  277. rate = parent_rate / div_main;
  278. if (rate < 500000 || rate > 8000000) {
  279. dev_err(dev, "No valid divider for ADC main clock\n");
  280. return -EINVAL;
  281. }
  282. /* We also need a divider that produces a 10us clock. */
  283. div_10us = DIV_ROUND_UP(rate, 100000);
  284. writel(((div_10us - 1) << JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB) |
  285. (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
  286. adc->base + JZ_ADC_REG_ADCLK);
  287. return 0;
  288. }
  289. static int jz4770_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
  290. {
  291. struct clk *parent_clk;
  292. unsigned long parent_rate, rate;
  293. unsigned int div_main, div_ms, div_10us;
  294. parent_clk = clk_get_parent(adc->clk);
  295. if (!parent_clk) {
  296. dev_err(dev, "ADC clock has no parent\n");
  297. return -ENODEV;
  298. }
  299. parent_rate = clk_get_rate(parent_clk);
  300. /*
  301. * The JZ4770 ADC works at 20 kHz to 200 kHz.
  302. * We pick the highest rate possible.
  303. */
  304. div_main = DIV_ROUND_UP(parent_rate, 200000);
  305. div_main = clamp(div_main, 1u, 256u);
  306. rate = parent_rate / div_main;
  307. if (rate < 20000 || rate > 200000) {
  308. dev_err(dev, "No valid divider for ADC main clock\n");
  309. return -EINVAL;
  310. }
  311. /* We also need a divider that produces a 10us clock. */
  312. div_10us = DIV_ROUND_UP(rate, 10000);
  313. /* And another, which produces a 1ms clock. */
  314. div_ms = DIV_ROUND_UP(rate, 1000);
  315. writel(((div_ms - 1) << JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB) |
  316. ((div_10us - 1) << JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB) |
  317. (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
  318. adc->base + JZ_ADC_REG_ADCLK);
  319. return 0;
  320. }
  321. static const struct iio_chan_spec jz4740_channels[] = {
  322. {
  323. .extend_name = "aux",
  324. .type = IIO_VOLTAGE,
  325. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
  326. BIT(IIO_CHAN_INFO_SCALE),
  327. .indexed = 1,
  328. .channel = INGENIC_ADC_AUX,
  329. .scan_index = -1,
  330. },
  331. {
  332. .extend_name = "battery",
  333. .type = IIO_VOLTAGE,
  334. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
  335. BIT(IIO_CHAN_INFO_SCALE),
  336. .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) |
  337. BIT(IIO_CHAN_INFO_SCALE),
  338. .indexed = 1,
  339. .channel = INGENIC_ADC_BATTERY,
  340. .scan_index = -1,
  341. },
  342. };
  343. static const struct iio_chan_spec jz4770_channels[] = {
  344. {
  345. .type = IIO_VOLTAGE,
  346. .indexed = 1,
  347. .channel = INGENIC_ADC_TOUCH_XP,
  348. .scan_index = 0,
  349. .scan_type = {
  350. .sign = 'u',
  351. .realbits = 12,
  352. .storagebits = 16,
  353. },
  354. },
  355. {
  356. .type = IIO_VOLTAGE,
  357. .indexed = 1,
  358. .channel = INGENIC_ADC_TOUCH_YP,
  359. .scan_index = 1,
  360. .scan_type = {
  361. .sign = 'u',
  362. .realbits = 12,
  363. .storagebits = 16,
  364. },
  365. },
  366. {
  367. .type = IIO_VOLTAGE,
  368. .indexed = 1,
  369. .channel = INGENIC_ADC_TOUCH_XN,
  370. .scan_index = 2,
  371. .scan_type = {
  372. .sign = 'u',
  373. .realbits = 12,
  374. .storagebits = 16,
  375. },
  376. },
  377. {
  378. .type = IIO_VOLTAGE,
  379. .indexed = 1,
  380. .channel = INGENIC_ADC_TOUCH_YN,
  381. .scan_index = 3,
  382. .scan_type = {
  383. .sign = 'u',
  384. .realbits = 12,
  385. .storagebits = 16,
  386. },
  387. },
  388. {
  389. .type = IIO_VOLTAGE,
  390. .indexed = 1,
  391. .channel = INGENIC_ADC_TOUCH_XD,
  392. .scan_index = 4,
  393. .scan_type = {
  394. .sign = 'u',
  395. .realbits = 12,
  396. .storagebits = 16,
  397. },
  398. },
  399. {
  400. .type = IIO_VOLTAGE,
  401. .indexed = 1,
  402. .channel = INGENIC_ADC_TOUCH_YD,
  403. .scan_index = 5,
  404. .scan_type = {
  405. .sign = 'u',
  406. .realbits = 12,
  407. .storagebits = 16,
  408. },
  409. },
  410. {
  411. .extend_name = "aux",
  412. .type = IIO_VOLTAGE,
  413. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
  414. BIT(IIO_CHAN_INFO_SCALE),
  415. .indexed = 1,
  416. .channel = INGENIC_ADC_AUX,
  417. .scan_index = -1,
  418. },
  419. {
  420. .extend_name = "battery",
  421. .type = IIO_VOLTAGE,
  422. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
  423. BIT(IIO_CHAN_INFO_SCALE),
  424. .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) |
  425. BIT(IIO_CHAN_INFO_SCALE),
  426. .indexed = 1,
  427. .channel = INGENIC_ADC_BATTERY,
  428. .scan_index = -1,
  429. },
  430. {
  431. .extend_name = "aux2",
  432. .type = IIO_VOLTAGE,
  433. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
  434. BIT(IIO_CHAN_INFO_SCALE),
  435. .indexed = 1,
  436. .channel = INGENIC_ADC_AUX2,
  437. .scan_index = -1,
  438. },
  439. };
  440. static const struct ingenic_adc_soc_data jz4725b_adc_soc_data = {
  441. .battery_high_vref = JZ4725B_ADC_BATTERY_HIGH_VREF,
  442. .battery_high_vref_bits = JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
  443. .battery_raw_avail = jz4725b_adc_battery_raw_avail,
  444. .battery_raw_avail_size = ARRAY_SIZE(jz4725b_adc_battery_raw_avail),
  445. .battery_scale_avail = jz4725b_adc_battery_scale_avail,
  446. .battery_scale_avail_size = ARRAY_SIZE(jz4725b_adc_battery_scale_avail),
  447. .battery_vref_mode = true,
  448. .has_aux2 = false,
  449. .channels = jz4740_channels,
  450. .num_channels = ARRAY_SIZE(jz4740_channels),
  451. .init_clk_div = jz4725b_adc_init_clk_div,
  452. };
  453. static const struct ingenic_adc_soc_data jz4740_adc_soc_data = {
  454. .battery_high_vref = JZ4740_ADC_BATTERY_HIGH_VREF,
  455. .battery_high_vref_bits = JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
  456. .battery_raw_avail = jz4740_adc_battery_raw_avail,
  457. .battery_raw_avail_size = ARRAY_SIZE(jz4740_adc_battery_raw_avail),
  458. .battery_scale_avail = jz4740_adc_battery_scale_avail,
  459. .battery_scale_avail_size = ARRAY_SIZE(jz4740_adc_battery_scale_avail),
  460. .battery_vref_mode = true,
  461. .has_aux2 = false,
  462. .channels = jz4740_channels,
  463. .num_channels = ARRAY_SIZE(jz4740_channels),
  464. .init_clk_div = NULL, /* no ADCLK register on JZ4740 */
  465. };
  466. static const struct ingenic_adc_soc_data jz4770_adc_soc_data = {
  467. .battery_high_vref = JZ4770_ADC_BATTERY_VREF,
  468. .battery_high_vref_bits = JZ4770_ADC_BATTERY_VREF_BITS,
  469. .battery_raw_avail = jz4770_adc_battery_raw_avail,
  470. .battery_raw_avail_size = ARRAY_SIZE(jz4770_adc_battery_raw_avail),
  471. .battery_scale_avail = jz4770_adc_battery_scale_avail,
  472. .battery_scale_avail_size = ARRAY_SIZE(jz4770_adc_battery_scale_avail),
  473. .battery_vref_mode = false,
  474. .has_aux2 = true,
  475. .channels = jz4770_channels,
  476. .num_channels = ARRAY_SIZE(jz4770_channels),
  477. .init_clk_div = jz4770_adc_init_clk_div,
  478. };
  479. static int ingenic_adc_read_avail(struct iio_dev *iio_dev,
  480. struct iio_chan_spec const *chan,
  481. const int **vals,
  482. int *type,
  483. int *length,
  484. long m)
  485. {
  486. struct ingenic_adc *adc = iio_priv(iio_dev);
  487. switch (m) {
  488. case IIO_CHAN_INFO_RAW:
  489. *type = IIO_VAL_INT;
  490. *length = adc->soc_data->battery_raw_avail_size;
  491. *vals = adc->soc_data->battery_raw_avail;
  492. return IIO_AVAIL_RANGE;
  493. case IIO_CHAN_INFO_SCALE:
  494. *type = IIO_VAL_FRACTIONAL_LOG2;
  495. *length = adc->soc_data->battery_scale_avail_size;
  496. *vals = adc->soc_data->battery_scale_avail;
  497. return IIO_AVAIL_LIST;
  498. default:
  499. return -EINVAL;
  500. };
  501. }
  502. static int ingenic_adc_read_chan_info_raw(struct iio_dev *iio_dev,
  503. struct iio_chan_spec const *chan,
  504. int *val)
  505. {
  506. int bit, ret, engine = (chan->channel == INGENIC_ADC_BATTERY);
  507. struct ingenic_adc *adc = iio_priv(iio_dev);
  508. ret = clk_enable(adc->clk);
  509. if (ret) {
  510. dev_err(iio_dev->dev.parent, "Failed to enable clock: %d\n",
  511. ret);
  512. return ret;
  513. }
  514. /* We cannot sample AUX/AUX2 in parallel. */
  515. mutex_lock(&adc->aux_lock);
  516. if (adc->soc_data->has_aux2 && engine == 0) {
  517. bit = BIT(chan->channel == INGENIC_ADC_AUX2);
  518. ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_AUX_MD, bit);
  519. }
  520. ret = ingenic_adc_capture(adc, engine);
  521. if (ret)
  522. goto out;
  523. switch (chan->channel) {
  524. case INGENIC_ADC_AUX:
  525. case INGENIC_ADC_AUX2:
  526. *val = readw(adc->base + JZ_ADC_REG_ADSDAT);
  527. break;
  528. case INGENIC_ADC_BATTERY:
  529. *val = readw(adc->base + JZ_ADC_REG_ADBDAT);
  530. break;
  531. }
  532. ret = IIO_VAL_INT;
  533. out:
  534. mutex_unlock(&adc->aux_lock);
  535. clk_disable(adc->clk);
  536. return ret;
  537. }
  538. static int ingenic_adc_read_raw(struct iio_dev *iio_dev,
  539. struct iio_chan_spec const *chan,
  540. int *val,
  541. int *val2,
  542. long m)
  543. {
  544. struct ingenic_adc *adc = iio_priv(iio_dev);
  545. switch (m) {
  546. case IIO_CHAN_INFO_RAW:
  547. return ingenic_adc_read_chan_info_raw(iio_dev, chan, val);
  548. case IIO_CHAN_INFO_SCALE:
  549. switch (chan->channel) {
  550. case INGENIC_ADC_AUX:
  551. case INGENIC_ADC_AUX2:
  552. *val = JZ_ADC_AUX_VREF;
  553. *val2 = JZ_ADC_AUX_VREF_BITS;
  554. break;
  555. case INGENIC_ADC_BATTERY:
  556. if (adc->low_vref_mode) {
  557. *val = JZ_ADC_BATTERY_LOW_VREF;
  558. *val2 = JZ_ADC_BATTERY_LOW_VREF_BITS;
  559. } else {
  560. *val = adc->soc_data->battery_high_vref;
  561. *val2 = adc->soc_data->battery_high_vref_bits;
  562. }
  563. break;
  564. }
  565. return IIO_VAL_FRACTIONAL_LOG2;
  566. default:
  567. return -EINVAL;
  568. }
  569. }
  570. static int ingenic_adc_of_xlate(struct iio_dev *iio_dev,
  571. const struct of_phandle_args *iiospec)
  572. {
  573. int i;
  574. if (!iiospec->args_count)
  575. return -EINVAL;
  576. for (i = 0; i < iio_dev->num_channels; ++i)
  577. if (iio_dev->channels[i].channel == iiospec->args[0])
  578. return i;
  579. return -EINVAL;
  580. }
  581. static void ingenic_adc_clk_cleanup(void *data)
  582. {
  583. clk_unprepare(data);
  584. }
  585. static const struct iio_info ingenic_adc_info = {
  586. .write_raw = ingenic_adc_write_raw,
  587. .read_raw = ingenic_adc_read_raw,
  588. .read_avail = ingenic_adc_read_avail,
  589. .of_xlate = ingenic_adc_of_xlate,
  590. };
  591. static int ingenic_adc_buffer_enable(struct iio_dev *iio_dev)
  592. {
  593. struct ingenic_adc *adc = iio_priv(iio_dev);
  594. int ret;
  595. ret = clk_enable(adc->clk);
  596. if (ret) {
  597. dev_err(iio_dev->dev.parent, "Failed to enable clock: %d\n",
  598. ret);
  599. return ret;
  600. }
  601. /* It takes significant time for the touchscreen hw to stabilize. */
  602. msleep(50);
  603. ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_TOUCH_OPS_MASK,
  604. JZ_ADC_REG_CFG_SAMPLE_NUM(4) |
  605. JZ_ADC_REG_CFG_PULL_UP(4));
  606. writew(80, adc->base + JZ_ADC_REG_ADWAIT);
  607. writew(2, adc->base + JZ_ADC_REG_ADSAME);
  608. writeb((u8)~JZ_ADC_IRQ_TOUCH, adc->base + JZ_ADC_REG_CTRL);
  609. writel(0, adc->base + JZ_ADC_REG_ADTCH);
  610. ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_CMD_SEL,
  611. JZ_ADC_REG_CFG_CMD_SEL);
  612. ingenic_adc_set_adcmd(iio_dev, iio_dev->active_scan_mask[0]);
  613. ingenic_adc_enable(adc, 2, true);
  614. return 0;
  615. }
  616. static int ingenic_adc_buffer_disable(struct iio_dev *iio_dev)
  617. {
  618. struct ingenic_adc *adc = iio_priv(iio_dev);
  619. ingenic_adc_enable(adc, 2, false);
  620. ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_CMD_SEL, 0);
  621. writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
  622. writeb(0xff, adc->base + JZ_ADC_REG_STATUS);
  623. ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_TOUCH_OPS_MASK, 0);
  624. writew(0, adc->base + JZ_ADC_REG_ADSAME);
  625. writew(0, adc->base + JZ_ADC_REG_ADWAIT);
  626. clk_disable(adc->clk);
  627. return 0;
  628. }
  629. static const struct iio_buffer_setup_ops ingenic_buffer_setup_ops = {
  630. .postenable = &ingenic_adc_buffer_enable,
  631. .predisable = &ingenic_adc_buffer_disable
  632. };
  633. static irqreturn_t ingenic_adc_irq(int irq, void *data)
  634. {
  635. struct iio_dev *iio_dev = data;
  636. struct ingenic_adc *adc = iio_priv(iio_dev);
  637. unsigned long mask = iio_dev->active_scan_mask[0];
  638. unsigned int i;
  639. u32 tdat[3];
  640. for (i = 0; i < ARRAY_SIZE(tdat); mask >>= 2, i++) {
  641. if (mask & 0x3)
  642. tdat[i] = readl(adc->base + JZ_ADC_REG_ADTCH);
  643. else
  644. tdat[i] = 0;
  645. }
  646. iio_push_to_buffers(iio_dev, tdat);
  647. writeb(JZ_ADC_IRQ_TOUCH, adc->base + JZ_ADC_REG_STATUS);
  648. return IRQ_HANDLED;
  649. }
  650. static int ingenic_adc_probe(struct platform_device *pdev)
  651. {
  652. struct device *dev = &pdev->dev;
  653. struct iio_dev *iio_dev;
  654. struct ingenic_adc *adc;
  655. const struct ingenic_adc_soc_data *soc_data;
  656. int irq, ret;
  657. soc_data = device_get_match_data(dev);
  658. if (!soc_data)
  659. return -EINVAL;
  660. iio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
  661. if (!iio_dev)
  662. return -ENOMEM;
  663. adc = iio_priv(iio_dev);
  664. mutex_init(&adc->lock);
  665. mutex_init(&adc->aux_lock);
  666. adc->soc_data = soc_data;
  667. irq = platform_get_irq(pdev, 0);
  668. if (irq < 0)
  669. return irq;
  670. ret = devm_request_irq(dev, irq, ingenic_adc_irq, 0,
  671. dev_name(dev), iio_dev);
  672. if (ret < 0) {
  673. dev_err(dev, "Failed to request irq: %d\n", ret);
  674. return ret;
  675. }
  676. adc->base = devm_platform_ioremap_resource(pdev, 0);
  677. if (IS_ERR(adc->base))
  678. return PTR_ERR(adc->base);
  679. adc->clk = devm_clk_get(dev, "adc");
  680. if (IS_ERR(adc->clk)) {
  681. dev_err(dev, "Unable to get clock\n");
  682. return PTR_ERR(adc->clk);
  683. }
  684. ret = clk_prepare_enable(adc->clk);
  685. if (ret) {
  686. dev_err(dev, "Failed to enable clock\n");
  687. return ret;
  688. }
  689. /* Set clock dividers. */
  690. if (soc_data->init_clk_div) {
  691. ret = soc_data->init_clk_div(dev, adc);
  692. if (ret) {
  693. clk_disable_unprepare(adc->clk);
  694. return ret;
  695. }
  696. }
  697. /* Put hardware in a known passive state. */
  698. writeb(0x00, adc->base + JZ_ADC_REG_ENABLE);
  699. writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
  700. usleep_range(2000, 3000); /* Must wait at least 2ms. */
  701. clk_disable(adc->clk);
  702. ret = devm_add_action_or_reset(dev, ingenic_adc_clk_cleanup, adc->clk);
  703. if (ret) {
  704. dev_err(dev, "Unable to add action\n");
  705. return ret;
  706. }
  707. iio_dev->name = "jz-adc";
  708. iio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
  709. iio_dev->setup_ops = &ingenic_buffer_setup_ops;
  710. iio_dev->channels = soc_data->channels;
  711. iio_dev->num_channels = soc_data->num_channels;
  712. iio_dev->info = &ingenic_adc_info;
  713. ret = devm_iio_device_register(dev, iio_dev);
  714. if (ret)
  715. dev_err(dev, "Unable to register IIO device\n");
  716. return ret;
  717. }
  718. static const struct of_device_id ingenic_adc_of_match[] = {
  719. { .compatible = "ingenic,jz4725b-adc", .data = &jz4725b_adc_soc_data, },
  720. { .compatible = "ingenic,jz4740-adc", .data = &jz4740_adc_soc_data, },
  721. { .compatible = "ingenic,jz4770-adc", .data = &jz4770_adc_soc_data, },
  722. { },
  723. };
  724. MODULE_DEVICE_TABLE(of, ingenic_adc_of_match);
  725. static struct platform_driver ingenic_adc_driver = {
  726. .driver = {
  727. .name = "ingenic-adc",
  728. .of_match_table = ingenic_adc_of_match,
  729. },
  730. .probe = ingenic_adc_probe,
  731. };
  732. module_platform_driver(ingenic_adc_driver);
  733. MODULE_LICENSE("GPL v2");