ina2xx-adc.c 28 KB

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  1. /*
  2. * INA2XX Current and Power Monitors
  3. *
  4. * Copyright 2015 Baylibre SAS.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Based on linux/drivers/iio/adc/ad7291.c
  11. * Copyright 2010-2011 Analog Devices Inc.
  12. *
  13. * Based on linux/drivers/hwmon/ina2xx.c
  14. * Copyright 2012 Lothar Felten <l-felten@ti.com>
  15. *
  16. * Licensed under the GPL-2 or later.
  17. *
  18. * IIO driver for INA219-220-226-230-231
  19. *
  20. * Configurable 7-bit I2C slave address from 0x40 to 0x4F
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/i2c.h>
  24. #include <linux/iio/iio.h>
  25. #include <linux/iio/buffer.h>
  26. #include <linux/iio/kfifo_buf.h>
  27. #include <linux/iio/sysfs.h>
  28. #include <linux/kthread.h>
  29. #include <linux/module.h>
  30. #include <linux/of_device.h>
  31. #include <linux/regmap.h>
  32. #include <linux/sched/task.h>
  33. #include <linux/util_macros.h>
  34. #include <linux/platform_data/ina2xx.h>
  35. /* INA2XX registers definition */
  36. #define INA2XX_CONFIG 0x00
  37. #define INA2XX_SHUNT_VOLTAGE 0x01 /* readonly */
  38. #define INA2XX_BUS_VOLTAGE 0x02 /* readonly */
  39. #define INA2XX_POWER 0x03 /* readonly */
  40. #define INA2XX_CURRENT 0x04 /* readonly */
  41. #define INA2XX_CALIBRATION 0x05
  42. #define INA226_MASK_ENABLE 0x06
  43. #define INA226_CVRF BIT(3)
  44. #define INA2XX_MAX_REGISTERS 8
  45. /* settings - depend on use case */
  46. #define INA219_CONFIG_DEFAULT 0x399F /* PGA=1/8, BRNG=32V */
  47. #define INA219_DEFAULT_IT 532
  48. #define INA219_DEFAULT_BRNG 1 /* 32V */
  49. #define INA219_DEFAULT_PGA 125 /* 1000/8 */
  50. #define INA226_CONFIG_DEFAULT 0x4327
  51. #define INA226_DEFAULT_AVG 4
  52. #define INA226_DEFAULT_IT 1110
  53. #define INA2XX_RSHUNT_DEFAULT 10000
  54. /*
  55. * bit masks for reading the settings in the configuration register
  56. * FIXME: use regmap_fields.
  57. */
  58. #define INA2XX_MODE_MASK GENMASK(3, 0)
  59. /* Gain for VShunt: 1/8 (default), 1/4, 1/2, 1 */
  60. #define INA219_PGA_MASK GENMASK(12, 11)
  61. #define INA219_SHIFT_PGA(val) ((val) << 11)
  62. /* VBus range: 32V (default), 16V */
  63. #define INA219_BRNG_MASK BIT(13)
  64. #define INA219_SHIFT_BRNG(val) ((val) << 13)
  65. /* Averaging for VBus/VShunt/Power */
  66. #define INA226_AVG_MASK GENMASK(11, 9)
  67. #define INA226_SHIFT_AVG(val) ((val) << 9)
  68. /* Integration time for VBus */
  69. #define INA219_ITB_MASK GENMASK(10, 7)
  70. #define INA219_SHIFT_ITB(val) ((val) << 7)
  71. #define INA226_ITB_MASK GENMASK(8, 6)
  72. #define INA226_SHIFT_ITB(val) ((val) << 6)
  73. /* Integration time for VShunt */
  74. #define INA219_ITS_MASK GENMASK(6, 3)
  75. #define INA219_SHIFT_ITS(val) ((val) << 3)
  76. #define INA226_ITS_MASK GENMASK(5, 3)
  77. #define INA226_SHIFT_ITS(val) ((val) << 3)
  78. /* INA219 Bus voltage register, low bits are flags */
  79. #define INA219_OVF BIT(0)
  80. #define INA219_CNVR BIT(1)
  81. #define INA219_BUS_VOLTAGE_SHIFT 3
  82. /* Cosmetic macro giving the sampling period for a full P=UxI cycle */
  83. #define SAMPLING_PERIOD(c) ((c->int_time_vbus + c->int_time_vshunt) \
  84. * c->avg)
  85. static bool ina2xx_is_writeable_reg(struct device *dev, unsigned int reg)
  86. {
  87. return (reg == INA2XX_CONFIG) || (reg > INA2XX_CURRENT);
  88. }
  89. static bool ina2xx_is_volatile_reg(struct device *dev, unsigned int reg)
  90. {
  91. return (reg != INA2XX_CONFIG);
  92. }
  93. static inline bool is_signed_reg(unsigned int reg)
  94. {
  95. return (reg == INA2XX_SHUNT_VOLTAGE) || (reg == INA2XX_CURRENT);
  96. }
  97. static const struct regmap_config ina2xx_regmap_config = {
  98. .reg_bits = 8,
  99. .val_bits = 16,
  100. .max_register = INA2XX_MAX_REGISTERS,
  101. .writeable_reg = ina2xx_is_writeable_reg,
  102. .volatile_reg = ina2xx_is_volatile_reg,
  103. };
  104. enum ina2xx_ids { ina219, ina226 };
  105. struct ina2xx_config {
  106. u16 config_default;
  107. int calibration_value;
  108. int shunt_voltage_lsb; /* nV */
  109. int bus_voltage_shift; /* position of lsb */
  110. int bus_voltage_lsb; /* uV */
  111. /* fixed relation between current and power lsb, uW/uA */
  112. int power_lsb_factor;
  113. enum ina2xx_ids chip_id;
  114. };
  115. struct ina2xx_chip_info {
  116. struct regmap *regmap;
  117. struct task_struct *task;
  118. const struct ina2xx_config *config;
  119. struct mutex state_lock;
  120. unsigned int shunt_resistor_uohm;
  121. int avg;
  122. int int_time_vbus; /* Bus voltage integration time uS */
  123. int int_time_vshunt; /* Shunt voltage integration time uS */
  124. int range_vbus; /* Bus voltage maximum in V */
  125. int pga_gain_vshunt; /* Shunt voltage PGA gain */
  126. bool allow_async_readout;
  127. /* data buffer needs space for channel data and timestamp */
  128. struct {
  129. u16 chan[4];
  130. u64 ts __aligned(8);
  131. } scan;
  132. };
  133. static const struct ina2xx_config ina2xx_config[] = {
  134. [ina219] = {
  135. .config_default = INA219_CONFIG_DEFAULT,
  136. .calibration_value = 4096,
  137. .shunt_voltage_lsb = 10000,
  138. .bus_voltage_shift = INA219_BUS_VOLTAGE_SHIFT,
  139. .bus_voltage_lsb = 4000,
  140. .power_lsb_factor = 20,
  141. .chip_id = ina219,
  142. },
  143. [ina226] = {
  144. .config_default = INA226_CONFIG_DEFAULT,
  145. .calibration_value = 2048,
  146. .shunt_voltage_lsb = 2500,
  147. .bus_voltage_shift = 0,
  148. .bus_voltage_lsb = 1250,
  149. .power_lsb_factor = 25,
  150. .chip_id = ina226,
  151. },
  152. };
  153. static int ina2xx_read_raw(struct iio_dev *indio_dev,
  154. struct iio_chan_spec const *chan,
  155. int *val, int *val2, long mask)
  156. {
  157. int ret;
  158. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  159. unsigned int regval;
  160. switch (mask) {
  161. case IIO_CHAN_INFO_RAW:
  162. ret = regmap_read(chip->regmap, chan->address, &regval);
  163. if (ret)
  164. return ret;
  165. if (is_signed_reg(chan->address))
  166. *val = (s16) regval;
  167. else
  168. *val = regval;
  169. if (chan->address == INA2XX_BUS_VOLTAGE)
  170. *val >>= chip->config->bus_voltage_shift;
  171. return IIO_VAL_INT;
  172. case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
  173. *val = chip->avg;
  174. return IIO_VAL_INT;
  175. case IIO_CHAN_INFO_INT_TIME:
  176. *val = 0;
  177. if (chan->address == INA2XX_SHUNT_VOLTAGE)
  178. *val2 = chip->int_time_vshunt;
  179. else
  180. *val2 = chip->int_time_vbus;
  181. return IIO_VAL_INT_PLUS_MICRO;
  182. case IIO_CHAN_INFO_SAMP_FREQ:
  183. /*
  184. * Sample freq is read only, it is a consequence of
  185. * 1/AVG*(CT_bus+CT_shunt).
  186. */
  187. *val = DIV_ROUND_CLOSEST(1000000, SAMPLING_PERIOD(chip));
  188. return IIO_VAL_INT;
  189. case IIO_CHAN_INFO_SCALE:
  190. switch (chan->address) {
  191. case INA2XX_SHUNT_VOLTAGE:
  192. /* processed (mV) = raw * lsb(nV) / 1000000 */
  193. *val = chip->config->shunt_voltage_lsb;
  194. *val2 = 1000000;
  195. return IIO_VAL_FRACTIONAL;
  196. case INA2XX_BUS_VOLTAGE:
  197. /* processed (mV) = raw * lsb (uV) / 1000 */
  198. *val = chip->config->bus_voltage_lsb;
  199. *val2 = 1000;
  200. return IIO_VAL_FRACTIONAL;
  201. case INA2XX_CURRENT:
  202. /*
  203. * processed (mA) = raw * current_lsb (mA)
  204. * current_lsb (mA) = shunt_voltage_lsb (nV) /
  205. * shunt_resistor (uOhm)
  206. */
  207. *val = chip->config->shunt_voltage_lsb;
  208. *val2 = chip->shunt_resistor_uohm;
  209. return IIO_VAL_FRACTIONAL;
  210. case INA2XX_POWER:
  211. /*
  212. * processed (mW) = raw * power_lsb (mW)
  213. * power_lsb (mW) = power_lsb_factor (mW/mA) *
  214. * current_lsb (mA)
  215. */
  216. *val = chip->config->power_lsb_factor *
  217. chip->config->shunt_voltage_lsb;
  218. *val2 = chip->shunt_resistor_uohm;
  219. return IIO_VAL_FRACTIONAL;
  220. }
  221. return -EINVAL;
  222. case IIO_CHAN_INFO_HARDWAREGAIN:
  223. switch (chan->address) {
  224. case INA2XX_SHUNT_VOLTAGE:
  225. *val = chip->pga_gain_vshunt;
  226. *val2 = 1000;
  227. return IIO_VAL_FRACTIONAL;
  228. case INA2XX_BUS_VOLTAGE:
  229. *val = chip->range_vbus == 32 ? 1 : 2;
  230. return IIO_VAL_INT;
  231. }
  232. return -EINVAL;
  233. }
  234. return -EINVAL;
  235. }
  236. /*
  237. * Available averaging rates for ina226. The indices correspond with
  238. * the bit values expected by the chip (according to the ina226 datasheet,
  239. * table 3 AVG bit settings, found at
  240. * https://www.ti.com/lit/ds/symlink/ina226.pdf.
  241. */
  242. static const int ina226_avg_tab[] = { 1, 4, 16, 64, 128, 256, 512, 1024 };
  243. static int ina226_set_average(struct ina2xx_chip_info *chip, unsigned int val,
  244. unsigned int *config)
  245. {
  246. int bits;
  247. if (val > 1024 || val < 1)
  248. return -EINVAL;
  249. bits = find_closest(val, ina226_avg_tab,
  250. ARRAY_SIZE(ina226_avg_tab));
  251. chip->avg = ina226_avg_tab[bits];
  252. *config &= ~INA226_AVG_MASK;
  253. *config |= INA226_SHIFT_AVG(bits) & INA226_AVG_MASK;
  254. return 0;
  255. }
  256. /* Conversion times in uS */
  257. static const int ina226_conv_time_tab[] = { 140, 204, 332, 588, 1100,
  258. 2116, 4156, 8244 };
  259. static int ina226_set_int_time_vbus(struct ina2xx_chip_info *chip,
  260. unsigned int val_us, unsigned int *config)
  261. {
  262. int bits;
  263. if (val_us > 8244 || val_us < 140)
  264. return -EINVAL;
  265. bits = find_closest(val_us, ina226_conv_time_tab,
  266. ARRAY_SIZE(ina226_conv_time_tab));
  267. chip->int_time_vbus = ina226_conv_time_tab[bits];
  268. *config &= ~INA226_ITB_MASK;
  269. *config |= INA226_SHIFT_ITB(bits) & INA226_ITB_MASK;
  270. return 0;
  271. }
  272. static int ina226_set_int_time_vshunt(struct ina2xx_chip_info *chip,
  273. unsigned int val_us, unsigned int *config)
  274. {
  275. int bits;
  276. if (val_us > 8244 || val_us < 140)
  277. return -EINVAL;
  278. bits = find_closest(val_us, ina226_conv_time_tab,
  279. ARRAY_SIZE(ina226_conv_time_tab));
  280. chip->int_time_vshunt = ina226_conv_time_tab[bits];
  281. *config &= ~INA226_ITS_MASK;
  282. *config |= INA226_SHIFT_ITS(bits) & INA226_ITS_MASK;
  283. return 0;
  284. }
  285. /* Conversion times in uS. */
  286. static const int ina219_conv_time_tab_subsample[] = { 84, 148, 276, 532 };
  287. static const int ina219_conv_time_tab_average[] = { 532, 1060, 2130, 4260,
  288. 8510, 17020, 34050, 68100};
  289. static int ina219_lookup_int_time(unsigned int *val_us, int *bits)
  290. {
  291. if (*val_us > 68100 || *val_us < 84)
  292. return -EINVAL;
  293. if (*val_us <= 532) {
  294. *bits = find_closest(*val_us, ina219_conv_time_tab_subsample,
  295. ARRAY_SIZE(ina219_conv_time_tab_subsample));
  296. *val_us = ina219_conv_time_tab_subsample[*bits];
  297. } else {
  298. *bits = find_closest(*val_us, ina219_conv_time_tab_average,
  299. ARRAY_SIZE(ina219_conv_time_tab_average));
  300. *val_us = ina219_conv_time_tab_average[*bits];
  301. *bits |= 0x8;
  302. }
  303. return 0;
  304. }
  305. static int ina219_set_int_time_vbus(struct ina2xx_chip_info *chip,
  306. unsigned int val_us, unsigned int *config)
  307. {
  308. int bits, ret;
  309. unsigned int val_us_best = val_us;
  310. ret = ina219_lookup_int_time(&val_us_best, &bits);
  311. if (ret)
  312. return ret;
  313. chip->int_time_vbus = val_us_best;
  314. *config &= ~INA219_ITB_MASK;
  315. *config |= INA219_SHIFT_ITB(bits) & INA219_ITB_MASK;
  316. return 0;
  317. }
  318. static int ina219_set_int_time_vshunt(struct ina2xx_chip_info *chip,
  319. unsigned int val_us, unsigned int *config)
  320. {
  321. int bits, ret;
  322. unsigned int val_us_best = val_us;
  323. ret = ina219_lookup_int_time(&val_us_best, &bits);
  324. if (ret)
  325. return ret;
  326. chip->int_time_vshunt = val_us_best;
  327. *config &= ~INA219_ITS_MASK;
  328. *config |= INA219_SHIFT_ITS(bits) & INA219_ITS_MASK;
  329. return 0;
  330. }
  331. static const int ina219_vbus_range_tab[] = { 1, 2 };
  332. static int ina219_set_vbus_range_denom(struct ina2xx_chip_info *chip,
  333. unsigned int range,
  334. unsigned int *config)
  335. {
  336. if (range == 1)
  337. chip->range_vbus = 32;
  338. else if (range == 2)
  339. chip->range_vbus = 16;
  340. else
  341. return -EINVAL;
  342. *config &= ~INA219_BRNG_MASK;
  343. *config |= INA219_SHIFT_BRNG(range == 1 ? 1 : 0) & INA219_BRNG_MASK;
  344. return 0;
  345. }
  346. static const int ina219_vshunt_gain_tab[] = { 125, 250, 500, 1000 };
  347. static const int ina219_vshunt_gain_frac[] = {
  348. 125, 1000, 250, 1000, 500, 1000, 1000, 1000 };
  349. static int ina219_set_vshunt_pga_gain(struct ina2xx_chip_info *chip,
  350. unsigned int gain,
  351. unsigned int *config)
  352. {
  353. int bits;
  354. if (gain < 125 || gain > 1000)
  355. return -EINVAL;
  356. bits = find_closest(gain, ina219_vshunt_gain_tab,
  357. ARRAY_SIZE(ina219_vshunt_gain_tab));
  358. chip->pga_gain_vshunt = ina219_vshunt_gain_tab[bits];
  359. bits = 3 - bits;
  360. *config &= ~INA219_PGA_MASK;
  361. *config |= INA219_SHIFT_PGA(bits) & INA219_PGA_MASK;
  362. return 0;
  363. }
  364. static int ina2xx_read_avail(struct iio_dev *indio_dev,
  365. struct iio_chan_spec const *chan,
  366. const int **vals, int *type, int *length,
  367. long mask)
  368. {
  369. switch (mask) {
  370. case IIO_CHAN_INFO_HARDWAREGAIN:
  371. switch (chan->address) {
  372. case INA2XX_SHUNT_VOLTAGE:
  373. *type = IIO_VAL_FRACTIONAL;
  374. *length = sizeof(ina219_vshunt_gain_frac) / sizeof(int);
  375. *vals = ina219_vshunt_gain_frac;
  376. return IIO_AVAIL_LIST;
  377. case INA2XX_BUS_VOLTAGE:
  378. *type = IIO_VAL_INT;
  379. *length = sizeof(ina219_vbus_range_tab) / sizeof(int);
  380. *vals = ina219_vbus_range_tab;
  381. return IIO_AVAIL_LIST;
  382. }
  383. }
  384. return -EINVAL;
  385. }
  386. static int ina2xx_write_raw(struct iio_dev *indio_dev,
  387. struct iio_chan_spec const *chan,
  388. int val, int val2, long mask)
  389. {
  390. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  391. unsigned int config, tmp;
  392. int ret;
  393. if (iio_buffer_enabled(indio_dev))
  394. return -EBUSY;
  395. mutex_lock(&chip->state_lock);
  396. ret = regmap_read(chip->regmap, INA2XX_CONFIG, &config);
  397. if (ret)
  398. goto err;
  399. tmp = config;
  400. switch (mask) {
  401. case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
  402. ret = ina226_set_average(chip, val, &tmp);
  403. break;
  404. case IIO_CHAN_INFO_INT_TIME:
  405. if (chip->config->chip_id == ina226) {
  406. if (chan->address == INA2XX_SHUNT_VOLTAGE)
  407. ret = ina226_set_int_time_vshunt(chip, val2,
  408. &tmp);
  409. else
  410. ret = ina226_set_int_time_vbus(chip, val2,
  411. &tmp);
  412. } else {
  413. if (chan->address == INA2XX_SHUNT_VOLTAGE)
  414. ret = ina219_set_int_time_vshunt(chip, val2,
  415. &tmp);
  416. else
  417. ret = ina219_set_int_time_vbus(chip, val2,
  418. &tmp);
  419. }
  420. break;
  421. case IIO_CHAN_INFO_HARDWAREGAIN:
  422. if (chan->address == INA2XX_SHUNT_VOLTAGE)
  423. ret = ina219_set_vshunt_pga_gain(chip, val * 1000 +
  424. val2 / 1000, &tmp);
  425. else
  426. ret = ina219_set_vbus_range_denom(chip, val, &tmp);
  427. break;
  428. default:
  429. ret = -EINVAL;
  430. }
  431. if (!ret && (tmp != config))
  432. ret = regmap_write(chip->regmap, INA2XX_CONFIG, tmp);
  433. err:
  434. mutex_unlock(&chip->state_lock);
  435. return ret;
  436. }
  437. static ssize_t ina2xx_allow_async_readout_show(struct device *dev,
  438. struct device_attribute *attr,
  439. char *buf)
  440. {
  441. struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
  442. return sprintf(buf, "%d\n", chip->allow_async_readout);
  443. }
  444. static ssize_t ina2xx_allow_async_readout_store(struct device *dev,
  445. struct device_attribute *attr,
  446. const char *buf, size_t len)
  447. {
  448. struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
  449. bool val;
  450. int ret;
  451. ret = strtobool((const char *) buf, &val);
  452. if (ret)
  453. return ret;
  454. chip->allow_async_readout = val;
  455. return len;
  456. }
  457. /*
  458. * Calibration register is set to the best value, which eliminates
  459. * truncation errors on calculating current register in hardware.
  460. * According to datasheet (INA 226: eq. 3, INA219: eq. 4) the best values
  461. * are 2048 for ina226 and 4096 for ina219. They are hardcoded as
  462. * calibration_value.
  463. */
  464. static int ina2xx_set_calibration(struct ina2xx_chip_info *chip)
  465. {
  466. return regmap_write(chip->regmap, INA2XX_CALIBRATION,
  467. chip->config->calibration_value);
  468. }
  469. static int set_shunt_resistor(struct ina2xx_chip_info *chip, unsigned int val)
  470. {
  471. if (val == 0 || val > INT_MAX)
  472. return -EINVAL;
  473. chip->shunt_resistor_uohm = val;
  474. return 0;
  475. }
  476. static ssize_t ina2xx_shunt_resistor_show(struct device *dev,
  477. struct device_attribute *attr,
  478. char *buf)
  479. {
  480. struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
  481. int vals[2] = { chip->shunt_resistor_uohm, 1000000 };
  482. return iio_format_value(buf, IIO_VAL_FRACTIONAL, 1, vals);
  483. }
  484. static ssize_t ina2xx_shunt_resistor_store(struct device *dev,
  485. struct device_attribute *attr,
  486. const char *buf, size_t len)
  487. {
  488. struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
  489. int val, val_fract, ret;
  490. ret = iio_str_to_fixpoint(buf, 100000, &val, &val_fract);
  491. if (ret)
  492. return ret;
  493. ret = set_shunt_resistor(chip, val * 1000000 + val_fract);
  494. if (ret)
  495. return ret;
  496. return len;
  497. }
  498. #define INA219_CHAN(_type, _index, _address) { \
  499. .type = (_type), \
  500. .address = (_address), \
  501. .indexed = 1, \
  502. .channel = (_index), \
  503. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  504. BIT(IIO_CHAN_INFO_SCALE), \
  505. .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  506. .scan_index = (_index), \
  507. .scan_type = { \
  508. .sign = 'u', \
  509. .realbits = 16, \
  510. .storagebits = 16, \
  511. .endianness = IIO_CPU, \
  512. } \
  513. }
  514. #define INA226_CHAN(_type, _index, _address) { \
  515. .type = (_type), \
  516. .address = (_address), \
  517. .indexed = 1, \
  518. .channel = (_index), \
  519. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  520. BIT(IIO_CHAN_INFO_SCALE), \
  521. .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
  522. BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
  523. .scan_index = (_index), \
  524. .scan_type = { \
  525. .sign = 'u', \
  526. .realbits = 16, \
  527. .storagebits = 16, \
  528. .endianness = IIO_CPU, \
  529. } \
  530. }
  531. /*
  532. * Sampling Freq is a consequence of the integration times of
  533. * the Voltage channels.
  534. */
  535. #define INA219_CHAN_VOLTAGE(_index, _address, _shift) { \
  536. .type = IIO_VOLTAGE, \
  537. .address = (_address), \
  538. .indexed = 1, \
  539. .channel = (_index), \
  540. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  541. BIT(IIO_CHAN_INFO_SCALE) | \
  542. BIT(IIO_CHAN_INFO_INT_TIME) | \
  543. BIT(IIO_CHAN_INFO_HARDWAREGAIN), \
  544. .info_mask_separate_available = \
  545. BIT(IIO_CHAN_INFO_HARDWAREGAIN), \
  546. .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  547. .scan_index = (_index), \
  548. .scan_type = { \
  549. .sign = 'u', \
  550. .shift = _shift, \
  551. .realbits = 16 - _shift, \
  552. .storagebits = 16, \
  553. .endianness = IIO_LE, \
  554. } \
  555. }
  556. #define INA226_CHAN_VOLTAGE(_index, _address) { \
  557. .type = IIO_VOLTAGE, \
  558. .address = (_address), \
  559. .indexed = 1, \
  560. .channel = (_index), \
  561. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  562. BIT(IIO_CHAN_INFO_SCALE) | \
  563. BIT(IIO_CHAN_INFO_INT_TIME), \
  564. .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
  565. BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
  566. .scan_index = (_index), \
  567. .scan_type = { \
  568. .sign = 'u', \
  569. .realbits = 16, \
  570. .storagebits = 16, \
  571. .endianness = IIO_LE, \
  572. } \
  573. }
  574. static const struct iio_chan_spec ina226_channels[] = {
  575. INA226_CHAN_VOLTAGE(0, INA2XX_SHUNT_VOLTAGE),
  576. INA226_CHAN_VOLTAGE(1, INA2XX_BUS_VOLTAGE),
  577. INA226_CHAN(IIO_POWER, 2, INA2XX_POWER),
  578. INA226_CHAN(IIO_CURRENT, 3, INA2XX_CURRENT),
  579. IIO_CHAN_SOFT_TIMESTAMP(4),
  580. };
  581. static const struct iio_chan_spec ina219_channels[] = {
  582. INA219_CHAN_VOLTAGE(0, INA2XX_SHUNT_VOLTAGE, 0),
  583. INA219_CHAN_VOLTAGE(1, INA2XX_BUS_VOLTAGE, INA219_BUS_VOLTAGE_SHIFT),
  584. INA219_CHAN(IIO_POWER, 2, INA2XX_POWER),
  585. INA219_CHAN(IIO_CURRENT, 3, INA2XX_CURRENT),
  586. IIO_CHAN_SOFT_TIMESTAMP(4),
  587. };
  588. static int ina2xx_conversion_ready(struct iio_dev *indio_dev)
  589. {
  590. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  591. int ret;
  592. unsigned int alert;
  593. /*
  594. * Because the timer thread and the chip conversion clock
  595. * are asynchronous, the period difference will eventually
  596. * result in reading V[k-1] again, or skip V[k] at time Tk.
  597. * In order to resync the timer with the conversion process
  598. * we check the ConVersionReadyFlag.
  599. * On hardware that supports using the ALERT pin to toggle a
  600. * GPIO a triggered buffer could be used instead.
  601. * For now, we do an extra read of the MASK_ENABLE register (INA226)
  602. * resp. the BUS_VOLTAGE register (INA219).
  603. */
  604. if (chip->config->chip_id == ina226) {
  605. ret = regmap_read(chip->regmap,
  606. INA226_MASK_ENABLE, &alert);
  607. alert &= INA226_CVRF;
  608. } else {
  609. ret = regmap_read(chip->regmap,
  610. INA2XX_BUS_VOLTAGE, &alert);
  611. alert &= INA219_CNVR;
  612. }
  613. if (ret < 0)
  614. return ret;
  615. return !!alert;
  616. }
  617. static int ina2xx_work_buffer(struct iio_dev *indio_dev)
  618. {
  619. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  620. int bit, ret, i = 0;
  621. s64 time;
  622. time = iio_get_time_ns(indio_dev);
  623. /*
  624. * Single register reads: bulk_read will not work with ina226/219
  625. * as there is no auto-increment of the register pointer.
  626. */
  627. for_each_set_bit(bit, indio_dev->active_scan_mask,
  628. indio_dev->masklength) {
  629. unsigned int val;
  630. ret = regmap_read(chip->regmap,
  631. INA2XX_SHUNT_VOLTAGE + bit, &val);
  632. if (ret < 0)
  633. return ret;
  634. chip->scan.chan[i++] = val;
  635. }
  636. iio_push_to_buffers_with_timestamp(indio_dev, &chip->scan, time);
  637. return 0;
  638. };
  639. static int ina2xx_capture_thread(void *data)
  640. {
  641. struct iio_dev *indio_dev = data;
  642. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  643. int sampling_us = SAMPLING_PERIOD(chip);
  644. int ret;
  645. struct timespec64 next, now, delta;
  646. s64 delay_us;
  647. /*
  648. * Poll a bit faster than the chip internal Fs, in case
  649. * we wish to sync with the conversion ready flag.
  650. */
  651. if (!chip->allow_async_readout)
  652. sampling_us -= 200;
  653. ktime_get_ts64(&next);
  654. do {
  655. while (!chip->allow_async_readout) {
  656. ret = ina2xx_conversion_ready(indio_dev);
  657. if (ret < 0)
  658. return ret;
  659. /*
  660. * If the conversion was not yet finished,
  661. * reset the reference timestamp.
  662. */
  663. if (ret == 0)
  664. ktime_get_ts64(&next);
  665. else
  666. break;
  667. }
  668. ret = ina2xx_work_buffer(indio_dev);
  669. if (ret < 0)
  670. return ret;
  671. ktime_get_ts64(&now);
  672. /*
  673. * Advance the timestamp for the next poll by one sampling
  674. * interval, and sleep for the remainder (next - now)
  675. * In case "next" has already passed, the interval is added
  676. * multiple times, i.e. samples are dropped.
  677. */
  678. do {
  679. timespec64_add_ns(&next, 1000 * sampling_us);
  680. delta = timespec64_sub(next, now);
  681. delay_us = div_s64(timespec64_to_ns(&delta), 1000);
  682. } while (delay_us <= 0);
  683. usleep_range(delay_us, (delay_us * 3) >> 1);
  684. } while (!kthread_should_stop());
  685. return 0;
  686. }
  687. static int ina2xx_buffer_enable(struct iio_dev *indio_dev)
  688. {
  689. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  690. unsigned int sampling_us = SAMPLING_PERIOD(chip);
  691. struct task_struct *task;
  692. dev_dbg(&indio_dev->dev, "Enabling buffer w/ scan_mask %02x, freq = %d, avg =%u\n",
  693. (unsigned int)(*indio_dev->active_scan_mask),
  694. 1000000 / sampling_us, chip->avg);
  695. dev_dbg(&indio_dev->dev, "Expected work period: %u us\n", sampling_us);
  696. dev_dbg(&indio_dev->dev, "Async readout mode: %d\n",
  697. chip->allow_async_readout);
  698. task = kthread_create(ina2xx_capture_thread, (void *)indio_dev,
  699. "%s:%d-%uus", indio_dev->name, indio_dev->id,
  700. sampling_us);
  701. if (IS_ERR(task))
  702. return PTR_ERR(task);
  703. get_task_struct(task);
  704. wake_up_process(task);
  705. chip->task = task;
  706. return 0;
  707. }
  708. static int ina2xx_buffer_disable(struct iio_dev *indio_dev)
  709. {
  710. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  711. if (chip->task) {
  712. kthread_stop(chip->task);
  713. put_task_struct(chip->task);
  714. chip->task = NULL;
  715. }
  716. return 0;
  717. }
  718. static const struct iio_buffer_setup_ops ina2xx_setup_ops = {
  719. .postenable = &ina2xx_buffer_enable,
  720. .predisable = &ina2xx_buffer_disable,
  721. };
  722. static int ina2xx_debug_reg(struct iio_dev *indio_dev,
  723. unsigned reg, unsigned writeval, unsigned *readval)
  724. {
  725. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  726. if (!readval)
  727. return regmap_write(chip->regmap, reg, writeval);
  728. return regmap_read(chip->regmap, reg, readval);
  729. }
  730. /* Possible integration times for vshunt and vbus */
  731. static IIO_CONST_ATTR_NAMED(ina219_integration_time_available,
  732. integration_time_available,
  733. "0.000084 0.000148 0.000276 0.000532 0.001060 0.002130 0.004260 0.008510 0.017020 0.034050 0.068100");
  734. static IIO_CONST_ATTR_NAMED(ina226_integration_time_available,
  735. integration_time_available,
  736. "0.000140 0.000204 0.000332 0.000588 0.001100 0.002116 0.004156 0.008244");
  737. static IIO_DEVICE_ATTR(in_allow_async_readout, S_IRUGO | S_IWUSR,
  738. ina2xx_allow_async_readout_show,
  739. ina2xx_allow_async_readout_store, 0);
  740. static IIO_DEVICE_ATTR(in_shunt_resistor, S_IRUGO | S_IWUSR,
  741. ina2xx_shunt_resistor_show,
  742. ina2xx_shunt_resistor_store, 0);
  743. static struct attribute *ina219_attributes[] = {
  744. &iio_dev_attr_in_allow_async_readout.dev_attr.attr,
  745. &iio_const_attr_ina219_integration_time_available.dev_attr.attr,
  746. &iio_dev_attr_in_shunt_resistor.dev_attr.attr,
  747. NULL,
  748. };
  749. static struct attribute *ina226_attributes[] = {
  750. &iio_dev_attr_in_allow_async_readout.dev_attr.attr,
  751. &iio_const_attr_ina226_integration_time_available.dev_attr.attr,
  752. &iio_dev_attr_in_shunt_resistor.dev_attr.attr,
  753. NULL,
  754. };
  755. static const struct attribute_group ina219_attribute_group = {
  756. .attrs = ina219_attributes,
  757. };
  758. static const struct attribute_group ina226_attribute_group = {
  759. .attrs = ina226_attributes,
  760. };
  761. static const struct iio_info ina219_info = {
  762. .attrs = &ina219_attribute_group,
  763. .read_raw = ina2xx_read_raw,
  764. .read_avail = ina2xx_read_avail,
  765. .write_raw = ina2xx_write_raw,
  766. .debugfs_reg_access = ina2xx_debug_reg,
  767. };
  768. static const struct iio_info ina226_info = {
  769. .attrs = &ina226_attribute_group,
  770. .read_raw = ina2xx_read_raw,
  771. .write_raw = ina2xx_write_raw,
  772. .debugfs_reg_access = ina2xx_debug_reg,
  773. };
  774. /* Initialize the configuration and calibration registers. */
  775. static int ina2xx_init(struct ina2xx_chip_info *chip, unsigned int config)
  776. {
  777. int ret = regmap_write(chip->regmap, INA2XX_CONFIG, config);
  778. if (ret)
  779. return ret;
  780. return ina2xx_set_calibration(chip);
  781. }
  782. static int ina2xx_probe(struct i2c_client *client,
  783. const struct i2c_device_id *id)
  784. {
  785. struct ina2xx_chip_info *chip;
  786. struct iio_dev *indio_dev;
  787. struct iio_buffer *buffer;
  788. unsigned int val;
  789. enum ina2xx_ids type;
  790. int ret;
  791. indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
  792. if (!indio_dev)
  793. return -ENOMEM;
  794. chip = iio_priv(indio_dev);
  795. /* This is only used for device removal purposes. */
  796. i2c_set_clientdata(client, indio_dev);
  797. chip->regmap = devm_regmap_init_i2c(client, &ina2xx_regmap_config);
  798. if (IS_ERR(chip->regmap)) {
  799. dev_err(&client->dev, "failed to allocate register map\n");
  800. return PTR_ERR(chip->regmap);
  801. }
  802. if (client->dev.of_node)
  803. type = (enum ina2xx_ids)of_device_get_match_data(&client->dev);
  804. else
  805. type = id->driver_data;
  806. chip->config = &ina2xx_config[type];
  807. mutex_init(&chip->state_lock);
  808. if (of_property_read_u32(client->dev.of_node,
  809. "shunt-resistor", &val) < 0) {
  810. struct ina2xx_platform_data *pdata =
  811. dev_get_platdata(&client->dev);
  812. if (pdata)
  813. val = pdata->shunt_uohms;
  814. else
  815. val = INA2XX_RSHUNT_DEFAULT;
  816. }
  817. ret = set_shunt_resistor(chip, val);
  818. if (ret)
  819. return ret;
  820. /* Patch the current config register with default. */
  821. val = chip->config->config_default;
  822. if (id->driver_data == ina226) {
  823. ina226_set_average(chip, INA226_DEFAULT_AVG, &val);
  824. ina226_set_int_time_vbus(chip, INA226_DEFAULT_IT, &val);
  825. ina226_set_int_time_vshunt(chip, INA226_DEFAULT_IT, &val);
  826. } else {
  827. chip->avg = 1;
  828. ina219_set_int_time_vbus(chip, INA219_DEFAULT_IT, &val);
  829. ina219_set_int_time_vshunt(chip, INA219_DEFAULT_IT, &val);
  830. ina219_set_vbus_range_denom(chip, INA219_DEFAULT_BRNG, &val);
  831. ina219_set_vshunt_pga_gain(chip, INA219_DEFAULT_PGA, &val);
  832. }
  833. ret = ina2xx_init(chip, val);
  834. if (ret) {
  835. dev_err(&client->dev, "error configuring the device\n");
  836. return ret;
  837. }
  838. indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
  839. if (id->driver_data == ina226) {
  840. indio_dev->channels = ina226_channels;
  841. indio_dev->num_channels = ARRAY_SIZE(ina226_channels);
  842. indio_dev->info = &ina226_info;
  843. } else {
  844. indio_dev->channels = ina219_channels;
  845. indio_dev->num_channels = ARRAY_SIZE(ina219_channels);
  846. indio_dev->info = &ina219_info;
  847. }
  848. indio_dev->name = id->name;
  849. indio_dev->setup_ops = &ina2xx_setup_ops;
  850. buffer = devm_iio_kfifo_allocate(&indio_dev->dev);
  851. if (!buffer)
  852. return -ENOMEM;
  853. iio_device_attach_buffer(indio_dev, buffer);
  854. return iio_device_register(indio_dev);
  855. }
  856. static int ina2xx_remove(struct i2c_client *client)
  857. {
  858. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  859. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  860. iio_device_unregister(indio_dev);
  861. /* Powerdown */
  862. return regmap_update_bits(chip->regmap, INA2XX_CONFIG,
  863. INA2XX_MODE_MASK, 0);
  864. }
  865. static const struct i2c_device_id ina2xx_id[] = {
  866. {"ina219", ina219},
  867. {"ina220", ina219},
  868. {"ina226", ina226},
  869. {"ina230", ina226},
  870. {"ina231", ina226},
  871. {}
  872. };
  873. MODULE_DEVICE_TABLE(i2c, ina2xx_id);
  874. static const struct of_device_id ina2xx_of_match[] = {
  875. {
  876. .compatible = "ti,ina219",
  877. .data = (void *)ina219
  878. },
  879. {
  880. .compatible = "ti,ina220",
  881. .data = (void *)ina219
  882. },
  883. {
  884. .compatible = "ti,ina226",
  885. .data = (void *)ina226
  886. },
  887. {
  888. .compatible = "ti,ina230",
  889. .data = (void *)ina226
  890. },
  891. {
  892. .compatible = "ti,ina231",
  893. .data = (void *)ina226
  894. },
  895. {},
  896. };
  897. MODULE_DEVICE_TABLE(of, ina2xx_of_match);
  898. static struct i2c_driver ina2xx_driver = {
  899. .driver = {
  900. .name = KBUILD_MODNAME,
  901. .of_match_table = ina2xx_of_match,
  902. },
  903. .probe = ina2xx_probe,
  904. .remove = ina2xx_remove,
  905. .id_table = ina2xx_id,
  906. };
  907. module_i2c_driver(ina2xx_driver);
  908. MODULE_AUTHOR("Marc Titinger <marc.titinger@baylibre.com>");
  909. MODULE_DESCRIPTION("Texas Instruments INA2XX ADC driver");
  910. MODULE_LICENSE("GPL v2");