imx7d_adc.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Freescale i.MX7D ADC driver
  4. *
  5. * Copyright (C) 2015 Freescale Semiconductor, Inc.
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/completion.h>
  9. #include <linux/err.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/io.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/regulator/consumer.h>
  16. #include <linux/iio/iio.h>
  17. #include <linux/iio/driver.h>
  18. #include <linux/iio/sysfs.h>
  19. /* ADC register */
  20. #define IMX7D_REG_ADC_CH_A_CFG1 0x00
  21. #define IMX7D_REG_ADC_CH_A_CFG2 0x10
  22. #define IMX7D_REG_ADC_CH_B_CFG1 0x20
  23. #define IMX7D_REG_ADC_CH_B_CFG2 0x30
  24. #define IMX7D_REG_ADC_CH_C_CFG1 0x40
  25. #define IMX7D_REG_ADC_CH_C_CFG2 0x50
  26. #define IMX7D_REG_ADC_CH_D_CFG1 0x60
  27. #define IMX7D_REG_ADC_CH_D_CFG2 0x70
  28. #define IMX7D_REG_ADC_CH_SW_CFG 0x80
  29. #define IMX7D_REG_ADC_TIMER_UNIT 0x90
  30. #define IMX7D_REG_ADC_DMA_FIFO 0xa0
  31. #define IMX7D_REG_ADC_FIFO_STATUS 0xb0
  32. #define IMX7D_REG_ADC_INT_SIG_EN 0xc0
  33. #define IMX7D_REG_ADC_INT_EN 0xd0
  34. #define IMX7D_REG_ADC_INT_STATUS 0xe0
  35. #define IMX7D_REG_ADC_CHA_B_CNV_RSLT 0xf0
  36. #define IMX7D_REG_ADC_CHC_D_CNV_RSLT 0x100
  37. #define IMX7D_REG_ADC_CH_SW_CNV_RSLT 0x110
  38. #define IMX7D_REG_ADC_DMA_FIFO_DAT 0x120
  39. #define IMX7D_REG_ADC_ADC_CFG 0x130
  40. #define IMX7D_REG_ADC_CHANNEL_CFG2_BASE 0x10
  41. #define IMX7D_EACH_CHANNEL_REG_OFFSET 0x20
  42. #define IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN (0x1 << 31)
  43. #define IMX7D_REG_ADC_CH_CFG1_CHANNEL_SINGLE BIT(30)
  44. #define IMX7D_REG_ADC_CH_CFG1_CHANNEL_AVG_EN BIT(29)
  45. #define IMX7D_REG_ADC_CH_CFG1_CHANNEL_SEL(x) ((x) << 24)
  46. #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_4 (0x0 << 12)
  47. #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_8 (0x1 << 12)
  48. #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_16 (0x2 << 12)
  49. #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_32 (0x3 << 12)
  50. #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_4 (0x0 << 29)
  51. #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_8 (0x1 << 29)
  52. #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_16 (0x2 << 29)
  53. #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_32 (0x3 << 29)
  54. #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_64 (0x4 << 29)
  55. #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_128 (0x5 << 29)
  56. #define IMX7D_REG_ADC_ADC_CFG_ADC_CLK_DOWN BIT(31)
  57. #define IMX7D_REG_ADC_ADC_CFG_ADC_POWER_DOWN BIT(1)
  58. #define IMX7D_REG_ADC_ADC_CFG_ADC_EN BIT(0)
  59. #define IMX7D_REG_ADC_INT_CHA_COV_INT_EN BIT(8)
  60. #define IMX7D_REG_ADC_INT_CHB_COV_INT_EN BIT(9)
  61. #define IMX7D_REG_ADC_INT_CHC_COV_INT_EN BIT(10)
  62. #define IMX7D_REG_ADC_INT_CHD_COV_INT_EN BIT(11)
  63. #define IMX7D_REG_ADC_INT_CHANNEL_INT_EN \
  64. (IMX7D_REG_ADC_INT_CHA_COV_INT_EN | \
  65. IMX7D_REG_ADC_INT_CHB_COV_INT_EN | \
  66. IMX7D_REG_ADC_INT_CHC_COV_INT_EN | \
  67. IMX7D_REG_ADC_INT_CHD_COV_INT_EN)
  68. #define IMX7D_REG_ADC_INT_STATUS_CHANNEL_INT_STATUS 0xf00
  69. #define IMX7D_REG_ADC_INT_STATUS_CHANNEL_CONV_TIME_OUT 0xf0000
  70. #define IMX7D_ADC_TIMEOUT msecs_to_jiffies(100)
  71. #define IMX7D_ADC_INPUT_CLK 24000000
  72. enum imx7d_adc_clk_pre_div {
  73. IMX7D_ADC_ANALOG_CLK_PRE_DIV_4,
  74. IMX7D_ADC_ANALOG_CLK_PRE_DIV_8,
  75. IMX7D_ADC_ANALOG_CLK_PRE_DIV_16,
  76. IMX7D_ADC_ANALOG_CLK_PRE_DIV_32,
  77. IMX7D_ADC_ANALOG_CLK_PRE_DIV_64,
  78. IMX7D_ADC_ANALOG_CLK_PRE_DIV_128,
  79. };
  80. enum imx7d_adc_average_num {
  81. IMX7D_ADC_AVERAGE_NUM_4,
  82. IMX7D_ADC_AVERAGE_NUM_8,
  83. IMX7D_ADC_AVERAGE_NUM_16,
  84. IMX7D_ADC_AVERAGE_NUM_32,
  85. };
  86. struct imx7d_adc_feature {
  87. enum imx7d_adc_clk_pre_div clk_pre_div;
  88. enum imx7d_adc_average_num avg_num;
  89. u32 core_time_unit; /* impact the sample rate */
  90. };
  91. struct imx7d_adc {
  92. struct device *dev;
  93. void __iomem *regs;
  94. struct clk *clk;
  95. u32 vref_uv;
  96. u32 value;
  97. u32 channel;
  98. u32 pre_div_num;
  99. struct regulator *vref;
  100. struct imx7d_adc_feature adc_feature;
  101. struct completion completion;
  102. };
  103. struct imx7d_adc_analogue_core_clk {
  104. u32 pre_div;
  105. u32 reg_config;
  106. };
  107. #define IMX7D_ADC_ANALOGUE_CLK_CONFIG(_pre_div, _reg_conf) { \
  108. .pre_div = (_pre_div), \
  109. .reg_config = (_reg_conf), \
  110. }
  111. static const struct imx7d_adc_analogue_core_clk imx7d_adc_analogue_clk[] = {
  112. IMX7D_ADC_ANALOGUE_CLK_CONFIG(4, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_4),
  113. IMX7D_ADC_ANALOGUE_CLK_CONFIG(8, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_8),
  114. IMX7D_ADC_ANALOGUE_CLK_CONFIG(16, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_16),
  115. IMX7D_ADC_ANALOGUE_CLK_CONFIG(32, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_32),
  116. IMX7D_ADC_ANALOGUE_CLK_CONFIG(64, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_64),
  117. IMX7D_ADC_ANALOGUE_CLK_CONFIG(128, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_128),
  118. };
  119. #define IMX7D_ADC_CHAN(_idx) { \
  120. .type = IIO_VOLTAGE, \
  121. .indexed = 1, \
  122. .channel = (_idx), \
  123. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  124. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
  125. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  126. }
  127. static const struct iio_chan_spec imx7d_adc_iio_channels[] = {
  128. IMX7D_ADC_CHAN(0),
  129. IMX7D_ADC_CHAN(1),
  130. IMX7D_ADC_CHAN(2),
  131. IMX7D_ADC_CHAN(3),
  132. IMX7D_ADC_CHAN(4),
  133. IMX7D_ADC_CHAN(5),
  134. IMX7D_ADC_CHAN(6),
  135. IMX7D_ADC_CHAN(7),
  136. IMX7D_ADC_CHAN(8),
  137. IMX7D_ADC_CHAN(9),
  138. IMX7D_ADC_CHAN(10),
  139. IMX7D_ADC_CHAN(11),
  140. IMX7D_ADC_CHAN(12),
  141. IMX7D_ADC_CHAN(13),
  142. IMX7D_ADC_CHAN(14),
  143. IMX7D_ADC_CHAN(15),
  144. };
  145. static const u32 imx7d_adc_average_num[] = {
  146. IMX7D_REG_ADC_CH_CFG2_AVG_NUM_4,
  147. IMX7D_REG_ADC_CH_CFG2_AVG_NUM_8,
  148. IMX7D_REG_ADC_CH_CFG2_AVG_NUM_16,
  149. IMX7D_REG_ADC_CH_CFG2_AVG_NUM_32,
  150. };
  151. static void imx7d_adc_feature_config(struct imx7d_adc *info)
  152. {
  153. info->adc_feature.clk_pre_div = IMX7D_ADC_ANALOG_CLK_PRE_DIV_4;
  154. info->adc_feature.avg_num = IMX7D_ADC_AVERAGE_NUM_32;
  155. info->adc_feature.core_time_unit = 1;
  156. }
  157. static void imx7d_adc_sample_rate_set(struct imx7d_adc *info)
  158. {
  159. struct imx7d_adc_feature *adc_feature = &info->adc_feature;
  160. struct imx7d_adc_analogue_core_clk adc_analogure_clk;
  161. u32 i;
  162. u32 tmp_cfg1;
  163. u32 sample_rate = 0;
  164. /*
  165. * Before sample set, disable channel A,B,C,D. Here we
  166. * clear the bit 31 of register REG_ADC_CH_A\B\C\D_CFG1.
  167. */
  168. for (i = 0; i < 4; i++) {
  169. tmp_cfg1 =
  170. readl(info->regs + i * IMX7D_EACH_CHANNEL_REG_OFFSET);
  171. tmp_cfg1 &= ~IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN;
  172. writel(tmp_cfg1,
  173. info->regs + i * IMX7D_EACH_CHANNEL_REG_OFFSET);
  174. }
  175. adc_analogure_clk = imx7d_adc_analogue_clk[adc_feature->clk_pre_div];
  176. sample_rate |= adc_analogure_clk.reg_config;
  177. info->pre_div_num = adc_analogure_clk.pre_div;
  178. sample_rate |= adc_feature->core_time_unit;
  179. writel(sample_rate, info->regs + IMX7D_REG_ADC_TIMER_UNIT);
  180. }
  181. static void imx7d_adc_hw_init(struct imx7d_adc *info)
  182. {
  183. u32 cfg;
  184. /* power up and enable adc analogue core */
  185. cfg = readl(info->regs + IMX7D_REG_ADC_ADC_CFG);
  186. cfg &= ~(IMX7D_REG_ADC_ADC_CFG_ADC_CLK_DOWN |
  187. IMX7D_REG_ADC_ADC_CFG_ADC_POWER_DOWN);
  188. cfg |= IMX7D_REG_ADC_ADC_CFG_ADC_EN;
  189. writel(cfg, info->regs + IMX7D_REG_ADC_ADC_CFG);
  190. /* enable channel A,B,C,D interrupt */
  191. writel(IMX7D_REG_ADC_INT_CHANNEL_INT_EN,
  192. info->regs + IMX7D_REG_ADC_INT_SIG_EN);
  193. writel(IMX7D_REG_ADC_INT_CHANNEL_INT_EN,
  194. info->regs + IMX7D_REG_ADC_INT_EN);
  195. imx7d_adc_sample_rate_set(info);
  196. }
  197. static void imx7d_adc_channel_set(struct imx7d_adc *info)
  198. {
  199. u32 cfg1 = 0;
  200. u32 cfg2;
  201. u32 channel;
  202. channel = info->channel;
  203. /* the channel choose single conversion, and enable average mode */
  204. cfg1 |= (IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN |
  205. IMX7D_REG_ADC_CH_CFG1_CHANNEL_SINGLE |
  206. IMX7D_REG_ADC_CH_CFG1_CHANNEL_AVG_EN);
  207. /*
  208. * physical channel 0 chose logical channel A
  209. * physical channel 1 chose logical channel B
  210. * physical channel 2 chose logical channel C
  211. * physical channel 3 chose logical channel D
  212. */
  213. cfg1 |= IMX7D_REG_ADC_CH_CFG1_CHANNEL_SEL(channel);
  214. /*
  215. * read register REG_ADC_CH_A\B\C\D_CFG2, according to the
  216. * channel chosen
  217. */
  218. cfg2 = readl(info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel +
  219. IMX7D_REG_ADC_CHANNEL_CFG2_BASE);
  220. cfg2 |= imx7d_adc_average_num[info->adc_feature.avg_num];
  221. /*
  222. * write the register REG_ADC_CH_A\B\C\D_CFG2, according to
  223. * the channel chosen
  224. */
  225. writel(cfg2, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel +
  226. IMX7D_REG_ADC_CHANNEL_CFG2_BASE);
  227. writel(cfg1, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel);
  228. }
  229. static u32 imx7d_adc_get_sample_rate(struct imx7d_adc *info)
  230. {
  231. u32 analogue_core_clk;
  232. u32 core_time_unit = info->adc_feature.core_time_unit;
  233. u32 tmp;
  234. analogue_core_clk = IMX7D_ADC_INPUT_CLK / info->pre_div_num;
  235. tmp = (core_time_unit + 1) * 6;
  236. return analogue_core_clk / tmp;
  237. }
  238. static int imx7d_adc_read_raw(struct iio_dev *indio_dev,
  239. struct iio_chan_spec const *chan,
  240. int *val,
  241. int *val2,
  242. long mask)
  243. {
  244. struct imx7d_adc *info = iio_priv(indio_dev);
  245. u32 channel;
  246. long ret;
  247. switch (mask) {
  248. case IIO_CHAN_INFO_RAW:
  249. mutex_lock(&indio_dev->mlock);
  250. reinit_completion(&info->completion);
  251. channel = chan->channel & 0x03;
  252. info->channel = channel;
  253. imx7d_adc_channel_set(info);
  254. ret = wait_for_completion_interruptible_timeout
  255. (&info->completion, IMX7D_ADC_TIMEOUT);
  256. if (ret == 0) {
  257. mutex_unlock(&indio_dev->mlock);
  258. return -ETIMEDOUT;
  259. }
  260. if (ret < 0) {
  261. mutex_unlock(&indio_dev->mlock);
  262. return ret;
  263. }
  264. *val = info->value;
  265. mutex_unlock(&indio_dev->mlock);
  266. return IIO_VAL_INT;
  267. case IIO_CHAN_INFO_SCALE:
  268. info->vref_uv = regulator_get_voltage(info->vref);
  269. *val = info->vref_uv / 1000;
  270. *val2 = 12;
  271. return IIO_VAL_FRACTIONAL_LOG2;
  272. case IIO_CHAN_INFO_SAMP_FREQ:
  273. *val = imx7d_adc_get_sample_rate(info);
  274. return IIO_VAL_INT;
  275. default:
  276. return -EINVAL;
  277. }
  278. }
  279. static int imx7d_adc_read_data(struct imx7d_adc *info)
  280. {
  281. u32 channel;
  282. u32 value;
  283. channel = info->channel & 0x03;
  284. /*
  285. * channel A and B conversion result share one register,
  286. * bit[27~16] is the channel B conversion result,
  287. * bit[11~0] is the channel A conversion result.
  288. * channel C and D is the same.
  289. */
  290. if (channel < 2)
  291. value = readl(info->regs + IMX7D_REG_ADC_CHA_B_CNV_RSLT);
  292. else
  293. value = readl(info->regs + IMX7D_REG_ADC_CHC_D_CNV_RSLT);
  294. if (channel & 0x1) /* channel B or D */
  295. value = (value >> 16) & 0xFFF;
  296. else /* channel A or C */
  297. value &= 0xFFF;
  298. return value;
  299. }
  300. static irqreturn_t imx7d_adc_isr(int irq, void *dev_id)
  301. {
  302. struct imx7d_adc *info = dev_id;
  303. int status;
  304. status = readl(info->regs + IMX7D_REG_ADC_INT_STATUS);
  305. if (status & IMX7D_REG_ADC_INT_STATUS_CHANNEL_INT_STATUS) {
  306. info->value = imx7d_adc_read_data(info);
  307. complete(&info->completion);
  308. /*
  309. * The register IMX7D_REG_ADC_INT_STATUS can't clear
  310. * itself after read operation, need software to write
  311. * 0 to the related bit. Here we clear the channel A/B/C/D
  312. * conversion finished flag.
  313. */
  314. status &= ~IMX7D_REG_ADC_INT_STATUS_CHANNEL_INT_STATUS;
  315. writel(status, info->regs + IMX7D_REG_ADC_INT_STATUS);
  316. }
  317. /*
  318. * If the channel A/B/C/D conversion timeout, report it and clear these
  319. * timeout flags.
  320. */
  321. if (status & IMX7D_REG_ADC_INT_STATUS_CHANNEL_CONV_TIME_OUT) {
  322. dev_err(info->dev,
  323. "ADC got conversion time out interrupt: 0x%08x\n",
  324. status);
  325. status &= ~IMX7D_REG_ADC_INT_STATUS_CHANNEL_CONV_TIME_OUT;
  326. writel(status, info->regs + IMX7D_REG_ADC_INT_STATUS);
  327. }
  328. return IRQ_HANDLED;
  329. }
  330. static int imx7d_adc_reg_access(struct iio_dev *indio_dev,
  331. unsigned reg, unsigned writeval,
  332. unsigned *readval)
  333. {
  334. struct imx7d_adc *info = iio_priv(indio_dev);
  335. if (!readval || reg % 4 || reg > IMX7D_REG_ADC_ADC_CFG)
  336. return -EINVAL;
  337. *readval = readl(info->regs + reg);
  338. return 0;
  339. }
  340. static const struct iio_info imx7d_adc_iio_info = {
  341. .read_raw = &imx7d_adc_read_raw,
  342. .debugfs_reg_access = &imx7d_adc_reg_access,
  343. };
  344. static const struct of_device_id imx7d_adc_match[] = {
  345. { .compatible = "fsl,imx7d-adc", },
  346. { /* sentinel */ }
  347. };
  348. MODULE_DEVICE_TABLE(of, imx7d_adc_match);
  349. static void imx7d_adc_power_down(struct imx7d_adc *info)
  350. {
  351. u32 adc_cfg;
  352. adc_cfg = readl(info->regs + IMX7D_REG_ADC_ADC_CFG);
  353. adc_cfg |= IMX7D_REG_ADC_ADC_CFG_ADC_CLK_DOWN |
  354. IMX7D_REG_ADC_ADC_CFG_ADC_POWER_DOWN;
  355. adc_cfg &= ~IMX7D_REG_ADC_ADC_CFG_ADC_EN;
  356. writel(adc_cfg, info->regs + IMX7D_REG_ADC_ADC_CFG);
  357. }
  358. static int imx7d_adc_enable(struct device *dev)
  359. {
  360. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  361. struct imx7d_adc *info = iio_priv(indio_dev);
  362. int ret;
  363. ret = regulator_enable(info->vref);
  364. if (ret) {
  365. dev_err(info->dev,
  366. "Can't enable adc reference top voltage, err = %d\n",
  367. ret);
  368. return ret;
  369. }
  370. ret = clk_prepare_enable(info->clk);
  371. if (ret) {
  372. dev_err(info->dev,
  373. "Could not prepare or enable clock.\n");
  374. regulator_disable(info->vref);
  375. return ret;
  376. }
  377. imx7d_adc_hw_init(info);
  378. return 0;
  379. }
  380. static int imx7d_adc_disable(struct device *dev)
  381. {
  382. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  383. struct imx7d_adc *info = iio_priv(indio_dev);
  384. imx7d_adc_power_down(info);
  385. clk_disable_unprepare(info->clk);
  386. regulator_disable(info->vref);
  387. return 0;
  388. }
  389. static void __imx7d_adc_disable(void *data)
  390. {
  391. imx7d_adc_disable(data);
  392. }
  393. static int imx7d_adc_probe(struct platform_device *pdev)
  394. {
  395. struct imx7d_adc *info;
  396. struct iio_dev *indio_dev;
  397. struct device *dev = &pdev->dev;
  398. int irq;
  399. int ret;
  400. indio_dev = devm_iio_device_alloc(dev, sizeof(*info));
  401. if (!indio_dev) {
  402. dev_err(&pdev->dev, "Failed allocating iio device\n");
  403. return -ENOMEM;
  404. }
  405. info = iio_priv(indio_dev);
  406. info->dev = dev;
  407. info->regs = devm_platform_ioremap_resource(pdev, 0);
  408. if (IS_ERR(info->regs))
  409. return PTR_ERR(info->regs);
  410. irq = platform_get_irq(pdev, 0);
  411. if (irq < 0)
  412. return irq;
  413. info->clk = devm_clk_get(dev, "adc");
  414. if (IS_ERR(info->clk)) {
  415. ret = PTR_ERR(info->clk);
  416. dev_err(dev, "Failed getting clock, err = %d\n", ret);
  417. return ret;
  418. }
  419. info->vref = devm_regulator_get(dev, "vref");
  420. if (IS_ERR(info->vref)) {
  421. ret = PTR_ERR(info->vref);
  422. dev_err(dev,
  423. "Failed getting reference voltage, err = %d\n", ret);
  424. return ret;
  425. }
  426. platform_set_drvdata(pdev, indio_dev);
  427. init_completion(&info->completion);
  428. indio_dev->name = dev_name(dev);
  429. indio_dev->info = &imx7d_adc_iio_info;
  430. indio_dev->modes = INDIO_DIRECT_MODE;
  431. indio_dev->channels = imx7d_adc_iio_channels;
  432. indio_dev->num_channels = ARRAY_SIZE(imx7d_adc_iio_channels);
  433. ret = devm_request_irq(dev, irq, imx7d_adc_isr, 0, dev_name(dev), info);
  434. if (ret < 0) {
  435. dev_err(dev, "Failed requesting irq, irq = %d\n", irq);
  436. return ret;
  437. }
  438. imx7d_adc_feature_config(info);
  439. ret = imx7d_adc_enable(&indio_dev->dev);
  440. if (ret)
  441. return ret;
  442. ret = devm_add_action_or_reset(dev, __imx7d_adc_disable,
  443. &indio_dev->dev);
  444. if (ret)
  445. return ret;
  446. ret = devm_iio_device_register(dev, indio_dev);
  447. if (ret) {
  448. dev_err(&pdev->dev, "Couldn't register the device.\n");
  449. return ret;
  450. }
  451. return 0;
  452. }
  453. static SIMPLE_DEV_PM_OPS(imx7d_adc_pm_ops, imx7d_adc_disable, imx7d_adc_enable);
  454. static struct platform_driver imx7d_adc_driver = {
  455. .probe = imx7d_adc_probe,
  456. .driver = {
  457. .name = "imx7d_adc",
  458. .of_match_table = imx7d_adc_match,
  459. .pm = &imx7d_adc_pm_ops,
  460. },
  461. };
  462. module_platform_driver(imx7d_adc_driver);
  463. MODULE_AUTHOR("Haibo Chen <haibo.chen@freescale.com>");
  464. MODULE_DESCRIPTION("Freescale IMX7D ADC driver");
  465. MODULE_LICENSE("GPL v2");