ep93xx_adc.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for ADC module on the Cirrus Logic EP93xx series of SoCs
  4. *
  5. * Copyright (C) 2015 Alexander Sverdlin
  6. *
  7. * The driver uses polling to get the conversion status. According to EP93xx
  8. * datasheets, reading ADCResult register starts the conversion, but user is also
  9. * responsible for ensuring that delay between adjacent conversion triggers is
  10. * long enough so that maximum allowed conversion rate is not exceeded. This
  11. * basically renders IRQ mode unusable.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/device.h>
  16. #include <linux/err.h>
  17. #include <linux/iio/iio.h>
  18. #include <linux/io.h>
  19. #include <linux/irqflags.h>
  20. #include <linux/module.h>
  21. #include <linux/mutex.h>
  22. #include <linux/platform_device.h>
  23. /*
  24. * This code could benefit from real HR Timers, but jiffy granularity would
  25. * lower ADC conversion rate down to CONFIG_HZ, so we fallback to busy wait
  26. * in such case.
  27. *
  28. * HR Timers-based version loads CPU only up to 10% during back to back ADC
  29. * conversion, while busy wait-based version consumes whole CPU power.
  30. */
  31. #ifdef CONFIG_HIGH_RES_TIMERS
  32. #define ep93xx_adc_delay(usmin, usmax) usleep_range(usmin, usmax)
  33. #else
  34. #define ep93xx_adc_delay(usmin, usmax) udelay(usmin)
  35. #endif
  36. #define EP93XX_ADC_RESULT 0x08
  37. #define EP93XX_ADC_SDR BIT(31)
  38. #define EP93XX_ADC_SWITCH 0x18
  39. #define EP93XX_ADC_SW_LOCK 0x20
  40. struct ep93xx_adc_priv {
  41. struct clk *clk;
  42. void __iomem *base;
  43. int lastch;
  44. struct mutex lock;
  45. };
  46. #define EP93XX_ADC_CH(index, dname, swcfg) { \
  47. .type = IIO_VOLTAGE, \
  48. .indexed = 1, \
  49. .channel = index, \
  50. .address = swcfg, \
  51. .datasheet_name = dname, \
  52. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  53. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) | \
  54. BIT(IIO_CHAN_INFO_OFFSET), \
  55. }
  56. /*
  57. * Numbering scheme for channels 0..4 is defined in EP9301 and EP9302 datasheets.
  58. * EP9307, EP9312 and EP9312 have 3 channels more (total 8), but the numbering is
  59. * not defined. So the last three are numbered randomly, let's say.
  60. */
  61. static const struct iio_chan_spec ep93xx_adc_channels[8] = {
  62. EP93XX_ADC_CH(0, "YM", 0x608),
  63. EP93XX_ADC_CH(1, "SXP", 0x680),
  64. EP93XX_ADC_CH(2, "SXM", 0x640),
  65. EP93XX_ADC_CH(3, "SYP", 0x620),
  66. EP93XX_ADC_CH(4, "SYM", 0x610),
  67. EP93XX_ADC_CH(5, "XP", 0x601),
  68. EP93XX_ADC_CH(6, "XM", 0x602),
  69. EP93XX_ADC_CH(7, "YP", 0x604),
  70. };
  71. static int ep93xx_read_raw(struct iio_dev *iiodev,
  72. struct iio_chan_spec const *channel, int *value,
  73. int *shift, long mask)
  74. {
  75. struct ep93xx_adc_priv *priv = iio_priv(iiodev);
  76. unsigned long timeout;
  77. int ret;
  78. switch (mask) {
  79. case IIO_CHAN_INFO_RAW:
  80. mutex_lock(&priv->lock);
  81. if (priv->lastch != channel->channel) {
  82. priv->lastch = channel->channel;
  83. /*
  84. * Switch register is software-locked, unlocking must be
  85. * immediately followed by write
  86. */
  87. local_irq_disable();
  88. writel_relaxed(0xAA, priv->base + EP93XX_ADC_SW_LOCK);
  89. writel_relaxed(channel->address,
  90. priv->base + EP93XX_ADC_SWITCH);
  91. local_irq_enable();
  92. /*
  93. * Settling delay depends on module clock and could be
  94. * 2ms or 500us
  95. */
  96. ep93xx_adc_delay(2000, 2000);
  97. }
  98. /* Start the conversion, eventually discarding old result */
  99. readl_relaxed(priv->base + EP93XX_ADC_RESULT);
  100. /* Ensure maximum conversion rate is not exceeded */
  101. ep93xx_adc_delay(DIV_ROUND_UP(1000000, 925),
  102. DIV_ROUND_UP(1000000, 925));
  103. /* At this point conversion must be completed, but anyway... */
  104. ret = IIO_VAL_INT;
  105. timeout = jiffies + msecs_to_jiffies(1) + 1;
  106. while (1) {
  107. u32 t;
  108. t = readl_relaxed(priv->base + EP93XX_ADC_RESULT);
  109. if (t & EP93XX_ADC_SDR) {
  110. *value = sign_extend32(t, 15);
  111. break;
  112. }
  113. if (time_after(jiffies, timeout)) {
  114. dev_err(&iiodev->dev, "Conversion timeout\n");
  115. ret = -ETIMEDOUT;
  116. break;
  117. }
  118. cpu_relax();
  119. }
  120. mutex_unlock(&priv->lock);
  121. return ret;
  122. case IIO_CHAN_INFO_OFFSET:
  123. /* According to datasheet, range is -25000..25000 */
  124. *value = 25000;
  125. return IIO_VAL_INT;
  126. case IIO_CHAN_INFO_SCALE:
  127. /* Typical supply voltage is 3.3v */
  128. *value = (1ULL << 32) * 3300 / 50000;
  129. *shift = 32;
  130. return IIO_VAL_FRACTIONAL_LOG2;
  131. }
  132. return -EINVAL;
  133. }
  134. static const struct iio_info ep93xx_adc_info = {
  135. .read_raw = ep93xx_read_raw,
  136. };
  137. static int ep93xx_adc_probe(struct platform_device *pdev)
  138. {
  139. int ret;
  140. struct iio_dev *iiodev;
  141. struct ep93xx_adc_priv *priv;
  142. struct clk *pclk;
  143. struct resource *res;
  144. iiodev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
  145. if (!iiodev)
  146. return -ENOMEM;
  147. priv = iio_priv(iiodev);
  148. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  149. priv->base = devm_ioremap_resource(&pdev->dev, res);
  150. if (IS_ERR(priv->base)) {
  151. dev_err(&pdev->dev, "Cannot map memory resource\n");
  152. return PTR_ERR(priv->base);
  153. }
  154. iiodev->name = dev_name(&pdev->dev);
  155. iiodev->modes = INDIO_DIRECT_MODE;
  156. iiodev->info = &ep93xx_adc_info;
  157. iiodev->num_channels = ARRAY_SIZE(ep93xx_adc_channels);
  158. iiodev->channels = ep93xx_adc_channels;
  159. priv->lastch = -1;
  160. mutex_init(&priv->lock);
  161. platform_set_drvdata(pdev, iiodev);
  162. priv->clk = devm_clk_get(&pdev->dev, NULL);
  163. if (IS_ERR(priv->clk)) {
  164. dev_err(&pdev->dev, "Cannot obtain clock\n");
  165. return PTR_ERR(priv->clk);
  166. }
  167. pclk = clk_get_parent(priv->clk);
  168. if (!pclk) {
  169. dev_warn(&pdev->dev, "Cannot obtain parent clock\n");
  170. } else {
  171. /*
  172. * This is actually a place for improvement:
  173. * EP93xx ADC supports two clock divisors -- 4 and 16,
  174. * resulting in conversion rates 3750 and 925 samples per second
  175. * with 500us or 2ms settling time respectively.
  176. * One might find this interesting enough to be configurable.
  177. */
  178. ret = clk_set_rate(priv->clk, clk_get_rate(pclk) / 16);
  179. if (ret)
  180. dev_warn(&pdev->dev, "Cannot set clock rate\n");
  181. /*
  182. * We can tolerate rate setting failure because the module should
  183. * work in any case.
  184. */
  185. }
  186. ret = clk_enable(priv->clk);
  187. if (ret) {
  188. dev_err(&pdev->dev, "Cannot enable clock\n");
  189. return ret;
  190. }
  191. ret = iio_device_register(iiodev);
  192. if (ret)
  193. clk_disable(priv->clk);
  194. return ret;
  195. }
  196. static int ep93xx_adc_remove(struct platform_device *pdev)
  197. {
  198. struct iio_dev *iiodev = platform_get_drvdata(pdev);
  199. struct ep93xx_adc_priv *priv = iio_priv(iiodev);
  200. iio_device_unregister(iiodev);
  201. clk_disable(priv->clk);
  202. return 0;
  203. }
  204. static struct platform_driver ep93xx_adc_driver = {
  205. .driver = {
  206. .name = "ep93xx-adc",
  207. },
  208. .probe = ep93xx_adc_probe,
  209. .remove = ep93xx_adc_remove,
  210. };
  211. module_platform_driver(ep93xx_adc_driver);
  212. MODULE_AUTHOR("Alexander Sverdlin <alexander.sverdlin@gmail.com>");
  213. MODULE_DESCRIPTION("Cirrus Logic EP93XX ADC driver");
  214. MODULE_LICENSE("GPL");
  215. MODULE_ALIAS("platform:ep93xx-adc");