dln2-adc.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for the Diolan DLN-2 USB-ADC adapter
  4. *
  5. * Copyright (c) 2017 Jack Andersen
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/types.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/mfd/dln2.h>
  12. #include <linux/iio/iio.h>
  13. #include <linux/iio/sysfs.h>
  14. #include <linux/iio/trigger.h>
  15. #include <linux/iio/trigger_consumer.h>
  16. #include <linux/iio/triggered_buffer.h>
  17. #include <linux/iio/buffer.h>
  18. #include <linux/iio/kfifo_buf.h>
  19. #define DLN2_ADC_MOD_NAME "dln2-adc"
  20. #define DLN2_ADC_ID 0x06
  21. #define DLN2_ADC_GET_CHANNEL_COUNT DLN2_CMD(0x01, DLN2_ADC_ID)
  22. #define DLN2_ADC_ENABLE DLN2_CMD(0x02, DLN2_ADC_ID)
  23. #define DLN2_ADC_DISABLE DLN2_CMD(0x03, DLN2_ADC_ID)
  24. #define DLN2_ADC_CHANNEL_ENABLE DLN2_CMD(0x05, DLN2_ADC_ID)
  25. #define DLN2_ADC_CHANNEL_DISABLE DLN2_CMD(0x06, DLN2_ADC_ID)
  26. #define DLN2_ADC_SET_RESOLUTION DLN2_CMD(0x08, DLN2_ADC_ID)
  27. #define DLN2_ADC_CHANNEL_GET_VAL DLN2_CMD(0x0A, DLN2_ADC_ID)
  28. #define DLN2_ADC_CHANNEL_GET_ALL_VAL DLN2_CMD(0x0B, DLN2_ADC_ID)
  29. #define DLN2_ADC_CHANNEL_SET_CFG DLN2_CMD(0x0C, DLN2_ADC_ID)
  30. #define DLN2_ADC_CHANNEL_GET_CFG DLN2_CMD(0x0D, DLN2_ADC_ID)
  31. #define DLN2_ADC_CONDITION_MET_EV DLN2_CMD(0x10, DLN2_ADC_ID)
  32. #define DLN2_ADC_EVENT_NONE 0
  33. #define DLN2_ADC_EVENT_BELOW 1
  34. #define DLN2_ADC_EVENT_LEVEL_ABOVE 2
  35. #define DLN2_ADC_EVENT_OUTSIDE 3
  36. #define DLN2_ADC_EVENT_INSIDE 4
  37. #define DLN2_ADC_EVENT_ALWAYS 5
  38. #define DLN2_ADC_MAX_CHANNELS 8
  39. #define DLN2_ADC_DATA_BITS 10
  40. /*
  41. * Plays similar role to iio_demux_table in subsystem core; except allocated
  42. * in a fixed 8-element array.
  43. */
  44. struct dln2_adc_demux_table {
  45. unsigned int from;
  46. unsigned int to;
  47. unsigned int length;
  48. };
  49. struct dln2_adc {
  50. struct platform_device *pdev;
  51. struct iio_chan_spec iio_channels[DLN2_ADC_MAX_CHANNELS + 1];
  52. int port, trigger_chan;
  53. struct iio_trigger *trig;
  54. struct mutex mutex;
  55. /* Cached sample period in milliseconds */
  56. unsigned int sample_period;
  57. /* Demux table */
  58. unsigned int demux_count;
  59. struct dln2_adc_demux_table demux[DLN2_ADC_MAX_CHANNELS];
  60. /* Precomputed timestamp padding offset and length */
  61. unsigned int ts_pad_offset, ts_pad_length;
  62. };
  63. struct dln2_adc_port_chan {
  64. u8 port;
  65. u8 chan;
  66. };
  67. struct dln2_adc_get_all_vals {
  68. __le16 channel_mask;
  69. __le16 values[DLN2_ADC_MAX_CHANNELS];
  70. };
  71. static void dln2_adc_add_demux(struct dln2_adc *dln2,
  72. unsigned int in_loc, unsigned int out_loc,
  73. unsigned int length)
  74. {
  75. struct dln2_adc_demux_table *p = dln2->demux_count ?
  76. &dln2->demux[dln2->demux_count - 1] : NULL;
  77. if (p && p->from + p->length == in_loc &&
  78. p->to + p->length == out_loc) {
  79. p->length += length;
  80. } else if (dln2->demux_count < DLN2_ADC_MAX_CHANNELS) {
  81. p = &dln2->demux[dln2->demux_count++];
  82. p->from = in_loc;
  83. p->to = out_loc;
  84. p->length = length;
  85. }
  86. }
  87. static void dln2_adc_update_demux(struct dln2_adc *dln2)
  88. {
  89. int in_ind = -1, out_ind;
  90. unsigned int in_loc = 0, out_loc = 0;
  91. struct iio_dev *indio_dev = platform_get_drvdata(dln2->pdev);
  92. /* Clear out any old demux */
  93. dln2->demux_count = 0;
  94. /* Optimize all 8-channels case */
  95. if (indio_dev->masklength &&
  96. (*indio_dev->active_scan_mask & 0xff) == 0xff) {
  97. dln2_adc_add_demux(dln2, 0, 0, 16);
  98. dln2->ts_pad_offset = 0;
  99. dln2->ts_pad_length = 0;
  100. return;
  101. }
  102. /* Build demux table from fixed 8-channels to active_scan_mask */
  103. for_each_set_bit(out_ind,
  104. indio_dev->active_scan_mask,
  105. indio_dev->masklength) {
  106. /* Handle timestamp separately */
  107. if (out_ind == DLN2_ADC_MAX_CHANNELS)
  108. break;
  109. for (++in_ind; in_ind != out_ind; ++in_ind)
  110. in_loc += 2;
  111. dln2_adc_add_demux(dln2, in_loc, out_loc, 2);
  112. out_loc += 2;
  113. in_loc += 2;
  114. }
  115. if (indio_dev->scan_timestamp) {
  116. size_t ts_offset = indio_dev->scan_bytes / sizeof(int64_t) - 1;
  117. dln2->ts_pad_offset = out_loc;
  118. dln2->ts_pad_length = ts_offset * sizeof(int64_t) - out_loc;
  119. } else {
  120. dln2->ts_pad_offset = 0;
  121. dln2->ts_pad_length = 0;
  122. }
  123. }
  124. static int dln2_adc_get_chan_count(struct dln2_adc *dln2)
  125. {
  126. int ret;
  127. u8 port = dln2->port;
  128. u8 count;
  129. int olen = sizeof(count);
  130. ret = dln2_transfer(dln2->pdev, DLN2_ADC_GET_CHANNEL_COUNT,
  131. &port, sizeof(port), &count, &olen);
  132. if (ret < 0) {
  133. dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
  134. return ret;
  135. }
  136. if (olen < sizeof(count))
  137. return -EPROTO;
  138. return count;
  139. }
  140. static int dln2_adc_set_port_resolution(struct dln2_adc *dln2)
  141. {
  142. int ret;
  143. struct dln2_adc_port_chan port_chan = {
  144. .port = dln2->port,
  145. .chan = DLN2_ADC_DATA_BITS,
  146. };
  147. ret = dln2_transfer_tx(dln2->pdev, DLN2_ADC_SET_RESOLUTION,
  148. &port_chan, sizeof(port_chan));
  149. if (ret < 0)
  150. dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
  151. return ret;
  152. }
  153. static int dln2_adc_set_chan_enabled(struct dln2_adc *dln2,
  154. int channel, bool enable)
  155. {
  156. int ret;
  157. struct dln2_adc_port_chan port_chan = {
  158. .port = dln2->port,
  159. .chan = channel,
  160. };
  161. u16 cmd = enable ? DLN2_ADC_CHANNEL_ENABLE : DLN2_ADC_CHANNEL_DISABLE;
  162. ret = dln2_transfer_tx(dln2->pdev, cmd, &port_chan, sizeof(port_chan));
  163. if (ret < 0)
  164. dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
  165. return ret;
  166. }
  167. static int dln2_adc_set_port_enabled(struct dln2_adc *dln2, bool enable,
  168. u16 *conflict_out)
  169. {
  170. int ret;
  171. u8 port = dln2->port;
  172. __le16 conflict;
  173. int olen = sizeof(conflict);
  174. u16 cmd = enable ? DLN2_ADC_ENABLE : DLN2_ADC_DISABLE;
  175. if (conflict_out)
  176. *conflict_out = 0;
  177. ret = dln2_transfer(dln2->pdev, cmd, &port, sizeof(port),
  178. &conflict, &olen);
  179. if (ret < 0) {
  180. dev_dbg(&dln2->pdev->dev, "Problem in %s(%d)\n",
  181. __func__, (int)enable);
  182. if (conflict_out && enable && olen >= sizeof(conflict))
  183. *conflict_out = le16_to_cpu(conflict);
  184. return ret;
  185. }
  186. if (enable && olen < sizeof(conflict))
  187. return -EPROTO;
  188. return ret;
  189. }
  190. static int dln2_adc_set_chan_period(struct dln2_adc *dln2,
  191. unsigned int channel, unsigned int period)
  192. {
  193. int ret;
  194. struct {
  195. struct dln2_adc_port_chan port_chan;
  196. __u8 type;
  197. __le16 period;
  198. __le16 low;
  199. __le16 high;
  200. } __packed set_cfg = {
  201. .port_chan.port = dln2->port,
  202. .port_chan.chan = channel,
  203. .type = period ? DLN2_ADC_EVENT_ALWAYS : DLN2_ADC_EVENT_NONE,
  204. .period = cpu_to_le16(period)
  205. };
  206. ret = dln2_transfer_tx(dln2->pdev, DLN2_ADC_CHANNEL_SET_CFG,
  207. &set_cfg, sizeof(set_cfg));
  208. if (ret < 0)
  209. dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
  210. return ret;
  211. }
  212. static int dln2_adc_read(struct dln2_adc *dln2, unsigned int channel)
  213. {
  214. int ret, i;
  215. u16 conflict;
  216. __le16 value;
  217. int olen = sizeof(value);
  218. struct dln2_adc_port_chan port_chan = {
  219. .port = dln2->port,
  220. .chan = channel,
  221. };
  222. ret = dln2_adc_set_chan_enabled(dln2, channel, true);
  223. if (ret < 0)
  224. return ret;
  225. ret = dln2_adc_set_port_enabled(dln2, true, &conflict);
  226. if (ret < 0) {
  227. if (conflict) {
  228. dev_err(&dln2->pdev->dev,
  229. "ADC pins conflict with mask %04X\n",
  230. (int)conflict);
  231. ret = -EBUSY;
  232. }
  233. goto disable_chan;
  234. }
  235. /*
  236. * Call GET_VAL twice due to initial zero-return immediately after
  237. * enabling channel.
  238. */
  239. for (i = 0; i < 2; ++i) {
  240. ret = dln2_transfer(dln2->pdev, DLN2_ADC_CHANNEL_GET_VAL,
  241. &port_chan, sizeof(port_chan),
  242. &value, &olen);
  243. if (ret < 0) {
  244. dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
  245. goto disable_port;
  246. }
  247. if (olen < sizeof(value)) {
  248. ret = -EPROTO;
  249. goto disable_port;
  250. }
  251. }
  252. ret = le16_to_cpu(value);
  253. disable_port:
  254. dln2_adc_set_port_enabled(dln2, false, NULL);
  255. disable_chan:
  256. dln2_adc_set_chan_enabled(dln2, channel, false);
  257. return ret;
  258. }
  259. static int dln2_adc_read_all(struct dln2_adc *dln2,
  260. struct dln2_adc_get_all_vals *get_all_vals)
  261. {
  262. int ret;
  263. __u8 port = dln2->port;
  264. int olen = sizeof(*get_all_vals);
  265. ret = dln2_transfer(dln2->pdev, DLN2_ADC_CHANNEL_GET_ALL_VAL,
  266. &port, sizeof(port), get_all_vals, &olen);
  267. if (ret < 0) {
  268. dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
  269. return ret;
  270. }
  271. if (olen < sizeof(*get_all_vals))
  272. return -EPROTO;
  273. return ret;
  274. }
  275. static int dln2_adc_read_raw(struct iio_dev *indio_dev,
  276. struct iio_chan_spec const *chan,
  277. int *val,
  278. int *val2,
  279. long mask)
  280. {
  281. int ret;
  282. unsigned int microhertz;
  283. struct dln2_adc *dln2 = iio_priv(indio_dev);
  284. switch (mask) {
  285. case IIO_CHAN_INFO_RAW:
  286. ret = iio_device_claim_direct_mode(indio_dev);
  287. if (ret < 0)
  288. return ret;
  289. mutex_lock(&dln2->mutex);
  290. ret = dln2_adc_read(dln2, chan->channel);
  291. mutex_unlock(&dln2->mutex);
  292. iio_device_release_direct_mode(indio_dev);
  293. if (ret < 0)
  294. return ret;
  295. *val = ret;
  296. return IIO_VAL_INT;
  297. case IIO_CHAN_INFO_SCALE:
  298. /*
  299. * Voltage reference is fixed at 3.3v
  300. * 3.3 / (1 << 10) * 1000000000
  301. */
  302. *val = 0;
  303. *val2 = 3222656;
  304. return IIO_VAL_INT_PLUS_NANO;
  305. case IIO_CHAN_INFO_SAMP_FREQ:
  306. if (dln2->sample_period) {
  307. microhertz = 1000000000 / dln2->sample_period;
  308. *val = microhertz / 1000000;
  309. *val2 = microhertz % 1000000;
  310. } else {
  311. *val = 0;
  312. *val2 = 0;
  313. }
  314. return IIO_VAL_INT_PLUS_MICRO;
  315. default:
  316. return -EINVAL;
  317. }
  318. }
  319. static int dln2_adc_write_raw(struct iio_dev *indio_dev,
  320. struct iio_chan_spec const *chan,
  321. int val,
  322. int val2,
  323. long mask)
  324. {
  325. int ret;
  326. unsigned int microhertz;
  327. struct dln2_adc *dln2 = iio_priv(indio_dev);
  328. switch (mask) {
  329. case IIO_CHAN_INFO_SAMP_FREQ:
  330. microhertz = 1000000 * val + val2;
  331. mutex_lock(&dln2->mutex);
  332. dln2->sample_period =
  333. microhertz ? 1000000000 / microhertz : UINT_MAX;
  334. if (dln2->sample_period > 65535) {
  335. dln2->sample_period = 65535;
  336. dev_warn(&dln2->pdev->dev,
  337. "clamping period to 65535ms\n");
  338. }
  339. /*
  340. * The first requested channel is arbitrated as a shared
  341. * trigger source, so only one event is registered with the
  342. * DLN. The event handler will then read all enabled channel
  343. * values using DLN2_ADC_CHANNEL_GET_ALL_VAL to maintain
  344. * synchronization between ADC readings.
  345. */
  346. if (dln2->trigger_chan != -1)
  347. ret = dln2_adc_set_chan_period(dln2,
  348. dln2->trigger_chan, dln2->sample_period);
  349. else
  350. ret = 0;
  351. mutex_unlock(&dln2->mutex);
  352. return ret;
  353. default:
  354. return -EINVAL;
  355. }
  356. }
  357. static int dln2_update_scan_mode(struct iio_dev *indio_dev,
  358. const unsigned long *scan_mask)
  359. {
  360. struct dln2_adc *dln2 = iio_priv(indio_dev);
  361. int chan_count = indio_dev->num_channels - 1;
  362. int ret, i, j;
  363. mutex_lock(&dln2->mutex);
  364. for (i = 0; i < chan_count; ++i) {
  365. ret = dln2_adc_set_chan_enabled(dln2, i,
  366. test_bit(i, scan_mask));
  367. if (ret < 0) {
  368. for (j = 0; j < i; ++j)
  369. dln2_adc_set_chan_enabled(dln2, j, false);
  370. mutex_unlock(&dln2->mutex);
  371. dev_err(&dln2->pdev->dev,
  372. "Unable to enable ADC channel %d\n", i);
  373. return -EBUSY;
  374. }
  375. }
  376. dln2_adc_update_demux(dln2);
  377. mutex_unlock(&dln2->mutex);
  378. return 0;
  379. }
  380. #define DLN2_ADC_CHAN(lval, idx) { \
  381. lval.type = IIO_VOLTAGE; \
  382. lval.channel = idx; \
  383. lval.indexed = 1; \
  384. lval.info_mask_separate = BIT(IIO_CHAN_INFO_RAW); \
  385. lval.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) | \
  386. BIT(IIO_CHAN_INFO_SAMP_FREQ); \
  387. lval.scan_index = idx; \
  388. lval.scan_type.sign = 'u'; \
  389. lval.scan_type.realbits = DLN2_ADC_DATA_BITS; \
  390. lval.scan_type.storagebits = 16; \
  391. lval.scan_type.endianness = IIO_LE; \
  392. }
  393. /* Assignment version of IIO_CHAN_SOFT_TIMESTAMP */
  394. #define IIO_CHAN_SOFT_TIMESTAMP_ASSIGN(lval, _si) { \
  395. lval.type = IIO_TIMESTAMP; \
  396. lval.channel = -1; \
  397. lval.scan_index = _si; \
  398. lval.scan_type.sign = 's'; \
  399. lval.scan_type.realbits = 64; \
  400. lval.scan_type.storagebits = 64; \
  401. }
  402. static const struct iio_info dln2_adc_info = {
  403. .read_raw = dln2_adc_read_raw,
  404. .write_raw = dln2_adc_write_raw,
  405. .update_scan_mode = dln2_update_scan_mode,
  406. };
  407. static irqreturn_t dln2_adc_trigger_h(int irq, void *p)
  408. {
  409. struct iio_poll_func *pf = p;
  410. struct iio_dev *indio_dev = pf->indio_dev;
  411. struct {
  412. __le16 values[DLN2_ADC_MAX_CHANNELS];
  413. int64_t timestamp_space;
  414. } data;
  415. struct dln2_adc_get_all_vals dev_data;
  416. struct dln2_adc *dln2 = iio_priv(indio_dev);
  417. const struct dln2_adc_demux_table *t;
  418. int ret, i;
  419. mutex_lock(&dln2->mutex);
  420. ret = dln2_adc_read_all(dln2, &dev_data);
  421. mutex_unlock(&dln2->mutex);
  422. if (ret < 0)
  423. goto done;
  424. /* Demux operation */
  425. for (i = 0; i < dln2->demux_count; ++i) {
  426. t = &dln2->demux[i];
  427. memcpy((void *)data.values + t->to,
  428. (void *)dev_data.values + t->from, t->length);
  429. }
  430. /* Zero padding space between values and timestamp */
  431. if (dln2->ts_pad_length)
  432. memset((void *)data.values + dln2->ts_pad_offset,
  433. 0, dln2->ts_pad_length);
  434. iio_push_to_buffers_with_timestamp(indio_dev, &data,
  435. iio_get_time_ns(indio_dev));
  436. done:
  437. iio_trigger_notify_done(indio_dev->trig);
  438. return IRQ_HANDLED;
  439. }
  440. static int dln2_adc_triggered_buffer_postenable(struct iio_dev *indio_dev)
  441. {
  442. int ret;
  443. struct dln2_adc *dln2 = iio_priv(indio_dev);
  444. u16 conflict;
  445. unsigned int trigger_chan;
  446. mutex_lock(&dln2->mutex);
  447. /* Enable ADC */
  448. ret = dln2_adc_set_port_enabled(dln2, true, &conflict);
  449. if (ret < 0) {
  450. mutex_unlock(&dln2->mutex);
  451. dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
  452. if (conflict) {
  453. dev_err(&dln2->pdev->dev,
  454. "ADC pins conflict with mask %04X\n",
  455. (int)conflict);
  456. ret = -EBUSY;
  457. }
  458. return ret;
  459. }
  460. /* Assign trigger channel based on first enabled channel */
  461. trigger_chan = find_first_bit(indio_dev->active_scan_mask,
  462. indio_dev->masklength);
  463. if (trigger_chan < DLN2_ADC_MAX_CHANNELS) {
  464. dln2->trigger_chan = trigger_chan;
  465. ret = dln2_adc_set_chan_period(dln2, dln2->trigger_chan,
  466. dln2->sample_period);
  467. mutex_unlock(&dln2->mutex);
  468. if (ret < 0) {
  469. dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
  470. return ret;
  471. }
  472. } else {
  473. dln2->trigger_chan = -1;
  474. mutex_unlock(&dln2->mutex);
  475. }
  476. return 0;
  477. }
  478. static int dln2_adc_triggered_buffer_predisable(struct iio_dev *indio_dev)
  479. {
  480. int ret;
  481. struct dln2_adc *dln2 = iio_priv(indio_dev);
  482. mutex_lock(&dln2->mutex);
  483. /* Disable trigger channel */
  484. if (dln2->trigger_chan != -1) {
  485. dln2_adc_set_chan_period(dln2, dln2->trigger_chan, 0);
  486. dln2->trigger_chan = -1;
  487. }
  488. /* Disable ADC */
  489. ret = dln2_adc_set_port_enabled(dln2, false, NULL);
  490. mutex_unlock(&dln2->mutex);
  491. if (ret < 0)
  492. dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
  493. return ret;
  494. }
  495. static const struct iio_buffer_setup_ops dln2_adc_buffer_setup_ops = {
  496. .postenable = dln2_adc_triggered_buffer_postenable,
  497. .predisable = dln2_adc_triggered_buffer_predisable,
  498. };
  499. static void dln2_adc_event(struct platform_device *pdev, u16 echo,
  500. const void *data, int len)
  501. {
  502. struct iio_dev *indio_dev = platform_get_drvdata(pdev);
  503. struct dln2_adc *dln2 = iio_priv(indio_dev);
  504. /* Called via URB completion handler */
  505. iio_trigger_poll(dln2->trig);
  506. }
  507. static int dln2_adc_probe(struct platform_device *pdev)
  508. {
  509. struct device *dev = &pdev->dev;
  510. struct dln2_adc *dln2;
  511. struct dln2_platform_data *pdata = dev_get_platdata(&pdev->dev);
  512. struct iio_dev *indio_dev;
  513. int i, ret, chans;
  514. indio_dev = devm_iio_device_alloc(dev, sizeof(*dln2));
  515. if (!indio_dev) {
  516. dev_err(dev, "failed allocating iio device\n");
  517. return -ENOMEM;
  518. }
  519. dln2 = iio_priv(indio_dev);
  520. dln2->pdev = pdev;
  521. dln2->port = pdata->port;
  522. dln2->trigger_chan = -1;
  523. mutex_init(&dln2->mutex);
  524. platform_set_drvdata(pdev, indio_dev);
  525. ret = dln2_adc_set_port_resolution(dln2);
  526. if (ret < 0) {
  527. dev_err(dev, "failed to set ADC resolution to 10 bits\n");
  528. return ret;
  529. }
  530. chans = dln2_adc_get_chan_count(dln2);
  531. if (chans < 0) {
  532. dev_err(dev, "failed to get channel count: %d\n", chans);
  533. return chans;
  534. }
  535. if (chans > DLN2_ADC_MAX_CHANNELS) {
  536. chans = DLN2_ADC_MAX_CHANNELS;
  537. dev_warn(dev, "clamping channels to %d\n",
  538. DLN2_ADC_MAX_CHANNELS);
  539. }
  540. for (i = 0; i < chans; ++i)
  541. DLN2_ADC_CHAN(dln2->iio_channels[i], i)
  542. IIO_CHAN_SOFT_TIMESTAMP_ASSIGN(dln2->iio_channels[i], i);
  543. indio_dev->name = DLN2_ADC_MOD_NAME;
  544. indio_dev->info = &dln2_adc_info;
  545. indio_dev->modes = INDIO_DIRECT_MODE;
  546. indio_dev->channels = dln2->iio_channels;
  547. indio_dev->num_channels = chans + 1;
  548. indio_dev->setup_ops = &dln2_adc_buffer_setup_ops;
  549. dln2->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
  550. indio_dev->name, indio_dev->id);
  551. if (!dln2->trig) {
  552. dev_err(dev, "failed to allocate trigger\n");
  553. return -ENOMEM;
  554. }
  555. iio_trigger_set_drvdata(dln2->trig, dln2);
  556. ret = devm_iio_trigger_register(dev, dln2->trig);
  557. if (ret) {
  558. dev_err(dev, "failed to register trigger: %d\n", ret);
  559. return ret;
  560. }
  561. iio_trigger_set_immutable(indio_dev, dln2->trig);
  562. ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
  563. dln2_adc_trigger_h,
  564. &dln2_adc_buffer_setup_ops);
  565. if (ret) {
  566. dev_err(dev, "failed to allocate triggered buffer: %d\n", ret);
  567. return ret;
  568. }
  569. ret = dln2_register_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV,
  570. dln2_adc_event);
  571. if (ret) {
  572. dev_err(dev, "failed to setup DLN2 periodic event: %d\n", ret);
  573. return ret;
  574. }
  575. ret = iio_device_register(indio_dev);
  576. if (ret) {
  577. dev_err(dev, "failed to register iio device: %d\n", ret);
  578. goto unregister_event;
  579. }
  580. return ret;
  581. unregister_event:
  582. dln2_unregister_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV);
  583. return ret;
  584. }
  585. static int dln2_adc_remove(struct platform_device *pdev)
  586. {
  587. struct iio_dev *indio_dev = platform_get_drvdata(pdev);
  588. iio_device_unregister(indio_dev);
  589. dln2_unregister_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV);
  590. return 0;
  591. }
  592. static struct platform_driver dln2_adc_driver = {
  593. .driver.name = DLN2_ADC_MOD_NAME,
  594. .probe = dln2_adc_probe,
  595. .remove = dln2_adc_remove,
  596. };
  597. module_platform_driver(dln2_adc_driver);
  598. MODULE_AUTHOR("Jack Andersen <jackoalan@gmail.com");
  599. MODULE_DESCRIPTION("Driver for the Diolan DLN2 ADC interface");
  600. MODULE_LICENSE("GPL v2");
  601. MODULE_ALIAS("platform:dln2-adc");