cpcap-adc.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2017 Tony Lindgren <tony@atomide.com>
  4. *
  5. * Rewritten for Linux IIO framework with some code based on
  6. * earlier driver found in the Motorola Linux kernel:
  7. *
  8. * Copyright (C) 2009-2010 Motorola, Inc.
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/device.h>
  12. #include <linux/err.h>
  13. #include <linux/init.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/mod_devicetable.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/property.h>
  20. #include <linux/regmap.h>
  21. #include <linux/iio/buffer.h>
  22. #include <linux/iio/driver.h>
  23. #include <linux/iio/iio.h>
  24. #include <linux/iio/kfifo_buf.h>
  25. #include <linux/mfd/motorola-cpcap.h>
  26. /* Register CPCAP_REG_ADCC1 bits */
  27. #define CPCAP_BIT_ADEN_AUTO_CLR BIT(15) /* Currently unused */
  28. #define CPCAP_BIT_CAL_MODE BIT(14) /* Set with BIT_RAND0 */
  29. #define CPCAP_BIT_ADC_CLK_SEL1 BIT(13) /* Currently unused */
  30. #define CPCAP_BIT_ADC_CLK_SEL0 BIT(12) /* Currently unused */
  31. #define CPCAP_BIT_ATOX BIT(11)
  32. #define CPCAP_BIT_ATO3 BIT(10)
  33. #define CPCAP_BIT_ATO2 BIT(9)
  34. #define CPCAP_BIT_ATO1 BIT(8)
  35. #define CPCAP_BIT_ATO0 BIT(7)
  36. #define CPCAP_BIT_ADA2 BIT(6)
  37. #define CPCAP_BIT_ADA1 BIT(5)
  38. #define CPCAP_BIT_ADA0 BIT(4)
  39. #define CPCAP_BIT_AD_SEL1 BIT(3) /* Set for bank1 */
  40. #define CPCAP_BIT_RAND1 BIT(2) /* Set for channel 16 & 17 */
  41. #define CPCAP_BIT_RAND0 BIT(1) /* Set with CAL_MODE */
  42. #define CPCAP_BIT_ADEN BIT(0) /* Currently unused */
  43. #define CPCAP_REG_ADCC1_DEFAULTS (CPCAP_BIT_ADEN_AUTO_CLR | \
  44. CPCAP_BIT_ADC_CLK_SEL0 | \
  45. CPCAP_BIT_RAND1)
  46. /* Register CPCAP_REG_ADCC2 bits */
  47. #define CPCAP_BIT_CAL_FACTOR_ENABLE BIT(15) /* Currently unused */
  48. #define CPCAP_BIT_BATDETB_EN BIT(14) /* Currently unused */
  49. #define CPCAP_BIT_ADTRIG_ONESHOT BIT(13) /* Set for !TIMING_IMM */
  50. #define CPCAP_BIT_ASC BIT(12) /* Set for TIMING_IMM */
  51. #define CPCAP_BIT_ATOX_PS_FACTOR BIT(11)
  52. #define CPCAP_BIT_ADC_PS_FACTOR1 BIT(10)
  53. #define CPCAP_BIT_ADC_PS_FACTOR0 BIT(9)
  54. #define CPCAP_BIT_AD4_SELECT BIT(8) /* Currently unused */
  55. #define CPCAP_BIT_ADC_BUSY BIT(7) /* Currently unused */
  56. #define CPCAP_BIT_THERMBIAS_EN BIT(6) /* Bias for AD0_BATTDETB */
  57. #define CPCAP_BIT_ADTRIG_DIS BIT(5) /* Disable interrupt */
  58. #define CPCAP_BIT_LIADC BIT(4) /* Currently unused */
  59. #define CPCAP_BIT_TS_REFEN BIT(3) /* Currently unused */
  60. #define CPCAP_BIT_TS_M2 BIT(2) /* Currently unused */
  61. #define CPCAP_BIT_TS_M1 BIT(1) /* Currently unused */
  62. #define CPCAP_BIT_TS_M0 BIT(0) /* Currently unused */
  63. #define CPCAP_REG_ADCC2_DEFAULTS (CPCAP_BIT_AD4_SELECT | \
  64. CPCAP_BIT_ADTRIG_DIS | \
  65. CPCAP_BIT_LIADC | \
  66. CPCAP_BIT_TS_M2 | \
  67. CPCAP_BIT_TS_M1)
  68. #define CPCAP_MAX_TEMP_LVL 27
  69. #define CPCAP_FOUR_POINT_TWO_ADC 801
  70. #define ST_ADC_CAL_CHRGI_HIGH_THRESHOLD 530
  71. #define ST_ADC_CAL_CHRGI_LOW_THRESHOLD 494
  72. #define ST_ADC_CAL_BATTI_HIGH_THRESHOLD 530
  73. #define ST_ADC_CAL_BATTI_LOW_THRESHOLD 494
  74. #define ST_ADC_CALIBRATE_DIFF_THRESHOLD 3
  75. #define CPCAP_ADC_MAX_RETRIES 5 /* Calibration */
  76. /*
  77. * struct cpcap_adc_ato - timing settings for cpcap adc
  78. *
  79. * Unfortunately no cpcap documentation available, please document when
  80. * using these.
  81. */
  82. struct cpcap_adc_ato {
  83. unsigned short ato_in;
  84. unsigned short atox_in;
  85. unsigned short adc_ps_factor_in;
  86. unsigned short atox_ps_factor_in;
  87. unsigned short ato_out;
  88. unsigned short atox_out;
  89. unsigned short adc_ps_factor_out;
  90. unsigned short atox_ps_factor_out;
  91. };
  92. /**
  93. * struct cpcap-adc - cpcap adc device driver data
  94. * @reg: cpcap regmap
  95. * @dev: struct device
  96. * @vendor: cpcap vendor
  97. * @irq: interrupt
  98. * @lock: mutex
  99. * @ato: request timings
  100. * @wq_data_avail: work queue
  101. * @done: work done
  102. */
  103. struct cpcap_adc {
  104. struct regmap *reg;
  105. struct device *dev;
  106. u16 vendor;
  107. int irq;
  108. struct mutex lock; /* ADC register access lock */
  109. const struct cpcap_adc_ato *ato;
  110. wait_queue_head_t wq_data_avail;
  111. bool done;
  112. };
  113. /*
  114. * enum cpcap_adc_channel - cpcap adc channels
  115. */
  116. enum cpcap_adc_channel {
  117. /* Bank0 channels */
  118. CPCAP_ADC_AD0, /* Battery temperature */
  119. CPCAP_ADC_BATTP, /* Battery voltage */
  120. CPCAP_ADC_VBUS, /* USB VBUS voltage */
  121. CPCAP_ADC_AD3, /* Die temperature when charging */
  122. CPCAP_ADC_BPLUS_AD4, /* Another battery or system voltage */
  123. CPCAP_ADC_CHG_ISENSE, /* Calibrated charge current */
  124. CPCAP_ADC_BATTI, /* Calibrated system current */
  125. CPCAP_ADC_USB_ID, /* USB OTG ID, unused on droid 4? */
  126. /* Bank1 channels */
  127. CPCAP_ADC_AD8, /* Seems unused */
  128. CPCAP_ADC_AD9, /* Seems unused */
  129. CPCAP_ADC_LICELL, /* Maybe system voltage? Always 3V */
  130. CPCAP_ADC_HV_BATTP, /* Another battery detection? */
  131. CPCAP_ADC_TSX1_AD12, /* Seems unused, for touchscreen? */
  132. CPCAP_ADC_TSX2_AD13, /* Seems unused, for touchscreen? */
  133. CPCAP_ADC_TSY1_AD14, /* Seems unused, for touchscreen? */
  134. CPCAP_ADC_TSY2_AD15, /* Seems unused, for touchscreen? */
  135. /* Remuxed channels using bank0 entries */
  136. CPCAP_ADC_BATTP_PI16, /* Alternative mux mode for BATTP */
  137. CPCAP_ADC_BATTI_PI17, /* Alternative mux mode for BATTI */
  138. CPCAP_ADC_CHANNEL_NUM,
  139. };
  140. /*
  141. * enum cpcap_adc_timing - cpcap adc timing options
  142. *
  143. * CPCAP_ADC_TIMING_IMM seems to be immediate with no timings.
  144. * Please document when using.
  145. */
  146. enum cpcap_adc_timing {
  147. CPCAP_ADC_TIMING_IMM,
  148. CPCAP_ADC_TIMING_IN,
  149. CPCAP_ADC_TIMING_OUT,
  150. };
  151. /**
  152. * struct cpcap_adc_phasing_tbl - cpcap phasing table
  153. * @offset: offset in the phasing table
  154. * @multiplier: multiplier in the phasing table
  155. * @divider: divider in the phasing table
  156. * @min: minimum value
  157. * @max: maximum value
  158. */
  159. struct cpcap_adc_phasing_tbl {
  160. short offset;
  161. unsigned short multiplier;
  162. unsigned short divider;
  163. short min;
  164. short max;
  165. };
  166. /**
  167. * struct cpcap_adc_conversion_tbl - cpcap conversion table
  168. * @conv_type: conversion type
  169. * @align_offset: align offset
  170. * @conv_offset: conversion offset
  171. * @cal_offset: calibration offset
  172. * @multiplier: conversion multiplier
  173. * @divider: conversion divider
  174. */
  175. struct cpcap_adc_conversion_tbl {
  176. enum iio_chan_info_enum conv_type;
  177. int align_offset;
  178. int conv_offset;
  179. int cal_offset;
  180. int multiplier;
  181. int divider;
  182. };
  183. /**
  184. * struct cpcap_adc_request - cpcap adc request
  185. * @channel: request channel
  186. * @phase_tbl: channel phasing table
  187. * @conv_tbl: channel conversion table
  188. * @bank_index: channel index within the bank
  189. * @timing: timing settings
  190. * @result: result
  191. */
  192. struct cpcap_adc_request {
  193. int channel;
  194. const struct cpcap_adc_phasing_tbl *phase_tbl;
  195. const struct cpcap_adc_conversion_tbl *conv_tbl;
  196. int bank_index;
  197. enum cpcap_adc_timing timing;
  198. int result;
  199. };
  200. /* Phasing table for channels. Note that channels 16 & 17 use BATTP and BATTI */
  201. static const struct cpcap_adc_phasing_tbl bank_phasing[] = {
  202. /* Bank0 */
  203. [CPCAP_ADC_AD0] = {0, 0x80, 0x80, 0, 1023},
  204. [CPCAP_ADC_BATTP] = {0, 0x80, 0x80, 0, 1023},
  205. [CPCAP_ADC_VBUS] = {0, 0x80, 0x80, 0, 1023},
  206. [CPCAP_ADC_AD3] = {0, 0x80, 0x80, 0, 1023},
  207. [CPCAP_ADC_BPLUS_AD4] = {0, 0x80, 0x80, 0, 1023},
  208. [CPCAP_ADC_CHG_ISENSE] = {0, 0x80, 0x80, -512, 511},
  209. [CPCAP_ADC_BATTI] = {0, 0x80, 0x80, -512, 511},
  210. [CPCAP_ADC_USB_ID] = {0, 0x80, 0x80, 0, 1023},
  211. /* Bank1 */
  212. [CPCAP_ADC_AD8] = {0, 0x80, 0x80, 0, 1023},
  213. [CPCAP_ADC_AD9] = {0, 0x80, 0x80, 0, 1023},
  214. [CPCAP_ADC_LICELL] = {0, 0x80, 0x80, 0, 1023},
  215. [CPCAP_ADC_HV_BATTP] = {0, 0x80, 0x80, 0, 1023},
  216. [CPCAP_ADC_TSX1_AD12] = {0, 0x80, 0x80, 0, 1023},
  217. [CPCAP_ADC_TSX2_AD13] = {0, 0x80, 0x80, 0, 1023},
  218. [CPCAP_ADC_TSY1_AD14] = {0, 0x80, 0x80, 0, 1023},
  219. [CPCAP_ADC_TSY2_AD15] = {0, 0x80, 0x80, 0, 1023},
  220. };
  221. /*
  222. * Conversion table for channels. Updated during init based on calibration.
  223. * Here too channels 16 & 17 use BATTP and BATTI.
  224. */
  225. static struct cpcap_adc_conversion_tbl bank_conversion[] = {
  226. /* Bank0 */
  227. [CPCAP_ADC_AD0] = {
  228. IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 1, 1,
  229. },
  230. [CPCAP_ADC_BATTP] = {
  231. IIO_CHAN_INFO_PROCESSED, 0, 2400, 0, 2300, 1023,
  232. },
  233. [CPCAP_ADC_VBUS] = {
  234. IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 10000, 1023,
  235. },
  236. [CPCAP_ADC_AD3] = {
  237. IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 1, 1,
  238. },
  239. [CPCAP_ADC_BPLUS_AD4] = {
  240. IIO_CHAN_INFO_PROCESSED, 0, 2400, 0, 2300, 1023,
  241. },
  242. [CPCAP_ADC_CHG_ISENSE] = {
  243. IIO_CHAN_INFO_PROCESSED, -512, 2, 0, 5000, 1023,
  244. },
  245. [CPCAP_ADC_BATTI] = {
  246. IIO_CHAN_INFO_PROCESSED, -512, 2, 0, 5000, 1023,
  247. },
  248. [CPCAP_ADC_USB_ID] = {
  249. IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
  250. },
  251. /* Bank1 */
  252. [CPCAP_ADC_AD8] = {
  253. IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
  254. },
  255. [CPCAP_ADC_AD9] = {
  256. IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
  257. },
  258. [CPCAP_ADC_LICELL] = {
  259. IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 3400, 1023,
  260. },
  261. [CPCAP_ADC_HV_BATTP] = {
  262. IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
  263. },
  264. [CPCAP_ADC_TSX1_AD12] = {
  265. IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
  266. },
  267. [CPCAP_ADC_TSX2_AD13] = {
  268. IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
  269. },
  270. [CPCAP_ADC_TSY1_AD14] = {
  271. IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
  272. },
  273. [CPCAP_ADC_TSY2_AD15] = {
  274. IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
  275. },
  276. };
  277. /*
  278. * Temperature lookup table of register values to milliCelcius.
  279. * REVISIT: Check the duplicate 0x3ff entry in a freezer
  280. */
  281. static const int temp_map[CPCAP_MAX_TEMP_LVL][2] = {
  282. { 0x03ff, -40000 },
  283. { 0x03ff, -35000 },
  284. { 0x03ef, -30000 },
  285. { 0x03b2, -25000 },
  286. { 0x036c, -20000 },
  287. { 0x0320, -15000 },
  288. { 0x02d0, -10000 },
  289. { 0x027f, -5000 },
  290. { 0x022f, 0 },
  291. { 0x01e4, 5000 },
  292. { 0x019f, 10000 },
  293. { 0x0161, 15000 },
  294. { 0x012b, 20000 },
  295. { 0x00fc, 25000 },
  296. { 0x00d4, 30000 },
  297. { 0x00b2, 35000 },
  298. { 0x0095, 40000 },
  299. { 0x007d, 45000 },
  300. { 0x0069, 50000 },
  301. { 0x0059, 55000 },
  302. { 0x004b, 60000 },
  303. { 0x003f, 65000 },
  304. { 0x0036, 70000 },
  305. { 0x002e, 75000 },
  306. { 0x0027, 80000 },
  307. { 0x0022, 85000 },
  308. { 0x001d, 90000 },
  309. };
  310. #define CPCAP_CHAN(_type, _index, _address, _datasheet_name) { \
  311. .type = (_type), \
  312. .address = (_address), \
  313. .indexed = 1, \
  314. .channel = (_index), \
  315. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  316. BIT(IIO_CHAN_INFO_PROCESSED), \
  317. .scan_index = (_index), \
  318. .scan_type = { \
  319. .sign = 'u', \
  320. .realbits = 10, \
  321. .storagebits = 16, \
  322. .endianness = IIO_CPU, \
  323. }, \
  324. .datasheet_name = (_datasheet_name), \
  325. }
  326. /*
  327. * The datasheet names are from Motorola mapphone Linux kernel except
  328. * for the last two which might be uncalibrated charge voltage and
  329. * current.
  330. */
  331. static const struct iio_chan_spec cpcap_adc_channels[] = {
  332. /* Bank0 */
  333. CPCAP_CHAN(IIO_TEMP, 0, CPCAP_REG_ADCD0, "battdetb"),
  334. CPCAP_CHAN(IIO_VOLTAGE, 1, CPCAP_REG_ADCD1, "battp"),
  335. CPCAP_CHAN(IIO_VOLTAGE, 2, CPCAP_REG_ADCD2, "vbus"),
  336. CPCAP_CHAN(IIO_TEMP, 3, CPCAP_REG_ADCD3, "ad3"),
  337. CPCAP_CHAN(IIO_VOLTAGE, 4, CPCAP_REG_ADCD4, "ad4"),
  338. CPCAP_CHAN(IIO_CURRENT, 5, CPCAP_REG_ADCD5, "chg_isense"),
  339. CPCAP_CHAN(IIO_CURRENT, 6, CPCAP_REG_ADCD6, "batti"),
  340. CPCAP_CHAN(IIO_VOLTAGE, 7, CPCAP_REG_ADCD7, "usb_id"),
  341. /* Bank1 */
  342. CPCAP_CHAN(IIO_CURRENT, 8, CPCAP_REG_ADCD0, "ad8"),
  343. CPCAP_CHAN(IIO_VOLTAGE, 9, CPCAP_REG_ADCD1, "ad9"),
  344. CPCAP_CHAN(IIO_VOLTAGE, 10, CPCAP_REG_ADCD2, "licell"),
  345. CPCAP_CHAN(IIO_VOLTAGE, 11, CPCAP_REG_ADCD3, "hv_battp"),
  346. CPCAP_CHAN(IIO_VOLTAGE, 12, CPCAP_REG_ADCD4, "tsx1_ad12"),
  347. CPCAP_CHAN(IIO_VOLTAGE, 13, CPCAP_REG_ADCD5, "tsx2_ad13"),
  348. CPCAP_CHAN(IIO_VOLTAGE, 14, CPCAP_REG_ADCD6, "tsy1_ad14"),
  349. CPCAP_CHAN(IIO_VOLTAGE, 15, CPCAP_REG_ADCD7, "tsy2_ad15"),
  350. /* There are two registers with multiplexed functionality */
  351. CPCAP_CHAN(IIO_VOLTAGE, 16, CPCAP_REG_ADCD0, "chg_vsense"),
  352. CPCAP_CHAN(IIO_CURRENT, 17, CPCAP_REG_ADCD1, "batti2"),
  353. };
  354. static irqreturn_t cpcap_adc_irq_thread(int irq, void *data)
  355. {
  356. struct iio_dev *indio_dev = data;
  357. struct cpcap_adc *ddata = iio_priv(indio_dev);
  358. int error;
  359. error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
  360. CPCAP_BIT_ADTRIG_DIS,
  361. CPCAP_BIT_ADTRIG_DIS);
  362. if (error)
  363. return IRQ_NONE;
  364. ddata->done = true;
  365. wake_up_interruptible(&ddata->wq_data_avail);
  366. return IRQ_HANDLED;
  367. }
  368. /* ADC calibration functions */
  369. static void cpcap_adc_setup_calibrate(struct cpcap_adc *ddata,
  370. enum cpcap_adc_channel chan)
  371. {
  372. unsigned int value = 0;
  373. unsigned long timeout = jiffies + msecs_to_jiffies(3000);
  374. int error;
  375. if ((chan != CPCAP_ADC_CHG_ISENSE) &&
  376. (chan != CPCAP_ADC_BATTI))
  377. return;
  378. value |= CPCAP_BIT_CAL_MODE | CPCAP_BIT_RAND0;
  379. value |= ((chan << 4) &
  380. (CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 | CPCAP_BIT_ADA0));
  381. error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1,
  382. CPCAP_BIT_CAL_MODE | CPCAP_BIT_ATOX |
  383. CPCAP_BIT_ATO3 | CPCAP_BIT_ATO2 |
  384. CPCAP_BIT_ATO1 | CPCAP_BIT_ATO0 |
  385. CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 |
  386. CPCAP_BIT_ADA0 | CPCAP_BIT_AD_SEL1 |
  387. CPCAP_BIT_RAND1 | CPCAP_BIT_RAND0,
  388. value);
  389. if (error)
  390. return;
  391. error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
  392. CPCAP_BIT_ATOX_PS_FACTOR |
  393. CPCAP_BIT_ADC_PS_FACTOR1 |
  394. CPCAP_BIT_ADC_PS_FACTOR0,
  395. 0);
  396. if (error)
  397. return;
  398. error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
  399. CPCAP_BIT_ADTRIG_DIS,
  400. CPCAP_BIT_ADTRIG_DIS);
  401. if (error)
  402. return;
  403. error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
  404. CPCAP_BIT_ASC,
  405. CPCAP_BIT_ASC);
  406. if (error)
  407. return;
  408. do {
  409. schedule_timeout_uninterruptible(1);
  410. error = regmap_read(ddata->reg, CPCAP_REG_ADCC2, &value);
  411. if (error)
  412. return;
  413. } while ((value & CPCAP_BIT_ASC) && time_before(jiffies, timeout));
  414. if (value & CPCAP_BIT_ASC)
  415. dev_err(ddata->dev,
  416. "Timeout waiting for calibration to complete\n");
  417. error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1,
  418. CPCAP_BIT_CAL_MODE, 0);
  419. if (error)
  420. return;
  421. }
  422. static int cpcap_adc_calibrate_one(struct cpcap_adc *ddata,
  423. int channel,
  424. u16 calibration_register,
  425. int lower_threshold,
  426. int upper_threshold)
  427. {
  428. unsigned int calibration_data[2];
  429. unsigned short cal_data_diff;
  430. int i, error;
  431. for (i = 0; i < CPCAP_ADC_MAX_RETRIES; i++) {
  432. calibration_data[0] = 0;
  433. calibration_data[1] = 0;
  434. cal_data_diff = 0;
  435. cpcap_adc_setup_calibrate(ddata, channel);
  436. error = regmap_read(ddata->reg, calibration_register,
  437. &calibration_data[0]);
  438. if (error)
  439. return error;
  440. cpcap_adc_setup_calibrate(ddata, channel);
  441. error = regmap_read(ddata->reg, calibration_register,
  442. &calibration_data[1]);
  443. if (error)
  444. return error;
  445. if (calibration_data[0] > calibration_data[1])
  446. cal_data_diff =
  447. calibration_data[0] - calibration_data[1];
  448. else
  449. cal_data_diff =
  450. calibration_data[1] - calibration_data[0];
  451. if (((calibration_data[1] >= lower_threshold) &&
  452. (calibration_data[1] <= upper_threshold) &&
  453. (cal_data_diff <= ST_ADC_CALIBRATE_DIFF_THRESHOLD)) ||
  454. (ddata->vendor == CPCAP_VENDOR_TI)) {
  455. bank_conversion[channel].cal_offset =
  456. ((short)calibration_data[1] * -1) + 512;
  457. dev_dbg(ddata->dev, "ch%i calibration complete: %i\n",
  458. channel, bank_conversion[channel].cal_offset);
  459. break;
  460. }
  461. usleep_range(5000, 10000);
  462. }
  463. return 0;
  464. }
  465. static int cpcap_adc_calibrate(struct cpcap_adc *ddata)
  466. {
  467. int error;
  468. error = cpcap_adc_calibrate_one(ddata, CPCAP_ADC_CHG_ISENSE,
  469. CPCAP_REG_ADCAL1,
  470. ST_ADC_CAL_CHRGI_LOW_THRESHOLD,
  471. ST_ADC_CAL_CHRGI_HIGH_THRESHOLD);
  472. if (error)
  473. return error;
  474. error = cpcap_adc_calibrate_one(ddata, CPCAP_ADC_BATTI,
  475. CPCAP_REG_ADCAL2,
  476. ST_ADC_CAL_BATTI_LOW_THRESHOLD,
  477. ST_ADC_CAL_BATTI_HIGH_THRESHOLD);
  478. if (error)
  479. return error;
  480. return 0;
  481. }
  482. /* ADC setup, read and scale functions */
  483. static void cpcap_adc_setup_bank(struct cpcap_adc *ddata,
  484. struct cpcap_adc_request *req)
  485. {
  486. const struct cpcap_adc_ato *ato = ddata->ato;
  487. unsigned short value1 = 0;
  488. unsigned short value2 = 0;
  489. int error;
  490. if (!ato)
  491. return;
  492. switch (req->channel) {
  493. case CPCAP_ADC_AD0:
  494. value2 |= CPCAP_BIT_THERMBIAS_EN;
  495. error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
  496. CPCAP_BIT_THERMBIAS_EN,
  497. value2);
  498. if (error)
  499. return;
  500. usleep_range(800, 1000);
  501. break;
  502. case CPCAP_ADC_AD8 ... CPCAP_ADC_TSY2_AD15:
  503. value1 |= CPCAP_BIT_AD_SEL1;
  504. break;
  505. case CPCAP_ADC_BATTP_PI16 ... CPCAP_ADC_BATTI_PI17:
  506. value1 |= CPCAP_BIT_RAND1;
  507. default:
  508. break;
  509. }
  510. switch (req->timing) {
  511. case CPCAP_ADC_TIMING_IN:
  512. value1 |= ato->ato_in;
  513. value1 |= ato->atox_in;
  514. value2 |= ato->adc_ps_factor_in;
  515. value2 |= ato->atox_ps_factor_in;
  516. break;
  517. case CPCAP_ADC_TIMING_OUT:
  518. value1 |= ato->ato_out;
  519. value1 |= ato->atox_out;
  520. value2 |= ato->adc_ps_factor_out;
  521. value2 |= ato->atox_ps_factor_out;
  522. break;
  523. case CPCAP_ADC_TIMING_IMM:
  524. default:
  525. break;
  526. }
  527. error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1,
  528. CPCAP_BIT_CAL_MODE | CPCAP_BIT_ATOX |
  529. CPCAP_BIT_ATO3 | CPCAP_BIT_ATO2 |
  530. CPCAP_BIT_ATO1 | CPCAP_BIT_ATO0 |
  531. CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 |
  532. CPCAP_BIT_ADA0 | CPCAP_BIT_AD_SEL1 |
  533. CPCAP_BIT_RAND1 | CPCAP_BIT_RAND0,
  534. value1);
  535. if (error)
  536. return;
  537. error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
  538. CPCAP_BIT_ATOX_PS_FACTOR |
  539. CPCAP_BIT_ADC_PS_FACTOR1 |
  540. CPCAP_BIT_ADC_PS_FACTOR0 |
  541. CPCAP_BIT_THERMBIAS_EN,
  542. value2);
  543. if (error)
  544. return;
  545. if (req->timing == CPCAP_ADC_TIMING_IMM) {
  546. error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
  547. CPCAP_BIT_ADTRIG_DIS,
  548. CPCAP_BIT_ADTRIG_DIS);
  549. if (error)
  550. return;
  551. error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
  552. CPCAP_BIT_ASC,
  553. CPCAP_BIT_ASC);
  554. if (error)
  555. return;
  556. } else {
  557. error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
  558. CPCAP_BIT_ADTRIG_ONESHOT,
  559. CPCAP_BIT_ADTRIG_ONESHOT);
  560. if (error)
  561. return;
  562. error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
  563. CPCAP_BIT_ADTRIG_DIS, 0);
  564. if (error)
  565. return;
  566. }
  567. }
  568. static int cpcap_adc_start_bank(struct cpcap_adc *ddata,
  569. struct cpcap_adc_request *req)
  570. {
  571. int i, error;
  572. req->timing = CPCAP_ADC_TIMING_IMM;
  573. ddata->done = false;
  574. for (i = 0; i < CPCAP_ADC_MAX_RETRIES; i++) {
  575. cpcap_adc_setup_bank(ddata, req);
  576. error = wait_event_interruptible_timeout(ddata->wq_data_avail,
  577. ddata->done,
  578. msecs_to_jiffies(50));
  579. if (error > 0)
  580. return 0;
  581. if (error == 0) {
  582. error = -ETIMEDOUT;
  583. continue;
  584. }
  585. if (error < 0)
  586. return error;
  587. }
  588. return error;
  589. }
  590. static int cpcap_adc_stop_bank(struct cpcap_adc *ddata)
  591. {
  592. int error;
  593. error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1,
  594. 0xffff,
  595. CPCAP_REG_ADCC1_DEFAULTS);
  596. if (error)
  597. return error;
  598. return regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
  599. 0xffff,
  600. CPCAP_REG_ADCC2_DEFAULTS);
  601. }
  602. static void cpcap_adc_phase(struct cpcap_adc_request *req)
  603. {
  604. const struct cpcap_adc_conversion_tbl *conv_tbl = req->conv_tbl;
  605. const struct cpcap_adc_phasing_tbl *phase_tbl = req->phase_tbl;
  606. int index = req->channel;
  607. /* Remuxed channels 16 and 17 use BATTP and BATTI entries */
  608. switch (req->channel) {
  609. case CPCAP_ADC_BATTP:
  610. case CPCAP_ADC_BATTP_PI16:
  611. index = req->bank_index;
  612. req->result -= phase_tbl[index].offset;
  613. req->result -= CPCAP_FOUR_POINT_TWO_ADC;
  614. req->result *= phase_tbl[index].multiplier;
  615. if (phase_tbl[index].divider == 0)
  616. return;
  617. req->result /= phase_tbl[index].divider;
  618. req->result += CPCAP_FOUR_POINT_TWO_ADC;
  619. break;
  620. case CPCAP_ADC_BATTI_PI17:
  621. index = req->bank_index;
  622. fallthrough;
  623. default:
  624. req->result += conv_tbl[index].cal_offset;
  625. req->result += conv_tbl[index].align_offset;
  626. req->result *= phase_tbl[index].multiplier;
  627. if (phase_tbl[index].divider == 0)
  628. return;
  629. req->result /= phase_tbl[index].divider;
  630. req->result += phase_tbl[index].offset;
  631. break;
  632. }
  633. if (req->result < phase_tbl[index].min)
  634. req->result = phase_tbl[index].min;
  635. else if (req->result > phase_tbl[index].max)
  636. req->result = phase_tbl[index].max;
  637. }
  638. /* Looks up temperatures in a table and calculates averages if needed */
  639. static int cpcap_adc_table_to_millicelcius(unsigned short value)
  640. {
  641. int i, result = 0, alpha;
  642. if (value <= temp_map[CPCAP_MAX_TEMP_LVL - 1][0])
  643. return temp_map[CPCAP_MAX_TEMP_LVL - 1][1];
  644. if (value >= temp_map[0][0])
  645. return temp_map[0][1];
  646. for (i = 0; i < CPCAP_MAX_TEMP_LVL - 1; i++) {
  647. if ((value <= temp_map[i][0]) &&
  648. (value >= temp_map[i + 1][0])) {
  649. if (value == temp_map[i][0]) {
  650. result = temp_map[i][1];
  651. } else if (value == temp_map[i + 1][0]) {
  652. result = temp_map[i + 1][1];
  653. } else {
  654. alpha = ((value - temp_map[i][0]) * 1000) /
  655. (temp_map[i + 1][0] - temp_map[i][0]);
  656. result = temp_map[i][1] +
  657. ((alpha * (temp_map[i + 1][1] -
  658. temp_map[i][1])) / 1000);
  659. }
  660. break;
  661. }
  662. }
  663. return result;
  664. }
  665. static void cpcap_adc_convert(struct cpcap_adc_request *req)
  666. {
  667. const struct cpcap_adc_conversion_tbl *conv_tbl = req->conv_tbl;
  668. int index = req->channel;
  669. /* Remuxed channels 16 and 17 use BATTP and BATTI entries */
  670. switch (req->channel) {
  671. case CPCAP_ADC_BATTP_PI16:
  672. index = CPCAP_ADC_BATTP;
  673. break;
  674. case CPCAP_ADC_BATTI_PI17:
  675. index = CPCAP_ADC_BATTI;
  676. break;
  677. default:
  678. break;
  679. }
  680. /* No conversion for raw channels */
  681. if (conv_tbl[index].conv_type == IIO_CHAN_INFO_RAW)
  682. return;
  683. /* Temperatures use a lookup table instead of conversion table */
  684. if ((req->channel == CPCAP_ADC_AD0) ||
  685. (req->channel == CPCAP_ADC_AD3)) {
  686. req->result =
  687. cpcap_adc_table_to_millicelcius(req->result);
  688. return;
  689. }
  690. /* All processed channels use a conversion table */
  691. req->result *= conv_tbl[index].multiplier;
  692. if (conv_tbl[index].divider == 0)
  693. return;
  694. req->result /= conv_tbl[index].divider;
  695. req->result += conv_tbl[index].conv_offset;
  696. }
  697. /*
  698. * REVISIT: Check if timed sampling can use multiple channels at the
  699. * same time. If not, replace channel_mask with just channel.
  700. */
  701. static int cpcap_adc_read_bank_scaled(struct cpcap_adc *ddata,
  702. struct cpcap_adc_request *req)
  703. {
  704. int calibration_data, error, addr;
  705. if (ddata->vendor == CPCAP_VENDOR_TI) {
  706. error = regmap_read(ddata->reg, CPCAP_REG_ADCAL1,
  707. &calibration_data);
  708. if (error)
  709. return error;
  710. bank_conversion[CPCAP_ADC_CHG_ISENSE].cal_offset =
  711. ((short)calibration_data * -1) + 512;
  712. error = regmap_read(ddata->reg, CPCAP_REG_ADCAL2,
  713. &calibration_data);
  714. if (error)
  715. return error;
  716. bank_conversion[CPCAP_ADC_BATTI].cal_offset =
  717. ((short)calibration_data * -1) + 512;
  718. }
  719. addr = CPCAP_REG_ADCD0 + req->bank_index * 4;
  720. error = regmap_read(ddata->reg, addr, &req->result);
  721. if (error)
  722. return error;
  723. req->result &= 0x3ff;
  724. cpcap_adc_phase(req);
  725. cpcap_adc_convert(req);
  726. return 0;
  727. }
  728. static int cpcap_adc_init_request(struct cpcap_adc_request *req,
  729. int channel)
  730. {
  731. req->channel = channel;
  732. req->phase_tbl = bank_phasing;
  733. req->conv_tbl = bank_conversion;
  734. switch (channel) {
  735. case CPCAP_ADC_AD0 ... CPCAP_ADC_USB_ID:
  736. req->bank_index = channel;
  737. break;
  738. case CPCAP_ADC_AD8 ... CPCAP_ADC_TSY2_AD15:
  739. req->bank_index = channel - 8;
  740. break;
  741. case CPCAP_ADC_BATTP_PI16:
  742. req->bank_index = CPCAP_ADC_BATTP;
  743. break;
  744. case CPCAP_ADC_BATTI_PI17:
  745. req->bank_index = CPCAP_ADC_BATTI;
  746. break;
  747. default:
  748. return -EINVAL;
  749. }
  750. return 0;
  751. }
  752. static int cpcap_adc_read_st_die_temp(struct cpcap_adc *ddata,
  753. int addr, int *val)
  754. {
  755. int error;
  756. error = regmap_read(ddata->reg, addr, val);
  757. if (error)
  758. return error;
  759. *val -= 282;
  760. *val *= 114;
  761. *val += 25000;
  762. return 0;
  763. }
  764. static int cpcap_adc_read(struct iio_dev *indio_dev,
  765. struct iio_chan_spec const *chan,
  766. int *val, int *val2, long mask)
  767. {
  768. struct cpcap_adc *ddata = iio_priv(indio_dev);
  769. struct cpcap_adc_request req;
  770. int error;
  771. error = cpcap_adc_init_request(&req, chan->channel);
  772. if (error)
  773. return error;
  774. switch (mask) {
  775. case IIO_CHAN_INFO_RAW:
  776. mutex_lock(&ddata->lock);
  777. error = cpcap_adc_start_bank(ddata, &req);
  778. if (error)
  779. goto err_unlock;
  780. error = regmap_read(ddata->reg, chan->address, val);
  781. if (error)
  782. goto err_unlock;
  783. error = cpcap_adc_stop_bank(ddata);
  784. if (error)
  785. goto err_unlock;
  786. mutex_unlock(&ddata->lock);
  787. break;
  788. case IIO_CHAN_INFO_PROCESSED:
  789. mutex_lock(&ddata->lock);
  790. error = cpcap_adc_start_bank(ddata, &req);
  791. if (error)
  792. goto err_unlock;
  793. if ((ddata->vendor == CPCAP_VENDOR_ST) &&
  794. (chan->channel == CPCAP_ADC_AD3)) {
  795. error = cpcap_adc_read_st_die_temp(ddata,
  796. chan->address,
  797. &req.result);
  798. if (error)
  799. goto err_unlock;
  800. } else {
  801. error = cpcap_adc_read_bank_scaled(ddata, &req);
  802. if (error)
  803. goto err_unlock;
  804. }
  805. error = cpcap_adc_stop_bank(ddata);
  806. if (error)
  807. goto err_unlock;
  808. mutex_unlock(&ddata->lock);
  809. *val = req.result;
  810. break;
  811. default:
  812. return -EINVAL;
  813. }
  814. return IIO_VAL_INT;
  815. err_unlock:
  816. mutex_unlock(&ddata->lock);
  817. dev_err(ddata->dev, "error reading ADC: %i\n", error);
  818. return error;
  819. }
  820. static const struct iio_info cpcap_adc_info = {
  821. .read_raw = &cpcap_adc_read,
  822. };
  823. /*
  824. * Configuration for Motorola mapphone series such as droid 4.
  825. * Copied from the Motorola mapphone kernel tree.
  826. */
  827. static const struct cpcap_adc_ato mapphone_adc = {
  828. .ato_in = 0x0480,
  829. .atox_in = 0,
  830. .adc_ps_factor_in = 0x0200,
  831. .atox_ps_factor_in = 0,
  832. .ato_out = 0,
  833. .atox_out = 0,
  834. .adc_ps_factor_out = 0,
  835. .atox_ps_factor_out = 0,
  836. };
  837. static const struct of_device_id cpcap_adc_id_table[] = {
  838. {
  839. .compatible = "motorola,cpcap-adc",
  840. },
  841. {
  842. .compatible = "motorola,mapphone-cpcap-adc",
  843. .data = &mapphone_adc,
  844. },
  845. { /* sentinel */ },
  846. };
  847. MODULE_DEVICE_TABLE(of, cpcap_adc_id_table);
  848. static int cpcap_adc_probe(struct platform_device *pdev)
  849. {
  850. struct cpcap_adc *ddata;
  851. struct iio_dev *indio_dev;
  852. int error;
  853. indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*ddata));
  854. if (!indio_dev) {
  855. dev_err(&pdev->dev, "failed to allocate iio device\n");
  856. return -ENOMEM;
  857. }
  858. ddata = iio_priv(indio_dev);
  859. ddata->ato = device_get_match_data(&pdev->dev);
  860. if (!ddata->ato)
  861. return -ENODEV;
  862. ddata->dev = &pdev->dev;
  863. mutex_init(&ddata->lock);
  864. init_waitqueue_head(&ddata->wq_data_avail);
  865. indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
  866. indio_dev->channels = cpcap_adc_channels;
  867. indio_dev->num_channels = ARRAY_SIZE(cpcap_adc_channels);
  868. indio_dev->name = dev_name(&pdev->dev);
  869. indio_dev->info = &cpcap_adc_info;
  870. ddata->reg = dev_get_regmap(pdev->dev.parent, NULL);
  871. if (!ddata->reg)
  872. return -ENODEV;
  873. error = cpcap_get_vendor(ddata->dev, ddata->reg, &ddata->vendor);
  874. if (error)
  875. return error;
  876. platform_set_drvdata(pdev, indio_dev);
  877. ddata->irq = platform_get_irq_byname(pdev, "adcdone");
  878. if (ddata->irq < 0)
  879. return -ENODEV;
  880. error = devm_request_threaded_irq(&pdev->dev, ddata->irq, NULL,
  881. cpcap_adc_irq_thread,
  882. IRQF_TRIGGER_NONE | IRQF_ONESHOT,
  883. "cpcap-adc", indio_dev);
  884. if (error) {
  885. dev_err(&pdev->dev, "could not get irq: %i\n",
  886. error);
  887. return error;
  888. }
  889. error = cpcap_adc_calibrate(ddata);
  890. if (error)
  891. return error;
  892. dev_info(&pdev->dev, "CPCAP ADC device probed\n");
  893. return devm_iio_device_register(&pdev->dev, indio_dev);
  894. }
  895. static struct platform_driver cpcap_adc_driver = {
  896. .driver = {
  897. .name = "cpcap_adc",
  898. .of_match_table = cpcap_adc_id_table,
  899. },
  900. .probe = cpcap_adc_probe,
  901. };
  902. module_platform_driver(cpcap_adc_driver);
  903. MODULE_ALIAS("platform:cpcap_adc");
  904. MODULE_DESCRIPTION("CPCAP ADC driver");
  905. MODULE_AUTHOR("Tony Lindgren <tony@atomide.com");
  906. MODULE_LICENSE("GPL v2");