cc10001_adc.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014-2015 Imagination Technologies Ltd.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/err.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_device.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/regulator/consumer.h>
  14. #include <linux/slab.h>
  15. #include <linux/iio/buffer.h>
  16. #include <linux/iio/iio.h>
  17. #include <linux/iio/sysfs.h>
  18. #include <linux/iio/trigger.h>
  19. #include <linux/iio/trigger_consumer.h>
  20. #include <linux/iio/triggered_buffer.h>
  21. /* Registers */
  22. #define CC10001_ADC_CONFIG 0x00
  23. #define CC10001_ADC_START_CONV BIT(4)
  24. #define CC10001_ADC_MODE_SINGLE_CONV BIT(5)
  25. #define CC10001_ADC_DDATA_OUT 0x04
  26. #define CC10001_ADC_EOC 0x08
  27. #define CC10001_ADC_EOC_SET BIT(0)
  28. #define CC10001_ADC_CHSEL_SAMPLED 0x0c
  29. #define CC10001_ADC_POWER_DOWN 0x10
  30. #define CC10001_ADC_POWER_DOWN_SET BIT(0)
  31. #define CC10001_ADC_DEBUG 0x14
  32. #define CC10001_ADC_DATA_COUNT 0x20
  33. #define CC10001_ADC_DATA_MASK GENMASK(9, 0)
  34. #define CC10001_ADC_NUM_CHANNELS 8
  35. #define CC10001_ADC_CH_MASK GENMASK(2, 0)
  36. #define CC10001_INVALID_SAMPLED 0xffff
  37. #define CC10001_MAX_POLL_COUNT 20
  38. /*
  39. * As per device specification, wait six clock cycles after power-up to
  40. * activate START. Since adding two more clock cycles delay does not
  41. * impact the performance too much, we are adding two additional cycles delay
  42. * intentionally here.
  43. */
  44. #define CC10001_WAIT_CYCLES 8
  45. struct cc10001_adc_device {
  46. void __iomem *reg_base;
  47. struct clk *adc_clk;
  48. struct regulator *reg;
  49. u16 *buf;
  50. bool shared;
  51. struct mutex lock;
  52. unsigned int start_delay_ns;
  53. unsigned int eoc_delay_ns;
  54. };
  55. static inline void cc10001_adc_write_reg(struct cc10001_adc_device *adc_dev,
  56. u32 reg, u32 val)
  57. {
  58. writel(val, adc_dev->reg_base + reg);
  59. }
  60. static inline u32 cc10001_adc_read_reg(struct cc10001_adc_device *adc_dev,
  61. u32 reg)
  62. {
  63. return readl(adc_dev->reg_base + reg);
  64. }
  65. static void cc10001_adc_power_up(struct cc10001_adc_device *adc_dev)
  66. {
  67. cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN, 0);
  68. ndelay(adc_dev->start_delay_ns);
  69. }
  70. static void cc10001_adc_power_down(struct cc10001_adc_device *adc_dev)
  71. {
  72. cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN,
  73. CC10001_ADC_POWER_DOWN_SET);
  74. }
  75. static void cc10001_adc_start(struct cc10001_adc_device *adc_dev,
  76. unsigned int channel)
  77. {
  78. u32 val;
  79. /* Channel selection and mode of operation */
  80. val = (channel & CC10001_ADC_CH_MASK) | CC10001_ADC_MODE_SINGLE_CONV;
  81. cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
  82. udelay(1);
  83. val = cc10001_adc_read_reg(adc_dev, CC10001_ADC_CONFIG);
  84. val = val | CC10001_ADC_START_CONV;
  85. cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
  86. }
  87. static u16 cc10001_adc_poll_done(struct iio_dev *indio_dev,
  88. unsigned int channel,
  89. unsigned int delay)
  90. {
  91. struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
  92. unsigned int poll_count = 0;
  93. while (!(cc10001_adc_read_reg(adc_dev, CC10001_ADC_EOC) &
  94. CC10001_ADC_EOC_SET)) {
  95. ndelay(delay);
  96. if (poll_count++ == CC10001_MAX_POLL_COUNT)
  97. return CC10001_INVALID_SAMPLED;
  98. }
  99. poll_count = 0;
  100. while ((cc10001_adc_read_reg(adc_dev, CC10001_ADC_CHSEL_SAMPLED) &
  101. CC10001_ADC_CH_MASK) != channel) {
  102. ndelay(delay);
  103. if (poll_count++ == CC10001_MAX_POLL_COUNT)
  104. return CC10001_INVALID_SAMPLED;
  105. }
  106. /* Read the 10 bit output register */
  107. return cc10001_adc_read_reg(adc_dev, CC10001_ADC_DDATA_OUT) &
  108. CC10001_ADC_DATA_MASK;
  109. }
  110. static irqreturn_t cc10001_adc_trigger_h(int irq, void *p)
  111. {
  112. struct cc10001_adc_device *adc_dev;
  113. struct iio_poll_func *pf = p;
  114. struct iio_dev *indio_dev;
  115. unsigned int delay_ns;
  116. unsigned int channel;
  117. unsigned int scan_idx;
  118. bool sample_invalid;
  119. u16 *data;
  120. int i;
  121. indio_dev = pf->indio_dev;
  122. adc_dev = iio_priv(indio_dev);
  123. data = adc_dev->buf;
  124. mutex_lock(&adc_dev->lock);
  125. if (!adc_dev->shared)
  126. cc10001_adc_power_up(adc_dev);
  127. /* Calculate delay step for eoc and sampled data */
  128. delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
  129. i = 0;
  130. sample_invalid = false;
  131. for_each_set_bit(scan_idx, indio_dev->active_scan_mask,
  132. indio_dev->masklength) {
  133. channel = indio_dev->channels[scan_idx].channel;
  134. cc10001_adc_start(adc_dev, channel);
  135. data[i] = cc10001_adc_poll_done(indio_dev, channel, delay_ns);
  136. if (data[i] == CC10001_INVALID_SAMPLED) {
  137. dev_warn(&indio_dev->dev,
  138. "invalid sample on channel %d\n", channel);
  139. sample_invalid = true;
  140. goto done;
  141. }
  142. i++;
  143. }
  144. done:
  145. if (!adc_dev->shared)
  146. cc10001_adc_power_down(adc_dev);
  147. mutex_unlock(&adc_dev->lock);
  148. if (!sample_invalid)
  149. iio_push_to_buffers_with_timestamp(indio_dev, data,
  150. iio_get_time_ns(indio_dev));
  151. iio_trigger_notify_done(indio_dev->trig);
  152. return IRQ_HANDLED;
  153. }
  154. static u16 cc10001_adc_read_raw_voltage(struct iio_dev *indio_dev,
  155. struct iio_chan_spec const *chan)
  156. {
  157. struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
  158. unsigned int delay_ns;
  159. u16 val;
  160. if (!adc_dev->shared)
  161. cc10001_adc_power_up(adc_dev);
  162. /* Calculate delay step for eoc and sampled data */
  163. delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
  164. cc10001_adc_start(adc_dev, chan->channel);
  165. val = cc10001_adc_poll_done(indio_dev, chan->channel, delay_ns);
  166. if (!adc_dev->shared)
  167. cc10001_adc_power_down(adc_dev);
  168. return val;
  169. }
  170. static int cc10001_adc_read_raw(struct iio_dev *indio_dev,
  171. struct iio_chan_spec const *chan,
  172. int *val, int *val2, long mask)
  173. {
  174. struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
  175. int ret;
  176. switch (mask) {
  177. case IIO_CHAN_INFO_RAW:
  178. if (iio_buffer_enabled(indio_dev))
  179. return -EBUSY;
  180. mutex_lock(&adc_dev->lock);
  181. *val = cc10001_adc_read_raw_voltage(indio_dev, chan);
  182. mutex_unlock(&adc_dev->lock);
  183. if (*val == CC10001_INVALID_SAMPLED)
  184. return -EIO;
  185. return IIO_VAL_INT;
  186. case IIO_CHAN_INFO_SCALE:
  187. ret = regulator_get_voltage(adc_dev->reg);
  188. if (ret < 0)
  189. return ret;
  190. *val = ret / 1000;
  191. *val2 = chan->scan_type.realbits;
  192. return IIO_VAL_FRACTIONAL_LOG2;
  193. default:
  194. return -EINVAL;
  195. }
  196. }
  197. static int cc10001_update_scan_mode(struct iio_dev *indio_dev,
  198. const unsigned long *scan_mask)
  199. {
  200. struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
  201. kfree(adc_dev->buf);
  202. adc_dev->buf = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
  203. if (!adc_dev->buf)
  204. return -ENOMEM;
  205. return 0;
  206. }
  207. static const struct iio_info cc10001_adc_info = {
  208. .read_raw = &cc10001_adc_read_raw,
  209. .update_scan_mode = &cc10001_update_scan_mode,
  210. };
  211. static int cc10001_adc_channel_init(struct iio_dev *indio_dev,
  212. unsigned long channel_map)
  213. {
  214. struct iio_chan_spec *chan_array, *timestamp;
  215. unsigned int bit, idx = 0;
  216. indio_dev->num_channels = bitmap_weight(&channel_map,
  217. CC10001_ADC_NUM_CHANNELS) + 1;
  218. chan_array = devm_kcalloc(&indio_dev->dev, indio_dev->num_channels,
  219. sizeof(struct iio_chan_spec),
  220. GFP_KERNEL);
  221. if (!chan_array)
  222. return -ENOMEM;
  223. for_each_set_bit(bit, &channel_map, CC10001_ADC_NUM_CHANNELS) {
  224. struct iio_chan_spec *chan = &chan_array[idx];
  225. chan->type = IIO_VOLTAGE;
  226. chan->indexed = 1;
  227. chan->channel = bit;
  228. chan->scan_index = idx;
  229. chan->scan_type.sign = 'u';
  230. chan->scan_type.realbits = 10;
  231. chan->scan_type.storagebits = 16;
  232. chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
  233. chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
  234. idx++;
  235. }
  236. timestamp = &chan_array[idx];
  237. timestamp->type = IIO_TIMESTAMP;
  238. timestamp->channel = -1;
  239. timestamp->scan_index = idx;
  240. timestamp->scan_type.sign = 's';
  241. timestamp->scan_type.realbits = 64;
  242. timestamp->scan_type.storagebits = 64;
  243. indio_dev->channels = chan_array;
  244. return 0;
  245. }
  246. static int cc10001_adc_probe(struct platform_device *pdev)
  247. {
  248. struct device_node *node = pdev->dev.of_node;
  249. struct cc10001_adc_device *adc_dev;
  250. unsigned long adc_clk_rate;
  251. struct iio_dev *indio_dev;
  252. unsigned long channel_map;
  253. int ret;
  254. indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
  255. if (indio_dev == NULL)
  256. return -ENOMEM;
  257. adc_dev = iio_priv(indio_dev);
  258. channel_map = GENMASK(CC10001_ADC_NUM_CHANNELS - 1, 0);
  259. if (!of_property_read_u32(node, "adc-reserved-channels", &ret)) {
  260. adc_dev->shared = true;
  261. channel_map &= ~ret;
  262. }
  263. adc_dev->reg = devm_regulator_get(&pdev->dev, "vref");
  264. if (IS_ERR(adc_dev->reg))
  265. return PTR_ERR(adc_dev->reg);
  266. ret = regulator_enable(adc_dev->reg);
  267. if (ret)
  268. return ret;
  269. indio_dev->name = dev_name(&pdev->dev);
  270. indio_dev->info = &cc10001_adc_info;
  271. indio_dev->modes = INDIO_DIRECT_MODE;
  272. adc_dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
  273. if (IS_ERR(adc_dev->reg_base)) {
  274. ret = PTR_ERR(adc_dev->reg_base);
  275. goto err_disable_reg;
  276. }
  277. adc_dev->adc_clk = devm_clk_get(&pdev->dev, "adc");
  278. if (IS_ERR(adc_dev->adc_clk)) {
  279. dev_err(&pdev->dev, "failed to get the clock\n");
  280. ret = PTR_ERR(adc_dev->adc_clk);
  281. goto err_disable_reg;
  282. }
  283. ret = clk_prepare_enable(adc_dev->adc_clk);
  284. if (ret) {
  285. dev_err(&pdev->dev, "failed to enable the clock\n");
  286. goto err_disable_reg;
  287. }
  288. adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
  289. if (!adc_clk_rate) {
  290. ret = -EINVAL;
  291. dev_err(&pdev->dev, "null clock rate!\n");
  292. goto err_disable_clk;
  293. }
  294. adc_dev->eoc_delay_ns = NSEC_PER_SEC / adc_clk_rate;
  295. adc_dev->start_delay_ns = adc_dev->eoc_delay_ns * CC10001_WAIT_CYCLES;
  296. /*
  297. * There is only one register to power-up/power-down the AUX ADC.
  298. * If the ADC is shared among multiple CPUs, always power it up here.
  299. * If the ADC is used only by the MIPS, power-up/power-down at runtime.
  300. */
  301. if (adc_dev->shared)
  302. cc10001_adc_power_up(adc_dev);
  303. /* Setup the ADC channels available on the device */
  304. ret = cc10001_adc_channel_init(indio_dev, channel_map);
  305. if (ret < 0)
  306. goto err_disable_clk;
  307. mutex_init(&adc_dev->lock);
  308. ret = iio_triggered_buffer_setup(indio_dev, NULL,
  309. &cc10001_adc_trigger_h, NULL);
  310. if (ret < 0)
  311. goto err_disable_clk;
  312. ret = iio_device_register(indio_dev);
  313. if (ret < 0)
  314. goto err_cleanup_buffer;
  315. platform_set_drvdata(pdev, indio_dev);
  316. return 0;
  317. err_cleanup_buffer:
  318. iio_triggered_buffer_cleanup(indio_dev);
  319. err_disable_clk:
  320. clk_disable_unprepare(adc_dev->adc_clk);
  321. err_disable_reg:
  322. regulator_disable(adc_dev->reg);
  323. return ret;
  324. }
  325. static int cc10001_adc_remove(struct platform_device *pdev)
  326. {
  327. struct iio_dev *indio_dev = platform_get_drvdata(pdev);
  328. struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
  329. cc10001_adc_power_down(adc_dev);
  330. iio_device_unregister(indio_dev);
  331. iio_triggered_buffer_cleanup(indio_dev);
  332. clk_disable_unprepare(adc_dev->adc_clk);
  333. regulator_disable(adc_dev->reg);
  334. return 0;
  335. }
  336. static const struct of_device_id cc10001_adc_dt_ids[] = {
  337. { .compatible = "cosmic,10001-adc", },
  338. { }
  339. };
  340. MODULE_DEVICE_TABLE(of, cc10001_adc_dt_ids);
  341. static struct platform_driver cc10001_adc_driver = {
  342. .driver = {
  343. .name = "cc10001-adc",
  344. .of_match_table = cc10001_adc_dt_ids,
  345. },
  346. .probe = cc10001_adc_probe,
  347. .remove = cc10001_adc_remove,
  348. };
  349. module_platform_driver(cc10001_adc_driver);
  350. MODULE_AUTHOR("Phani Movva <Phani.Movva@imgtec.com>");
  351. MODULE_DESCRIPTION("Cosmic Circuits ADC driver");
  352. MODULE_LICENSE("GPL v2");