at91_adc.c 40 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for the ADC present in the Atmel AT91 evaluation boards.
  4. *
  5. * Copyright 2011 Free Electrons
  6. */
  7. #include <linux/bitmap.h>
  8. #include <linux/bitops.h>
  9. #include <linux/clk.h>
  10. #include <linux/err.h>
  11. #include <linux/io.h>
  12. #include <linux/input.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/jiffies.h>
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/of_device.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/sched.h>
  21. #include <linux/slab.h>
  22. #include <linux/wait.h>
  23. #include <linux/platform_data/at91_adc.h>
  24. #include <linux/iio/iio.h>
  25. #include <linux/iio/buffer.h>
  26. #include <linux/iio/trigger.h>
  27. #include <linux/iio/trigger_consumer.h>
  28. #include <linux/iio/triggered_buffer.h>
  29. #include <linux/pinctrl/consumer.h>
  30. /* Registers */
  31. #define AT91_ADC_CR 0x00 /* Control Register */
  32. #define AT91_ADC_SWRST (1 << 0) /* Software Reset */
  33. #define AT91_ADC_START (1 << 1) /* Start Conversion */
  34. #define AT91_ADC_MR 0x04 /* Mode Register */
  35. #define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */
  36. #define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */
  37. #define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */
  38. #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
  39. #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
  40. #define AT91_ADC_TRGSEL_TC0 (0 << 1)
  41. #define AT91_ADC_TRGSEL_TC1 (1 << 1)
  42. #define AT91_ADC_TRGSEL_TC2 (2 << 1)
  43. #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
  44. #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
  45. #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */
  46. #define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */
  47. #define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */
  48. #define AT91_ADC_PRESCAL_9G45 (0xff << 8)
  49. #define AT91_ADC_PRESCAL_(x) ((x) << 8)
  50. #define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */
  51. #define AT91_ADC_STARTUP_9G45 (0x7f << 16)
  52. #define AT91_ADC_STARTUP_9X5 (0xf << 16)
  53. #define AT91_ADC_STARTUP_(x) ((x) << 16)
  54. #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */
  55. #define AT91_ADC_SHTIM_(x) ((x) << 24)
  56. #define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */
  57. #define AT91_ADC_PENDBC_(x) ((x) << 28)
  58. #define AT91_ADC_TSR 0x0C
  59. #define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */
  60. #define AT91_ADC_TSR_SHTIM_(x) ((x) << 24)
  61. #define AT91_ADC_CHER 0x10 /* Channel Enable Register */
  62. #define AT91_ADC_CHDR 0x14 /* Channel Disable Register */
  63. #define AT91_ADC_CHSR 0x18 /* Channel Status Register */
  64. #define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */
  65. #define AT91_ADC_SR 0x1C /* Status Register */
  66. #define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */
  67. #define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */
  68. #define AT91_ADC_DRDY (1 << 16) /* Data Ready */
  69. #define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */
  70. #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */
  71. #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */
  72. #define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */
  73. #define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */
  74. #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */
  75. #define AT91_ADC_LDATA (0x3ff)
  76. #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */
  77. #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
  78. #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
  79. #define AT91RL_ADC_IER_PEN (1 << 20)
  80. #define AT91RL_ADC_IER_NOPEN (1 << 21)
  81. #define AT91_ADC_IER_PEN (1 << 29)
  82. #define AT91_ADC_IER_NOPEN (1 << 30)
  83. #define AT91_ADC_IER_XRDY (1 << 20)
  84. #define AT91_ADC_IER_YRDY (1 << 21)
  85. #define AT91_ADC_IER_PRDY (1 << 22)
  86. #define AT91_ADC_ISR_PENS (1 << 31)
  87. #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */
  88. #define AT91_ADC_DATA (0x3ff)
  89. #define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */
  90. #define AT91_ADC_ACR 0x94 /* Analog Control Register */
  91. #define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */
  92. #define AT91_ADC_TSMR 0xB0
  93. #define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */
  94. #define AT91_ADC_TSMR_TSMODE_NONE (0 << 0)
  95. #define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0)
  96. #define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0)
  97. #define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0)
  98. #define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */
  99. #define AT91_ADC_TSMR_TSAV_(x) ((x) << 4)
  100. #define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */
  101. #define AT91_ADC_TSMR_SCTIM_(x) ((x) << 16)
  102. #define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */
  103. #define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28)
  104. #define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */
  105. #define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */
  106. #define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */
  107. #define AT91_ADC_TSXPOSR 0xB4
  108. #define AT91_ADC_TSYPOSR 0xB8
  109. #define AT91_ADC_TSPRESSR 0xBC
  110. #define AT91_ADC_TRGR_9260 AT91_ADC_MR
  111. #define AT91_ADC_TRGR_9G45 0x08
  112. #define AT91_ADC_TRGR_9X5 0xC0
  113. /* Trigger Register bit field */
  114. #define AT91_ADC_TRGR_TRGPER (0xffff << 16)
  115. #define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16)
  116. #define AT91_ADC_TRGR_TRGMOD (0x7 << 0)
  117. #define AT91_ADC_TRGR_NONE (0 << 0)
  118. #define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0)
  119. #define AT91_ADC_CHAN(st, ch) \
  120. (st->registers->channel_base + (ch * 4))
  121. #define at91_adc_readl(st, reg) \
  122. (readl_relaxed(st->reg_base + reg))
  123. #define at91_adc_writel(st, reg, val) \
  124. (writel_relaxed(val, st->reg_base + reg))
  125. #define DRIVER_NAME "at91_adc"
  126. #define MAX_POS_BITS 12
  127. #define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
  128. #define TOUCH_PEN_DETECT_DEBOUNCE_US 200
  129. #define MAX_RLPOS_BITS 10
  130. #define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */
  131. #define TOUCH_SHTIM 0xa
  132. #define TOUCH_SCTIM_US 10 /* 10us for the Touchscreen Switches Closure Time */
  133. /**
  134. * struct at91_adc_reg_desc - Various informations relative to registers
  135. * @channel_base: Base offset for the channel data registers
  136. * @drdy_mask: Mask of the DRDY field in the relevant registers
  137. * (Interruptions registers mostly)
  138. * @status_register: Offset of the Interrupt Status Register
  139. * @trigger_register: Offset of the Trigger setup register
  140. * @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register
  141. * @mr_startup_mask: Mask of the STARTUP field in the adc MR register
  142. */
  143. struct at91_adc_reg_desc {
  144. u8 channel_base;
  145. u32 drdy_mask;
  146. u8 status_register;
  147. u8 trigger_register;
  148. u32 mr_prescal_mask;
  149. u32 mr_startup_mask;
  150. };
  151. struct at91_adc_caps {
  152. bool has_ts; /* Support touch screen */
  153. bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */
  154. /*
  155. * Numbers of sampling data will be averaged. Can be 0~3.
  156. * Hardware can average (2 ^ ts_filter_average) sample data.
  157. */
  158. u8 ts_filter_average;
  159. /* Pen Detection input pull-up resistor, can be 0~3 */
  160. u8 ts_pen_detect_sensitivity;
  161. /* startup time calculate function */
  162. u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz);
  163. u8 num_channels;
  164. struct at91_adc_reg_desc registers;
  165. };
  166. struct at91_adc_state {
  167. struct clk *adc_clk;
  168. u16 *buffer;
  169. unsigned long channels_mask;
  170. struct clk *clk;
  171. bool done;
  172. int irq;
  173. u16 last_value;
  174. int chnb;
  175. struct mutex lock;
  176. u8 num_channels;
  177. void __iomem *reg_base;
  178. struct at91_adc_reg_desc *registers;
  179. u32 startup_time;
  180. u8 sample_hold_time;
  181. bool sleep_mode;
  182. struct iio_trigger **trig;
  183. struct at91_adc_trigger *trigger_list;
  184. u32 trigger_number;
  185. bool use_external;
  186. u32 vref_mv;
  187. u32 res; /* resolution used for convertions */
  188. bool low_res; /* the resolution corresponds to the lowest one */
  189. wait_queue_head_t wq_data_avail;
  190. struct at91_adc_caps *caps;
  191. /*
  192. * Following ADC channels are shared by touchscreen:
  193. *
  194. * CH0 -- Touch screen XP/UL
  195. * CH1 -- Touch screen XM/UR
  196. * CH2 -- Touch screen YP/LL
  197. * CH3 -- Touch screen YM/Sense
  198. * CH4 -- Touch screen LR(5-wire only)
  199. *
  200. * The bitfields below represents the reserved channel in the
  201. * touchscreen mode.
  202. */
  203. #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0)
  204. #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0)
  205. enum atmel_adc_ts_type touchscreen_type;
  206. struct input_dev *ts_input;
  207. u16 ts_sample_period_val;
  208. u32 ts_pressure_threshold;
  209. u16 ts_pendbc;
  210. bool ts_bufferedmeasure;
  211. u32 ts_prev_absx;
  212. u32 ts_prev_absy;
  213. };
  214. static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
  215. {
  216. struct iio_poll_func *pf = p;
  217. struct iio_dev *idev = pf->indio_dev;
  218. struct at91_adc_state *st = iio_priv(idev);
  219. struct iio_chan_spec const *chan;
  220. int i, j = 0;
  221. for (i = 0; i < idev->masklength; i++) {
  222. if (!test_bit(i, idev->active_scan_mask))
  223. continue;
  224. chan = idev->channels + i;
  225. st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, chan->channel));
  226. j++;
  227. }
  228. iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp);
  229. iio_trigger_notify_done(idev->trig);
  230. /* Needed to ACK the DRDY interruption */
  231. at91_adc_readl(st, AT91_ADC_LCDR);
  232. enable_irq(st->irq);
  233. return IRQ_HANDLED;
  234. }
  235. /* Handler for classic adc channel eoc trigger */
  236. static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev)
  237. {
  238. struct at91_adc_state *st = iio_priv(idev);
  239. if (iio_buffer_enabled(idev)) {
  240. disable_irq_nosync(irq);
  241. iio_trigger_poll(idev->trig);
  242. } else {
  243. st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb));
  244. /* Needed to ACK the DRDY interruption */
  245. at91_adc_readl(st, AT91_ADC_LCDR);
  246. st->done = true;
  247. wake_up_interruptible(&st->wq_data_avail);
  248. }
  249. }
  250. static int at91_ts_sample(struct iio_dev *idev)
  251. {
  252. struct at91_adc_state *st = iio_priv(idev);
  253. unsigned int xscale, yscale, reg, z1, z2;
  254. unsigned int x, y, pres, xpos, ypos;
  255. unsigned int rxp = 1;
  256. unsigned int factor = 1000;
  257. unsigned int xyz_mask_bits = st->res;
  258. unsigned int xyz_mask = (1 << xyz_mask_bits) - 1;
  259. /* calculate position */
  260. /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */
  261. reg = at91_adc_readl(st, AT91_ADC_TSXPOSR);
  262. xpos = reg & xyz_mask;
  263. x = (xpos << MAX_POS_BITS) - xpos;
  264. xscale = (reg >> 16) & xyz_mask;
  265. if (xscale == 0) {
  266. dev_err(&idev->dev, "Error: xscale == 0!\n");
  267. return -1;
  268. }
  269. x /= xscale;
  270. /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */
  271. reg = at91_adc_readl(st, AT91_ADC_TSYPOSR);
  272. ypos = reg & xyz_mask;
  273. y = (ypos << MAX_POS_BITS) - ypos;
  274. yscale = (reg >> 16) & xyz_mask;
  275. if (yscale == 0) {
  276. dev_err(&idev->dev, "Error: yscale == 0!\n");
  277. return -1;
  278. }
  279. y /= yscale;
  280. /* calculate the pressure */
  281. reg = at91_adc_readl(st, AT91_ADC_TSPRESSR);
  282. z1 = reg & xyz_mask;
  283. z2 = (reg >> 16) & xyz_mask;
  284. if (z1 != 0)
  285. pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor)
  286. / factor;
  287. else
  288. pres = st->ts_pressure_threshold; /* no pen contacted */
  289. dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n",
  290. xpos, xscale, ypos, yscale, z1, z2, pres);
  291. if (pres < st->ts_pressure_threshold) {
  292. dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n",
  293. x, y, pres / factor);
  294. input_report_abs(st->ts_input, ABS_X, x);
  295. input_report_abs(st->ts_input, ABS_Y, y);
  296. input_report_abs(st->ts_input, ABS_PRESSURE, pres);
  297. input_report_key(st->ts_input, BTN_TOUCH, 1);
  298. input_sync(st->ts_input);
  299. } else {
  300. dev_dbg(&idev->dev, "pressure too low: not reporting\n");
  301. }
  302. return 0;
  303. }
  304. static irqreturn_t at91_adc_rl_interrupt(int irq, void *private)
  305. {
  306. struct iio_dev *idev = private;
  307. struct at91_adc_state *st = iio_priv(idev);
  308. u32 status = at91_adc_readl(st, st->registers->status_register);
  309. unsigned int reg;
  310. status &= at91_adc_readl(st, AT91_ADC_IMR);
  311. if (status & GENMASK(st->num_channels - 1, 0))
  312. handle_adc_eoc_trigger(irq, idev);
  313. if (status & AT91RL_ADC_IER_PEN) {
  314. /* Disabling pen debounce is required to get a NOPEN irq */
  315. reg = at91_adc_readl(st, AT91_ADC_MR);
  316. reg &= ~AT91_ADC_PENDBC;
  317. at91_adc_writel(st, AT91_ADC_MR, reg);
  318. at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
  319. at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN
  320. | AT91_ADC_EOC(3));
  321. /* Set up period trigger for sampling */
  322. at91_adc_writel(st, st->registers->trigger_register,
  323. AT91_ADC_TRGR_MOD_PERIOD_TRIG |
  324. AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
  325. } else if (status & AT91RL_ADC_IER_NOPEN) {
  326. reg = at91_adc_readl(st, AT91_ADC_MR);
  327. reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
  328. at91_adc_writel(st, AT91_ADC_MR, reg);
  329. at91_adc_writel(st, st->registers->trigger_register,
  330. AT91_ADC_TRGR_NONE);
  331. at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN
  332. | AT91_ADC_EOC(3));
  333. at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
  334. st->ts_bufferedmeasure = false;
  335. input_report_key(st->ts_input, BTN_TOUCH, 0);
  336. input_sync(st->ts_input);
  337. } else if (status & AT91_ADC_EOC(3) && st->ts_input) {
  338. /* Conversion finished and we've a touchscreen */
  339. if (st->ts_bufferedmeasure) {
  340. /*
  341. * Last measurement is always discarded, since it can
  342. * be erroneous.
  343. * Always report previous measurement
  344. */
  345. input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx);
  346. input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy);
  347. input_report_key(st->ts_input, BTN_TOUCH, 1);
  348. input_sync(st->ts_input);
  349. } else
  350. st->ts_bufferedmeasure = true;
  351. /* Now make new measurement */
  352. st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3))
  353. << MAX_RLPOS_BITS;
  354. st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2));
  355. st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1))
  356. << MAX_RLPOS_BITS;
  357. st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0));
  358. }
  359. return IRQ_HANDLED;
  360. }
  361. static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private)
  362. {
  363. struct iio_dev *idev = private;
  364. struct at91_adc_state *st = iio_priv(idev);
  365. u32 status = at91_adc_readl(st, st->registers->status_register);
  366. const uint32_t ts_data_irq_mask =
  367. AT91_ADC_IER_XRDY |
  368. AT91_ADC_IER_YRDY |
  369. AT91_ADC_IER_PRDY;
  370. if (status & GENMASK(st->num_channels - 1, 0))
  371. handle_adc_eoc_trigger(irq, idev);
  372. if (status & AT91_ADC_IER_PEN) {
  373. at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
  374. at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN |
  375. ts_data_irq_mask);
  376. /* Set up period trigger for sampling */
  377. at91_adc_writel(st, st->registers->trigger_register,
  378. AT91_ADC_TRGR_MOD_PERIOD_TRIG |
  379. AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
  380. } else if (status & AT91_ADC_IER_NOPEN) {
  381. at91_adc_writel(st, st->registers->trigger_register, 0);
  382. at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN |
  383. ts_data_irq_mask);
  384. at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
  385. input_report_key(st->ts_input, BTN_TOUCH, 0);
  386. input_sync(st->ts_input);
  387. } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) {
  388. /* Now all touchscreen data is ready */
  389. if (status & AT91_ADC_ISR_PENS) {
  390. /* validate data by pen contact */
  391. at91_ts_sample(idev);
  392. } else {
  393. /* triggered by event that is no pen contact, just read
  394. * them to clean the interrupt and discard all.
  395. */
  396. at91_adc_readl(st, AT91_ADC_TSXPOSR);
  397. at91_adc_readl(st, AT91_ADC_TSYPOSR);
  398. at91_adc_readl(st, AT91_ADC_TSPRESSR);
  399. }
  400. }
  401. return IRQ_HANDLED;
  402. }
  403. static int at91_adc_channel_init(struct iio_dev *idev)
  404. {
  405. struct at91_adc_state *st = iio_priv(idev);
  406. struct iio_chan_spec *chan_array, *timestamp;
  407. int bit, idx = 0;
  408. unsigned long rsvd_mask = 0;
  409. /* If touchscreen is enable, then reserve the adc channels */
  410. if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
  411. rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE;
  412. else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE)
  413. rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE;
  414. /* set up the channel mask to reserve touchscreen channels */
  415. st->channels_mask &= ~rsvd_mask;
  416. idev->num_channels = bitmap_weight(&st->channels_mask,
  417. st->num_channels) + 1;
  418. chan_array = devm_kzalloc(&idev->dev,
  419. ((idev->num_channels + 1) *
  420. sizeof(struct iio_chan_spec)),
  421. GFP_KERNEL);
  422. if (!chan_array)
  423. return -ENOMEM;
  424. for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
  425. struct iio_chan_spec *chan = chan_array + idx;
  426. chan->type = IIO_VOLTAGE;
  427. chan->indexed = 1;
  428. chan->channel = bit;
  429. chan->scan_index = idx;
  430. chan->scan_type.sign = 'u';
  431. chan->scan_type.realbits = st->res;
  432. chan->scan_type.storagebits = 16;
  433. chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
  434. chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
  435. idx++;
  436. }
  437. timestamp = chan_array + idx;
  438. timestamp->type = IIO_TIMESTAMP;
  439. timestamp->channel = -1;
  440. timestamp->scan_index = idx;
  441. timestamp->scan_type.sign = 's';
  442. timestamp->scan_type.realbits = 64;
  443. timestamp->scan_type.storagebits = 64;
  444. idev->channels = chan_array;
  445. return idev->num_channels;
  446. }
  447. static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
  448. struct at91_adc_trigger *triggers,
  449. const char *trigger_name)
  450. {
  451. struct at91_adc_state *st = iio_priv(idev);
  452. int i;
  453. for (i = 0; i < st->trigger_number; i++) {
  454. char *name = kasprintf(GFP_KERNEL,
  455. "%s-dev%d-%s",
  456. idev->name,
  457. idev->id,
  458. triggers[i].name);
  459. if (!name)
  460. return -ENOMEM;
  461. if (strcmp(trigger_name, name) == 0) {
  462. kfree(name);
  463. if (triggers[i].value == 0)
  464. return -EINVAL;
  465. return triggers[i].value;
  466. }
  467. kfree(name);
  468. }
  469. return -EINVAL;
  470. }
  471. static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
  472. {
  473. struct iio_dev *idev = iio_trigger_get_drvdata(trig);
  474. struct at91_adc_state *st = iio_priv(idev);
  475. struct at91_adc_reg_desc *reg = st->registers;
  476. u32 status = at91_adc_readl(st, reg->trigger_register);
  477. int value;
  478. u8 bit;
  479. value = at91_adc_get_trigger_value_by_name(idev,
  480. st->trigger_list,
  481. idev->trig->name);
  482. if (value < 0)
  483. return value;
  484. if (state) {
  485. st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
  486. if (st->buffer == NULL)
  487. return -ENOMEM;
  488. at91_adc_writel(st, reg->trigger_register,
  489. status | value);
  490. for_each_set_bit(bit, idev->active_scan_mask,
  491. st->num_channels) {
  492. struct iio_chan_spec const *chan = idev->channels + bit;
  493. at91_adc_writel(st, AT91_ADC_CHER,
  494. AT91_ADC_CH(chan->channel));
  495. }
  496. at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
  497. } else {
  498. at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
  499. at91_adc_writel(st, reg->trigger_register,
  500. status & ~value);
  501. for_each_set_bit(bit, idev->active_scan_mask,
  502. st->num_channels) {
  503. struct iio_chan_spec const *chan = idev->channels + bit;
  504. at91_adc_writel(st, AT91_ADC_CHDR,
  505. AT91_ADC_CH(chan->channel));
  506. }
  507. kfree(st->buffer);
  508. }
  509. return 0;
  510. }
  511. static const struct iio_trigger_ops at91_adc_trigger_ops = {
  512. .set_trigger_state = &at91_adc_configure_trigger,
  513. };
  514. static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
  515. struct at91_adc_trigger *trigger)
  516. {
  517. struct iio_trigger *trig;
  518. int ret;
  519. trig = iio_trigger_alloc("%s-dev%d-%s", idev->name,
  520. idev->id, trigger->name);
  521. if (trig == NULL)
  522. return NULL;
  523. trig->dev.parent = idev->dev.parent;
  524. iio_trigger_set_drvdata(trig, idev);
  525. trig->ops = &at91_adc_trigger_ops;
  526. ret = iio_trigger_register(trig);
  527. if (ret)
  528. return NULL;
  529. return trig;
  530. }
  531. static int at91_adc_trigger_init(struct iio_dev *idev)
  532. {
  533. struct at91_adc_state *st = iio_priv(idev);
  534. int i, ret;
  535. st->trig = devm_kcalloc(&idev->dev,
  536. st->trigger_number, sizeof(*st->trig),
  537. GFP_KERNEL);
  538. if (st->trig == NULL) {
  539. ret = -ENOMEM;
  540. goto error_ret;
  541. }
  542. for (i = 0; i < st->trigger_number; i++) {
  543. if (st->trigger_list[i].is_external && !(st->use_external))
  544. continue;
  545. st->trig[i] = at91_adc_allocate_trigger(idev,
  546. st->trigger_list + i);
  547. if (st->trig[i] == NULL) {
  548. dev_err(&idev->dev,
  549. "Could not allocate trigger %d\n", i);
  550. ret = -ENOMEM;
  551. goto error_trigger;
  552. }
  553. }
  554. return 0;
  555. error_trigger:
  556. for (i--; i >= 0; i--) {
  557. iio_trigger_unregister(st->trig[i]);
  558. iio_trigger_free(st->trig[i]);
  559. }
  560. error_ret:
  561. return ret;
  562. }
  563. static void at91_adc_trigger_remove(struct iio_dev *idev)
  564. {
  565. struct at91_adc_state *st = iio_priv(idev);
  566. int i;
  567. for (i = 0; i < st->trigger_number; i++) {
  568. iio_trigger_unregister(st->trig[i]);
  569. iio_trigger_free(st->trig[i]);
  570. }
  571. }
  572. static int at91_adc_buffer_init(struct iio_dev *idev)
  573. {
  574. return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
  575. &at91_adc_trigger_handler, NULL);
  576. }
  577. static void at91_adc_buffer_remove(struct iio_dev *idev)
  578. {
  579. iio_triggered_buffer_cleanup(idev);
  580. }
  581. static int at91_adc_read_raw(struct iio_dev *idev,
  582. struct iio_chan_spec const *chan,
  583. int *val, int *val2, long mask)
  584. {
  585. struct at91_adc_state *st = iio_priv(idev);
  586. int ret;
  587. switch (mask) {
  588. case IIO_CHAN_INFO_RAW:
  589. mutex_lock(&st->lock);
  590. st->chnb = chan->channel;
  591. at91_adc_writel(st, AT91_ADC_CHER,
  592. AT91_ADC_CH(chan->channel));
  593. at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel));
  594. at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
  595. ret = wait_event_interruptible_timeout(st->wq_data_avail,
  596. st->done,
  597. msecs_to_jiffies(1000));
  598. /* Disable interrupts, regardless if adc conversion was
  599. * successful or not
  600. */
  601. at91_adc_writel(st, AT91_ADC_CHDR,
  602. AT91_ADC_CH(chan->channel));
  603. at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel));
  604. if (ret > 0) {
  605. /* a valid conversion took place */
  606. *val = st->last_value;
  607. st->last_value = 0;
  608. st->done = false;
  609. ret = IIO_VAL_INT;
  610. } else if (ret == 0) {
  611. /* conversion timeout */
  612. dev_err(&idev->dev, "ADC Channel %d timeout.\n",
  613. chan->channel);
  614. ret = -ETIMEDOUT;
  615. }
  616. mutex_unlock(&st->lock);
  617. return ret;
  618. case IIO_CHAN_INFO_SCALE:
  619. *val = st->vref_mv;
  620. *val2 = chan->scan_type.realbits;
  621. return IIO_VAL_FRACTIONAL_LOG2;
  622. default:
  623. break;
  624. }
  625. return -EINVAL;
  626. }
  627. static int at91_adc_of_get_resolution(struct iio_dev *idev,
  628. struct platform_device *pdev)
  629. {
  630. struct at91_adc_state *st = iio_priv(idev);
  631. struct device_node *np = pdev->dev.of_node;
  632. int count, i, ret = 0;
  633. char *res_name, *s;
  634. u32 *resolutions;
  635. count = of_property_count_strings(np, "atmel,adc-res-names");
  636. if (count < 2) {
  637. dev_err(&idev->dev, "You must specified at least two resolution names for "
  638. "adc-res-names property in the DT\n");
  639. return count;
  640. }
  641. resolutions = kmalloc_array(count, sizeof(*resolutions), GFP_KERNEL);
  642. if (!resolutions)
  643. return -ENOMEM;
  644. if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) {
  645. dev_err(&idev->dev, "Missing adc-res property in the DT.\n");
  646. ret = -ENODEV;
  647. goto ret;
  648. }
  649. if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name))
  650. res_name = "highres";
  651. for (i = 0; i < count; i++) {
  652. if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s))
  653. continue;
  654. if (strcmp(res_name, s))
  655. continue;
  656. st->res = resolutions[i];
  657. if (!strcmp(res_name, "lowres"))
  658. st->low_res = true;
  659. else
  660. st->low_res = false;
  661. dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
  662. goto ret;
  663. }
  664. dev_err(&idev->dev, "There is no resolution for %s\n", res_name);
  665. ret:
  666. kfree(resolutions);
  667. return ret;
  668. }
  669. static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz)
  670. {
  671. /*
  672. * Number of ticks needed to cover the startup time of the ADC
  673. * as defined in the electrical characteristics of the board,
  674. * divided by 8. The formula thus is :
  675. * Startup Time = (ticks + 1) * 8 / ADC Clock
  676. */
  677. return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8;
  678. }
  679. static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz)
  680. {
  681. /*
  682. * For sama5d3x and at91sam9x5, the formula changes to:
  683. * Startup Time = <lookup_table_value> / ADC Clock
  684. */
  685. static const int startup_lookup[] = {
  686. 0, 8, 16, 24,
  687. 64, 80, 96, 112,
  688. 512, 576, 640, 704,
  689. 768, 832, 896, 960
  690. };
  691. int i, size = ARRAY_SIZE(startup_lookup);
  692. unsigned int ticks;
  693. ticks = startup_time * adc_clk_khz / 1000;
  694. for (i = 0; i < size; i++)
  695. if (ticks < startup_lookup[i])
  696. break;
  697. ticks = i;
  698. if (ticks == size)
  699. /* Reach the end of lookup table */
  700. ticks = size - 1;
  701. return ticks;
  702. }
  703. static const struct of_device_id at91_adc_dt_ids[];
  704. static int at91_adc_probe_dt_ts(struct device_node *node,
  705. struct at91_adc_state *st, struct device *dev)
  706. {
  707. int ret;
  708. u32 prop;
  709. ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop);
  710. if (ret) {
  711. dev_info(dev, "ADC Touch screen is disabled.\n");
  712. return 0;
  713. }
  714. switch (prop) {
  715. case 4:
  716. case 5:
  717. st->touchscreen_type = prop;
  718. break;
  719. default:
  720. dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop);
  721. return -EINVAL;
  722. }
  723. if (!st->caps->has_tsmr)
  724. return 0;
  725. prop = 0;
  726. of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop);
  727. st->ts_pressure_threshold = prop;
  728. if (st->ts_pressure_threshold) {
  729. return 0;
  730. } else {
  731. dev_err(dev, "Invalid pressure threshold for the touchscreen\n");
  732. return -EINVAL;
  733. }
  734. }
  735. static int at91_adc_probe_dt(struct iio_dev *idev,
  736. struct platform_device *pdev)
  737. {
  738. struct at91_adc_state *st = iio_priv(idev);
  739. struct device_node *node = pdev->dev.of_node;
  740. struct device_node *trig_node;
  741. int i = 0, ret;
  742. u32 prop;
  743. if (!node)
  744. return -EINVAL;
  745. st->caps = (struct at91_adc_caps *)
  746. of_match_device(at91_adc_dt_ids, &pdev->dev)->data;
  747. st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
  748. if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
  749. dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
  750. ret = -EINVAL;
  751. goto error_ret;
  752. }
  753. st->channels_mask = prop;
  754. st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode");
  755. if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
  756. dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
  757. ret = -EINVAL;
  758. goto error_ret;
  759. }
  760. st->startup_time = prop;
  761. prop = 0;
  762. of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop);
  763. st->sample_hold_time = prop;
  764. if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
  765. dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
  766. ret = -EINVAL;
  767. goto error_ret;
  768. }
  769. st->vref_mv = prop;
  770. ret = at91_adc_of_get_resolution(idev, pdev);
  771. if (ret)
  772. goto error_ret;
  773. st->registers = &st->caps->registers;
  774. st->num_channels = st->caps->num_channels;
  775. st->trigger_number = of_get_child_count(node);
  776. st->trigger_list = devm_kcalloc(&idev->dev,
  777. st->trigger_number,
  778. sizeof(struct at91_adc_trigger),
  779. GFP_KERNEL);
  780. if (!st->trigger_list) {
  781. dev_err(&idev->dev, "Could not allocate trigger list memory.\n");
  782. ret = -ENOMEM;
  783. goto error_ret;
  784. }
  785. for_each_child_of_node(node, trig_node) {
  786. struct at91_adc_trigger *trig = st->trigger_list + i;
  787. const char *name;
  788. if (of_property_read_string(trig_node, "trigger-name", &name)) {
  789. dev_err(&idev->dev, "Missing trigger-name property in the DT.\n");
  790. ret = -EINVAL;
  791. goto error_ret;
  792. }
  793. trig->name = name;
  794. if (of_property_read_u32(trig_node, "trigger-value", &prop)) {
  795. dev_err(&idev->dev, "Missing trigger-value property in the DT.\n");
  796. ret = -EINVAL;
  797. goto error_ret;
  798. }
  799. trig->value = prop;
  800. trig->is_external = of_property_read_bool(trig_node, "trigger-external");
  801. i++;
  802. }
  803. /* Check if touchscreen is supported. */
  804. if (st->caps->has_ts)
  805. return at91_adc_probe_dt_ts(node, st, &idev->dev);
  806. else
  807. dev_info(&idev->dev, "not support touchscreen in the adc compatible string.\n");
  808. return 0;
  809. error_ret:
  810. return ret;
  811. }
  812. static int at91_adc_probe_pdata(struct at91_adc_state *st,
  813. struct platform_device *pdev)
  814. {
  815. struct at91_adc_data *pdata = pdev->dev.platform_data;
  816. if (!pdata)
  817. return -EINVAL;
  818. st->caps = (struct at91_adc_caps *)
  819. platform_get_device_id(pdev)->driver_data;
  820. st->use_external = pdata->use_external_triggers;
  821. st->vref_mv = pdata->vref;
  822. st->channels_mask = pdata->channels_used;
  823. st->num_channels = st->caps->num_channels;
  824. st->startup_time = pdata->startup_time;
  825. st->trigger_number = pdata->trigger_number;
  826. st->trigger_list = pdata->trigger_list;
  827. st->registers = &st->caps->registers;
  828. st->touchscreen_type = pdata->touchscreen_type;
  829. return 0;
  830. }
  831. static const struct iio_info at91_adc_info = {
  832. .read_raw = &at91_adc_read_raw,
  833. };
  834. /* Touchscreen related functions */
  835. static int atmel_ts_open(struct input_dev *dev)
  836. {
  837. struct at91_adc_state *st = input_get_drvdata(dev);
  838. if (st->caps->has_tsmr)
  839. at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
  840. else
  841. at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
  842. return 0;
  843. }
  844. static void atmel_ts_close(struct input_dev *dev)
  845. {
  846. struct at91_adc_state *st = input_get_drvdata(dev);
  847. if (st->caps->has_tsmr)
  848. at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
  849. else
  850. at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
  851. }
  852. static int at91_ts_hw_init(struct iio_dev *idev, u32 adc_clk_khz)
  853. {
  854. struct at91_adc_state *st = iio_priv(idev);
  855. u32 reg = 0;
  856. u32 tssctim = 0;
  857. int i = 0;
  858. /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid
  859. * pen detect noise.
  860. * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock
  861. */
  862. st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz /
  863. 1000, 1);
  864. while (st->ts_pendbc >> ++i)
  865. ; /* Empty! Find the shift offset */
  866. if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1))))
  867. st->ts_pendbc = i;
  868. else
  869. st->ts_pendbc = i - 1;
  870. if (!st->caps->has_tsmr) {
  871. reg = at91_adc_readl(st, AT91_ADC_MR);
  872. reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET;
  873. reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
  874. at91_adc_writel(st, AT91_ADC_MR, reg);
  875. reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM;
  876. at91_adc_writel(st, AT91_ADC_TSR, reg);
  877. st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL *
  878. adc_clk_khz / 1000) - 1, 1);
  879. return 0;
  880. }
  881. /* Touchscreen Switches Closure time needed for allowing the value to
  882. * stabilize.
  883. * Switch Closure Time = (TSSCTIM * 4) ADCClock periods
  884. */
  885. tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4);
  886. dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n",
  887. adc_clk_khz, tssctim);
  888. if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
  889. reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS;
  890. else
  891. reg = AT91_ADC_TSMR_TSMODE_5WIRE;
  892. reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM;
  893. reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average)
  894. & AT91_ADC_TSMR_TSAV;
  895. reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC;
  896. reg |= AT91_ADC_TSMR_NOTSDMA;
  897. reg |= AT91_ADC_TSMR_PENDET_ENA;
  898. reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */
  899. at91_adc_writel(st, AT91_ADC_TSMR, reg);
  900. /* Change adc internal resistor value for better pen detection,
  901. * default value is 100 kOhm.
  902. * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm
  903. * option only available on ES2 and higher
  904. */
  905. at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity
  906. & AT91_ADC_ACR_PENDETSENS);
  907. /* Sample Period Time = (TRGPER + 1) / ADCClock */
  908. st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US *
  909. adc_clk_khz / 1000) - 1, 1);
  910. return 0;
  911. }
  912. static int at91_ts_register(struct iio_dev *idev,
  913. struct platform_device *pdev)
  914. {
  915. struct at91_adc_state *st = iio_priv(idev);
  916. struct input_dev *input;
  917. int ret;
  918. input = input_allocate_device();
  919. if (!input) {
  920. dev_err(&idev->dev, "Failed to allocate TS device!\n");
  921. return -ENOMEM;
  922. }
  923. input->name = DRIVER_NAME;
  924. input->id.bustype = BUS_HOST;
  925. input->dev.parent = &pdev->dev;
  926. input->open = atmel_ts_open;
  927. input->close = atmel_ts_close;
  928. __set_bit(EV_ABS, input->evbit);
  929. __set_bit(EV_KEY, input->evbit);
  930. __set_bit(BTN_TOUCH, input->keybit);
  931. if (st->caps->has_tsmr) {
  932. input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1,
  933. 0, 0);
  934. input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1,
  935. 0, 0);
  936. input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0);
  937. } else {
  938. if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) {
  939. dev_err(&pdev->dev,
  940. "This touchscreen controller only support 4 wires\n");
  941. ret = -EINVAL;
  942. goto err;
  943. }
  944. input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1,
  945. 0, 0);
  946. input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1,
  947. 0, 0);
  948. }
  949. st->ts_input = input;
  950. input_set_drvdata(input, st);
  951. ret = input_register_device(input);
  952. if (ret)
  953. goto err;
  954. return ret;
  955. err:
  956. input_free_device(st->ts_input);
  957. return ret;
  958. }
  959. static void at91_ts_unregister(struct at91_adc_state *st)
  960. {
  961. input_unregister_device(st->ts_input);
  962. }
  963. static int at91_adc_probe(struct platform_device *pdev)
  964. {
  965. unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
  966. int ret;
  967. struct iio_dev *idev;
  968. struct at91_adc_state *st;
  969. u32 reg;
  970. idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state));
  971. if (!idev)
  972. return -ENOMEM;
  973. st = iio_priv(idev);
  974. if (pdev->dev.of_node)
  975. ret = at91_adc_probe_dt(idev, pdev);
  976. else
  977. ret = at91_adc_probe_pdata(st, pdev);
  978. if (ret) {
  979. dev_err(&pdev->dev, "No platform data available.\n");
  980. return -EINVAL;
  981. }
  982. platform_set_drvdata(pdev, idev);
  983. idev->name = dev_name(&pdev->dev);
  984. idev->modes = INDIO_DIRECT_MODE;
  985. idev->info = &at91_adc_info;
  986. st->irq = platform_get_irq(pdev, 0);
  987. if (st->irq < 0)
  988. return -ENODEV;
  989. st->reg_base = devm_platform_ioremap_resource(pdev, 0);
  990. if (IS_ERR(st->reg_base))
  991. return PTR_ERR(st->reg_base);
  992. /*
  993. * Disable all IRQs before setting up the handler
  994. */
  995. at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
  996. at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
  997. if (st->caps->has_tsmr)
  998. ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0,
  999. pdev->dev.driver->name, idev);
  1000. else
  1001. ret = request_irq(st->irq, at91_adc_rl_interrupt, 0,
  1002. pdev->dev.driver->name, idev);
  1003. if (ret) {
  1004. dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
  1005. return ret;
  1006. }
  1007. st->clk = devm_clk_get(&pdev->dev, "adc_clk");
  1008. if (IS_ERR(st->clk)) {
  1009. dev_err(&pdev->dev, "Failed to get the clock.\n");
  1010. ret = PTR_ERR(st->clk);
  1011. goto error_free_irq;
  1012. }
  1013. ret = clk_prepare_enable(st->clk);
  1014. if (ret) {
  1015. dev_err(&pdev->dev,
  1016. "Could not prepare or enable the clock.\n");
  1017. goto error_free_irq;
  1018. }
  1019. st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
  1020. if (IS_ERR(st->adc_clk)) {
  1021. dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
  1022. ret = PTR_ERR(st->adc_clk);
  1023. goto error_disable_clk;
  1024. }
  1025. ret = clk_prepare_enable(st->adc_clk);
  1026. if (ret) {
  1027. dev_err(&pdev->dev,
  1028. "Could not prepare or enable the ADC clock.\n");
  1029. goto error_disable_clk;
  1030. }
  1031. /*
  1032. * Prescaler rate computation using the formula from the Atmel's
  1033. * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
  1034. * specified by the electrical characteristics of the board.
  1035. */
  1036. mstrclk = clk_get_rate(st->clk);
  1037. adc_clk = clk_get_rate(st->adc_clk);
  1038. adc_clk_khz = adc_clk / 1000;
  1039. dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n",
  1040. mstrclk, adc_clk);
  1041. prsc = (mstrclk / (2 * adc_clk)) - 1;
  1042. if (!st->startup_time) {
  1043. dev_err(&pdev->dev, "No startup time available.\n");
  1044. ret = -EINVAL;
  1045. goto error_disable_adc_clk;
  1046. }
  1047. ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz);
  1048. /*
  1049. * a minimal Sample and Hold Time is necessary for the ADC to guarantee
  1050. * the best converted final value between two channels selection
  1051. * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
  1052. */
  1053. if (st->sample_hold_time > 0)
  1054. shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000)
  1055. - 1, 1);
  1056. else
  1057. shtim = 0;
  1058. reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
  1059. reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
  1060. if (st->low_res)
  1061. reg |= AT91_ADC_LOWRES;
  1062. if (st->sleep_mode)
  1063. reg |= AT91_ADC_SLEEP;
  1064. reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM;
  1065. at91_adc_writel(st, AT91_ADC_MR, reg);
  1066. /* Setup the ADC channels available on the board */
  1067. ret = at91_adc_channel_init(idev);
  1068. if (ret < 0) {
  1069. dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
  1070. goto error_disable_adc_clk;
  1071. }
  1072. init_waitqueue_head(&st->wq_data_avail);
  1073. mutex_init(&st->lock);
  1074. /*
  1075. * Since touch screen will set trigger register as period trigger. So
  1076. * when touch screen is enabled, then we have to disable hardware
  1077. * trigger for classic adc.
  1078. */
  1079. if (!st->touchscreen_type) {
  1080. ret = at91_adc_buffer_init(idev);
  1081. if (ret < 0) {
  1082. dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
  1083. goto error_disable_adc_clk;
  1084. }
  1085. ret = at91_adc_trigger_init(idev);
  1086. if (ret < 0) {
  1087. dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
  1088. at91_adc_buffer_remove(idev);
  1089. goto error_disable_adc_clk;
  1090. }
  1091. } else {
  1092. ret = at91_ts_register(idev, pdev);
  1093. if (ret)
  1094. goto error_disable_adc_clk;
  1095. at91_ts_hw_init(idev, adc_clk_khz);
  1096. }
  1097. ret = iio_device_register(idev);
  1098. if (ret < 0) {
  1099. dev_err(&pdev->dev, "Couldn't register the device.\n");
  1100. goto error_iio_device_register;
  1101. }
  1102. return 0;
  1103. error_iio_device_register:
  1104. if (!st->touchscreen_type) {
  1105. at91_adc_trigger_remove(idev);
  1106. at91_adc_buffer_remove(idev);
  1107. } else {
  1108. at91_ts_unregister(st);
  1109. }
  1110. error_disable_adc_clk:
  1111. clk_disable_unprepare(st->adc_clk);
  1112. error_disable_clk:
  1113. clk_disable_unprepare(st->clk);
  1114. error_free_irq:
  1115. free_irq(st->irq, idev);
  1116. return ret;
  1117. }
  1118. static int at91_adc_remove(struct platform_device *pdev)
  1119. {
  1120. struct iio_dev *idev = platform_get_drvdata(pdev);
  1121. struct at91_adc_state *st = iio_priv(idev);
  1122. iio_device_unregister(idev);
  1123. if (!st->touchscreen_type) {
  1124. at91_adc_trigger_remove(idev);
  1125. at91_adc_buffer_remove(idev);
  1126. } else {
  1127. at91_ts_unregister(st);
  1128. }
  1129. clk_disable_unprepare(st->adc_clk);
  1130. clk_disable_unprepare(st->clk);
  1131. free_irq(st->irq, idev);
  1132. return 0;
  1133. }
  1134. #ifdef CONFIG_PM_SLEEP
  1135. static int at91_adc_suspend(struct device *dev)
  1136. {
  1137. struct iio_dev *idev = dev_get_drvdata(dev);
  1138. struct at91_adc_state *st = iio_priv(idev);
  1139. pinctrl_pm_select_sleep_state(dev);
  1140. clk_disable_unprepare(st->clk);
  1141. return 0;
  1142. }
  1143. static int at91_adc_resume(struct device *dev)
  1144. {
  1145. struct iio_dev *idev = dev_get_drvdata(dev);
  1146. struct at91_adc_state *st = iio_priv(idev);
  1147. clk_prepare_enable(st->clk);
  1148. pinctrl_pm_select_default_state(dev);
  1149. return 0;
  1150. }
  1151. #endif
  1152. static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume);
  1153. static struct at91_adc_caps at91sam9260_caps = {
  1154. .calc_startup_ticks = calc_startup_ticks_9260,
  1155. .num_channels = 4,
  1156. .registers = {
  1157. .channel_base = AT91_ADC_CHR(0),
  1158. .drdy_mask = AT91_ADC_DRDY,
  1159. .status_register = AT91_ADC_SR,
  1160. .trigger_register = AT91_ADC_TRGR_9260,
  1161. .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
  1162. .mr_startup_mask = AT91_ADC_STARTUP_9260,
  1163. },
  1164. };
  1165. static struct at91_adc_caps at91sam9rl_caps = {
  1166. .has_ts = true,
  1167. .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
  1168. .num_channels = 6,
  1169. .registers = {
  1170. .channel_base = AT91_ADC_CHR(0),
  1171. .drdy_mask = AT91_ADC_DRDY,
  1172. .status_register = AT91_ADC_SR,
  1173. .trigger_register = AT91_ADC_TRGR_9G45,
  1174. .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
  1175. .mr_startup_mask = AT91_ADC_STARTUP_9G45,
  1176. },
  1177. };
  1178. static struct at91_adc_caps at91sam9g45_caps = {
  1179. .has_ts = true,
  1180. .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
  1181. .num_channels = 8,
  1182. .registers = {
  1183. .channel_base = AT91_ADC_CHR(0),
  1184. .drdy_mask = AT91_ADC_DRDY,
  1185. .status_register = AT91_ADC_SR,
  1186. .trigger_register = AT91_ADC_TRGR_9G45,
  1187. .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
  1188. .mr_startup_mask = AT91_ADC_STARTUP_9G45,
  1189. },
  1190. };
  1191. static struct at91_adc_caps at91sam9x5_caps = {
  1192. .has_ts = true,
  1193. .has_tsmr = true,
  1194. .ts_filter_average = 3,
  1195. .ts_pen_detect_sensitivity = 2,
  1196. .calc_startup_ticks = calc_startup_ticks_9x5,
  1197. .num_channels = 12,
  1198. .registers = {
  1199. .channel_base = AT91_ADC_CDR0_9X5,
  1200. .drdy_mask = AT91_ADC_SR_DRDY_9X5,
  1201. .status_register = AT91_ADC_SR_9X5,
  1202. .trigger_register = AT91_ADC_TRGR_9X5,
  1203. /* prescal mask is same as 9G45 */
  1204. .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
  1205. .mr_startup_mask = AT91_ADC_STARTUP_9X5,
  1206. },
  1207. };
  1208. static const struct of_device_id at91_adc_dt_ids[] = {
  1209. { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps },
  1210. { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps },
  1211. { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps },
  1212. { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps },
  1213. {},
  1214. };
  1215. MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
  1216. static const struct platform_device_id at91_adc_ids[] = {
  1217. {
  1218. .name = "at91sam9260-adc",
  1219. .driver_data = (unsigned long)&at91sam9260_caps,
  1220. }, {
  1221. .name = "at91sam9rl-adc",
  1222. .driver_data = (unsigned long)&at91sam9rl_caps,
  1223. }, {
  1224. .name = "at91sam9g45-adc",
  1225. .driver_data = (unsigned long)&at91sam9g45_caps,
  1226. }, {
  1227. .name = "at91sam9x5-adc",
  1228. .driver_data = (unsigned long)&at91sam9x5_caps,
  1229. }, {
  1230. /* terminator */
  1231. }
  1232. };
  1233. MODULE_DEVICE_TABLE(platform, at91_adc_ids);
  1234. static struct platform_driver at91_adc_driver = {
  1235. .probe = at91_adc_probe,
  1236. .remove = at91_adc_remove,
  1237. .id_table = at91_adc_ids,
  1238. .driver = {
  1239. .name = DRIVER_NAME,
  1240. .of_match_table = at91_adc_dt_ids,
  1241. .pm = &at91_adc_pm_ops,
  1242. },
  1243. };
  1244. module_platform_driver(at91_adc_driver);
  1245. MODULE_LICENSE("GPL");
  1246. MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
  1247. MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");