at91-sama5d2_adc.c 56 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Atmel ADC driver for SAMA5D2 devices and compatible.
  4. *
  5. * Copyright (C) 2015 Atmel,
  6. * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/dmaengine.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/module.h>
  16. #include <linux/of_device.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/sched.h>
  19. #include <linux/wait.h>
  20. #include <linux/iio/iio.h>
  21. #include <linux/iio/sysfs.h>
  22. #include <linux/iio/buffer.h>
  23. #include <linux/iio/trigger.h>
  24. #include <linux/iio/trigger_consumer.h>
  25. #include <linux/iio/triggered_buffer.h>
  26. #include <linux/pinctrl/consumer.h>
  27. #include <linux/regulator/consumer.h>
  28. /* Control Register */
  29. #define AT91_SAMA5D2_CR 0x00
  30. /* Software Reset */
  31. #define AT91_SAMA5D2_CR_SWRST BIT(0)
  32. /* Start Conversion */
  33. #define AT91_SAMA5D2_CR_START BIT(1)
  34. /* Touchscreen Calibration */
  35. #define AT91_SAMA5D2_CR_TSCALIB BIT(2)
  36. /* Comparison Restart */
  37. #define AT91_SAMA5D2_CR_CMPRST BIT(4)
  38. /* Mode Register */
  39. #define AT91_SAMA5D2_MR 0x04
  40. /* Trigger Selection */
  41. #define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1)
  42. /* ADTRG */
  43. #define AT91_SAMA5D2_MR_TRGSEL_TRIG0 0
  44. /* TIOA0 */
  45. #define AT91_SAMA5D2_MR_TRGSEL_TRIG1 1
  46. /* TIOA1 */
  47. #define AT91_SAMA5D2_MR_TRGSEL_TRIG2 2
  48. /* TIOA2 */
  49. #define AT91_SAMA5D2_MR_TRGSEL_TRIG3 3
  50. /* PWM event line 0 */
  51. #define AT91_SAMA5D2_MR_TRGSEL_TRIG4 4
  52. /* PWM event line 1 */
  53. #define AT91_SAMA5D2_MR_TRGSEL_TRIG5 5
  54. /* TIOA3 */
  55. #define AT91_SAMA5D2_MR_TRGSEL_TRIG6 6
  56. /* RTCOUT0 */
  57. #define AT91_SAMA5D2_MR_TRGSEL_TRIG7 7
  58. /* Sleep Mode */
  59. #define AT91_SAMA5D2_MR_SLEEP BIT(5)
  60. /* Fast Wake Up */
  61. #define AT91_SAMA5D2_MR_FWUP BIT(6)
  62. /* Prescaler Rate Selection */
  63. #define AT91_SAMA5D2_MR_PRESCAL(v) ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET)
  64. #define AT91_SAMA5D2_MR_PRESCAL_OFFSET 8
  65. #define AT91_SAMA5D2_MR_PRESCAL_MAX 0xff
  66. #define AT91_SAMA5D2_MR_PRESCAL_MASK GENMASK(15, 8)
  67. /* Startup Time */
  68. #define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16)
  69. #define AT91_SAMA5D2_MR_STARTUP_MASK GENMASK(19, 16)
  70. /* Analog Change */
  71. #define AT91_SAMA5D2_MR_ANACH BIT(23)
  72. /* Tracking Time */
  73. #define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24)
  74. #define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xff
  75. /* Transfer Time */
  76. #define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28)
  77. #define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3
  78. /* Use Sequence Enable */
  79. #define AT91_SAMA5D2_MR_USEQ BIT(31)
  80. /* Channel Sequence Register 1 */
  81. #define AT91_SAMA5D2_SEQR1 0x08
  82. /* Channel Sequence Register 2 */
  83. #define AT91_SAMA5D2_SEQR2 0x0c
  84. /* Channel Enable Register */
  85. #define AT91_SAMA5D2_CHER 0x10
  86. /* Channel Disable Register */
  87. #define AT91_SAMA5D2_CHDR 0x14
  88. /* Channel Status Register */
  89. #define AT91_SAMA5D2_CHSR 0x18
  90. /* Last Converted Data Register */
  91. #define AT91_SAMA5D2_LCDR 0x20
  92. /* Interrupt Enable Register */
  93. #define AT91_SAMA5D2_IER 0x24
  94. /* Interrupt Enable Register - TS X measurement ready */
  95. #define AT91_SAMA5D2_IER_XRDY BIT(20)
  96. /* Interrupt Enable Register - TS Y measurement ready */
  97. #define AT91_SAMA5D2_IER_YRDY BIT(21)
  98. /* Interrupt Enable Register - TS pressure measurement ready */
  99. #define AT91_SAMA5D2_IER_PRDY BIT(22)
  100. /* Interrupt Enable Register - Data ready */
  101. #define AT91_SAMA5D2_IER_DRDY BIT(24)
  102. /* Interrupt Enable Register - general overrun error */
  103. #define AT91_SAMA5D2_IER_GOVRE BIT(25)
  104. /* Interrupt Enable Register - Pen detect */
  105. #define AT91_SAMA5D2_IER_PEN BIT(29)
  106. /* Interrupt Enable Register - No pen detect */
  107. #define AT91_SAMA5D2_IER_NOPEN BIT(30)
  108. /* Interrupt Disable Register */
  109. #define AT91_SAMA5D2_IDR 0x28
  110. /* Interrupt Mask Register */
  111. #define AT91_SAMA5D2_IMR 0x2c
  112. /* Interrupt Status Register */
  113. #define AT91_SAMA5D2_ISR 0x30
  114. /* Interrupt Status Register - Pen touching sense status */
  115. #define AT91_SAMA5D2_ISR_PENS BIT(31)
  116. /* Last Channel Trigger Mode Register */
  117. #define AT91_SAMA5D2_LCTMR 0x34
  118. /* Last Channel Compare Window Register */
  119. #define AT91_SAMA5D2_LCCWR 0x38
  120. /* Overrun Status Register */
  121. #define AT91_SAMA5D2_OVER 0x3c
  122. /* Extended Mode Register */
  123. #define AT91_SAMA5D2_EMR 0x40
  124. /* Extended Mode Register - Oversampling rate */
  125. #define AT91_SAMA5D2_EMR_OSR(V) ((V) << 16)
  126. #define AT91_SAMA5D2_EMR_OSR_MASK GENMASK(17, 16)
  127. #define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0
  128. #define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1
  129. #define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2
  130. /* Extended Mode Register - Averaging on single trigger event */
  131. #define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20)
  132. /* Compare Window Register */
  133. #define AT91_SAMA5D2_CWR 0x44
  134. /* Channel Gain Register */
  135. #define AT91_SAMA5D2_CGR 0x48
  136. /* Channel Offset Register */
  137. #define AT91_SAMA5D2_COR 0x4c
  138. #define AT91_SAMA5D2_COR_DIFF_OFFSET 16
  139. /* Channel Data Register 0 */
  140. #define AT91_SAMA5D2_CDR0 0x50
  141. /* Analog Control Register */
  142. #define AT91_SAMA5D2_ACR 0x94
  143. /* Analog Control Register - Pen detect sensitivity mask */
  144. #define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0)
  145. /* Touchscreen Mode Register */
  146. #define AT91_SAMA5D2_TSMR 0xb0
  147. /* Touchscreen Mode Register - No touch mode */
  148. #define AT91_SAMA5D2_TSMR_TSMODE_NONE 0
  149. /* Touchscreen Mode Register - 4 wire screen, no pressure measurement */
  150. #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_NO_PRESS 1
  151. /* Touchscreen Mode Register - 4 wire screen, pressure measurement */
  152. #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS 2
  153. /* Touchscreen Mode Register - 5 wire screen */
  154. #define AT91_SAMA5D2_TSMR_TSMODE_5WIRE 3
  155. /* Touchscreen Mode Register - Average samples mask */
  156. #define AT91_SAMA5D2_TSMR_TSAV_MASK GENMASK(5, 4)
  157. /* Touchscreen Mode Register - Average samples */
  158. #define AT91_SAMA5D2_TSMR_TSAV(x) ((x) << 4)
  159. /* Touchscreen Mode Register - Touch/trigger frequency ratio mask */
  160. #define AT91_SAMA5D2_TSMR_TSFREQ_MASK GENMASK(11, 8)
  161. /* Touchscreen Mode Register - Touch/trigger frequency ratio */
  162. #define AT91_SAMA5D2_TSMR_TSFREQ(x) ((x) << 8)
  163. /* Touchscreen Mode Register - Pen Debounce Time mask */
  164. #define AT91_SAMA5D2_TSMR_PENDBC_MASK GENMASK(31, 28)
  165. /* Touchscreen Mode Register - Pen Debounce Time */
  166. #define AT91_SAMA5D2_TSMR_PENDBC(x) ((x) << 28)
  167. /* Touchscreen Mode Register - No DMA for touch measurements */
  168. #define AT91_SAMA5D2_TSMR_NOTSDMA BIT(22)
  169. /* Touchscreen Mode Register - Disable pen detection */
  170. #define AT91_SAMA5D2_TSMR_PENDET_DIS (0 << 24)
  171. /* Touchscreen Mode Register - Enable pen detection */
  172. #define AT91_SAMA5D2_TSMR_PENDET_ENA BIT(24)
  173. /* Touchscreen X Position Register */
  174. #define AT91_SAMA5D2_XPOSR 0xb4
  175. /* Touchscreen Y Position Register */
  176. #define AT91_SAMA5D2_YPOSR 0xb8
  177. /* Touchscreen Pressure Register */
  178. #define AT91_SAMA5D2_PRESSR 0xbc
  179. /* Trigger Register */
  180. #define AT91_SAMA5D2_TRGR 0xc0
  181. /* Mask for TRGMOD field of TRGR register */
  182. #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0)
  183. /* No trigger, only software trigger can start conversions */
  184. #define AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER 0
  185. /* Trigger Mode external trigger rising edge */
  186. #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE 1
  187. /* Trigger Mode external trigger falling edge */
  188. #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL 2
  189. /* Trigger Mode external trigger any edge */
  190. #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY 3
  191. /* Trigger Mode internal periodic */
  192. #define AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC 5
  193. /* Trigger Mode - trigger period mask */
  194. #define AT91_SAMA5D2_TRGR_TRGPER_MASK GENMASK(31, 16)
  195. /* Trigger Mode - trigger period */
  196. #define AT91_SAMA5D2_TRGR_TRGPER(x) ((x) << 16)
  197. /* Correction Select Register */
  198. #define AT91_SAMA5D2_COSR 0xd0
  199. /* Correction Value Register */
  200. #define AT91_SAMA5D2_CVR 0xd4
  201. /* Channel Error Correction Register */
  202. #define AT91_SAMA5D2_CECR 0xd8
  203. /* Write Protection Mode Register */
  204. #define AT91_SAMA5D2_WPMR 0xe4
  205. /* Write Protection Status Register */
  206. #define AT91_SAMA5D2_WPSR 0xe8
  207. /* Version Register */
  208. #define AT91_SAMA5D2_VERSION 0xfc
  209. #define AT91_SAMA5D2_HW_TRIG_CNT 3
  210. #define AT91_SAMA5D2_SINGLE_CHAN_CNT 12
  211. #define AT91_SAMA5D2_DIFF_CHAN_CNT 6
  212. #define AT91_SAMA5D2_TIMESTAMP_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \
  213. AT91_SAMA5D2_DIFF_CHAN_CNT + 1)
  214. #define AT91_SAMA5D2_TOUCH_X_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \
  215. AT91_SAMA5D2_DIFF_CHAN_CNT * 2)
  216. #define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX (AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1)
  217. #define AT91_SAMA5D2_TOUCH_P_CHAN_IDX (AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1)
  218. #define AT91_SAMA5D2_MAX_CHAN_IDX AT91_SAMA5D2_TOUCH_P_CHAN_IDX
  219. #define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
  220. #define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US 200
  221. #define AT91_SAMA5D2_XYZ_MASK GENMASK(11, 0)
  222. #define AT91_SAMA5D2_MAX_POS_BITS 12
  223. /*
  224. * Maximum number of bytes to hold conversion from all channels
  225. * without the timestamp.
  226. */
  227. #define AT91_BUFFER_MAX_CONVERSION_BYTES ((AT91_SAMA5D2_SINGLE_CHAN_CNT + \
  228. AT91_SAMA5D2_DIFF_CHAN_CNT) * 2)
  229. /* This total must also include the timestamp */
  230. #define AT91_BUFFER_MAX_BYTES (AT91_BUFFER_MAX_CONVERSION_BYTES + 8)
  231. #define AT91_BUFFER_MAX_HWORDS (AT91_BUFFER_MAX_BYTES / 2)
  232. #define AT91_HWFIFO_MAX_SIZE_STR "128"
  233. #define AT91_HWFIFO_MAX_SIZE 128
  234. /* Possible values for oversampling ratio */
  235. #define AT91_OSR_1SAMPLES 1
  236. #define AT91_OSR_4SAMPLES 4
  237. #define AT91_OSR_16SAMPLES 16
  238. #define AT91_SAMA5D2_CHAN_SINGLE(num, addr) \
  239. { \
  240. .type = IIO_VOLTAGE, \
  241. .channel = num, \
  242. .address = addr, \
  243. .scan_index = num, \
  244. .scan_type = { \
  245. .sign = 'u', \
  246. .realbits = 14, \
  247. .storagebits = 16, \
  248. }, \
  249. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  250. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  251. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
  252. BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
  253. .datasheet_name = "CH"#num, \
  254. .indexed = 1, \
  255. }
  256. #define AT91_SAMA5D2_CHAN_DIFF(num, num2, addr) \
  257. { \
  258. .type = IIO_VOLTAGE, \
  259. .differential = 1, \
  260. .channel = num, \
  261. .channel2 = num2, \
  262. .address = addr, \
  263. .scan_index = num + AT91_SAMA5D2_SINGLE_CHAN_CNT, \
  264. .scan_type = { \
  265. .sign = 's', \
  266. .realbits = 14, \
  267. .storagebits = 16, \
  268. }, \
  269. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  270. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  271. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
  272. BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
  273. .datasheet_name = "CH"#num"-CH"#num2, \
  274. .indexed = 1, \
  275. }
  276. #define AT91_SAMA5D2_CHAN_TOUCH(num, name, mod) \
  277. { \
  278. .type = IIO_POSITIONRELATIVE, \
  279. .modified = 1, \
  280. .channel = num, \
  281. .channel2 = mod, \
  282. .scan_index = num, \
  283. .scan_type = { \
  284. .sign = 'u', \
  285. .realbits = 12, \
  286. .storagebits = 16, \
  287. }, \
  288. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  289. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
  290. BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
  291. .datasheet_name = name, \
  292. }
  293. #define AT91_SAMA5D2_CHAN_PRESSURE(num, name) \
  294. { \
  295. .type = IIO_PRESSURE, \
  296. .channel = num, \
  297. .scan_index = num, \
  298. .scan_type = { \
  299. .sign = 'u', \
  300. .realbits = 12, \
  301. .storagebits = 16, \
  302. }, \
  303. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  304. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
  305. BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
  306. .datasheet_name = name, \
  307. }
  308. #define at91_adc_readl(st, reg) readl_relaxed(st->base + reg)
  309. #define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg)
  310. struct at91_adc_soc_info {
  311. unsigned startup_time;
  312. unsigned min_sample_rate;
  313. unsigned max_sample_rate;
  314. };
  315. struct at91_adc_trigger {
  316. char *name;
  317. unsigned int trgmod_value;
  318. unsigned int edge_type;
  319. bool hw_trig;
  320. };
  321. /**
  322. * struct at91_adc_dma - at91-sama5d2 dma information struct
  323. * @dma_chan: the dma channel acquired
  324. * @rx_buf: dma coherent allocated area
  325. * @rx_dma_buf: dma handler for the buffer
  326. * @phys_addr: physical address of the ADC base register
  327. * @buf_idx: index inside the dma buffer where reading was last done
  328. * @rx_buf_sz: size of buffer used by DMA operation
  329. * @watermark: number of conversions to copy before DMA triggers irq
  330. * @dma_ts: hold the start timestamp of dma operation
  331. */
  332. struct at91_adc_dma {
  333. struct dma_chan *dma_chan;
  334. u8 *rx_buf;
  335. dma_addr_t rx_dma_buf;
  336. phys_addr_t phys_addr;
  337. int buf_idx;
  338. int rx_buf_sz;
  339. int watermark;
  340. s64 dma_ts;
  341. };
  342. /**
  343. * struct at91_adc_touch - at91-sama5d2 touchscreen information struct
  344. * @sample_period_val: the value for periodic trigger interval
  345. * @touching: is the pen touching the screen or not
  346. * @x_pos: temporary placeholder for pressure computation
  347. * @channels_bitmask: bitmask with the touchscreen channels enabled
  348. * @workq: workqueue for buffer data pushing
  349. */
  350. struct at91_adc_touch {
  351. u16 sample_period_val;
  352. bool touching;
  353. u16 x_pos;
  354. unsigned long channels_bitmask;
  355. struct work_struct workq;
  356. };
  357. struct at91_adc_state {
  358. void __iomem *base;
  359. int irq;
  360. struct clk *per_clk;
  361. struct regulator *reg;
  362. struct regulator *vref;
  363. int vref_uv;
  364. unsigned int current_sample_rate;
  365. struct iio_trigger *trig;
  366. const struct at91_adc_trigger *selected_trig;
  367. const struct iio_chan_spec *chan;
  368. bool conversion_done;
  369. u32 conversion_value;
  370. unsigned int oversampling_ratio;
  371. struct at91_adc_soc_info soc_info;
  372. wait_queue_head_t wq_data_available;
  373. struct at91_adc_dma dma_st;
  374. struct at91_adc_touch touch_st;
  375. struct iio_dev *indio_dev;
  376. /* Ensure naturally aligned timestamp */
  377. u16 buffer[AT91_BUFFER_MAX_HWORDS] __aligned(8);
  378. /*
  379. * lock to prevent concurrent 'single conversion' requests through
  380. * sysfs.
  381. */
  382. struct mutex lock;
  383. };
  384. static const struct at91_adc_trigger at91_adc_trigger_list[] = {
  385. {
  386. .name = "external_rising",
  387. .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE,
  388. .edge_type = IRQ_TYPE_EDGE_RISING,
  389. .hw_trig = true,
  390. },
  391. {
  392. .name = "external_falling",
  393. .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL,
  394. .edge_type = IRQ_TYPE_EDGE_FALLING,
  395. .hw_trig = true,
  396. },
  397. {
  398. .name = "external_any",
  399. .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY,
  400. .edge_type = IRQ_TYPE_EDGE_BOTH,
  401. .hw_trig = true,
  402. },
  403. {
  404. .name = "software",
  405. .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER,
  406. .edge_type = IRQ_TYPE_NONE,
  407. .hw_trig = false,
  408. },
  409. };
  410. static const struct iio_chan_spec at91_adc_channels[] = {
  411. AT91_SAMA5D2_CHAN_SINGLE(0, 0x50),
  412. AT91_SAMA5D2_CHAN_SINGLE(1, 0x54),
  413. AT91_SAMA5D2_CHAN_SINGLE(2, 0x58),
  414. AT91_SAMA5D2_CHAN_SINGLE(3, 0x5c),
  415. AT91_SAMA5D2_CHAN_SINGLE(4, 0x60),
  416. AT91_SAMA5D2_CHAN_SINGLE(5, 0x64),
  417. AT91_SAMA5D2_CHAN_SINGLE(6, 0x68),
  418. AT91_SAMA5D2_CHAN_SINGLE(7, 0x6c),
  419. AT91_SAMA5D2_CHAN_SINGLE(8, 0x70),
  420. AT91_SAMA5D2_CHAN_SINGLE(9, 0x74),
  421. AT91_SAMA5D2_CHAN_SINGLE(10, 0x78),
  422. AT91_SAMA5D2_CHAN_SINGLE(11, 0x7c),
  423. AT91_SAMA5D2_CHAN_DIFF(0, 1, 0x50),
  424. AT91_SAMA5D2_CHAN_DIFF(2, 3, 0x58),
  425. AT91_SAMA5D2_CHAN_DIFF(4, 5, 0x60),
  426. AT91_SAMA5D2_CHAN_DIFF(6, 7, 0x68),
  427. AT91_SAMA5D2_CHAN_DIFF(8, 9, 0x70),
  428. AT91_SAMA5D2_CHAN_DIFF(10, 11, 0x78),
  429. IIO_CHAN_SOFT_TIMESTAMP(AT91_SAMA5D2_TIMESTAMP_CHAN_IDX),
  430. AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_X_CHAN_IDX, "x", IIO_MOD_X),
  431. AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, "y", IIO_MOD_Y),
  432. AT91_SAMA5D2_CHAN_PRESSURE(AT91_SAMA5D2_TOUCH_P_CHAN_IDX, "pressure"),
  433. };
  434. static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan)
  435. {
  436. int i;
  437. for (i = 0; i < indio_dev->num_channels; i++) {
  438. if (indio_dev->channels[i].scan_index == chan)
  439. return i;
  440. }
  441. return -EINVAL;
  442. }
  443. static inline struct iio_chan_spec const *
  444. at91_adc_chan_get(struct iio_dev *indio_dev, int chan)
  445. {
  446. int index = at91_adc_chan_xlate(indio_dev, chan);
  447. if (index < 0)
  448. return NULL;
  449. return indio_dev->channels + index;
  450. }
  451. static inline int at91_adc_of_xlate(struct iio_dev *indio_dev,
  452. const struct of_phandle_args *iiospec)
  453. {
  454. return at91_adc_chan_xlate(indio_dev, iiospec->args[0]);
  455. }
  456. static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev)
  457. {
  458. u32 mask = 0;
  459. u8 bit;
  460. for_each_set_bit(bit, indio_dev->active_scan_mask,
  461. indio_dev->num_channels) {
  462. struct iio_chan_spec const *chan =
  463. at91_adc_chan_get(indio_dev, bit);
  464. mask |= BIT(chan->channel);
  465. }
  466. return mask & GENMASK(11, 0);
  467. }
  468. static void at91_adc_config_emr(struct at91_adc_state *st)
  469. {
  470. /* configure the extended mode register */
  471. unsigned int emr = at91_adc_readl(st, AT91_SAMA5D2_EMR);
  472. /* select oversampling per single trigger event */
  473. emr |= AT91_SAMA5D2_EMR_ASTE(1);
  474. /* delete leftover content if it's the case */
  475. emr &= ~AT91_SAMA5D2_EMR_OSR_MASK;
  476. /* select oversampling ratio from configuration */
  477. switch (st->oversampling_ratio) {
  478. case AT91_OSR_1SAMPLES:
  479. emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES) &
  480. AT91_SAMA5D2_EMR_OSR_MASK;
  481. break;
  482. case AT91_OSR_4SAMPLES:
  483. emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES) &
  484. AT91_SAMA5D2_EMR_OSR_MASK;
  485. break;
  486. case AT91_OSR_16SAMPLES:
  487. emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES) &
  488. AT91_SAMA5D2_EMR_OSR_MASK;
  489. break;
  490. }
  491. at91_adc_writel(st, AT91_SAMA5D2_EMR, emr);
  492. }
  493. static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val)
  494. {
  495. if (st->oversampling_ratio == AT91_OSR_1SAMPLES) {
  496. /*
  497. * in this case we only have 12 bits of real data, but channel
  498. * is registered as 14 bits, so shift left two bits
  499. */
  500. *val <<= 2;
  501. } else if (st->oversampling_ratio == AT91_OSR_4SAMPLES) {
  502. /*
  503. * in this case we have 13 bits of real data, but channel
  504. * is registered as 14 bits, so left shift one bit
  505. */
  506. *val <<= 1;
  507. }
  508. return IIO_VAL_INT;
  509. }
  510. static void at91_adc_adjust_val_osr_array(struct at91_adc_state *st, void *buf,
  511. int len)
  512. {
  513. int i = 0, val;
  514. u16 *buf_u16 = (u16 *) buf;
  515. /*
  516. * We are converting each two bytes (each sample).
  517. * First convert the byte based array to u16, and convert each sample
  518. * separately.
  519. * Each value is two bytes in an array of chars, so to not shift
  520. * more than we need, save the value separately.
  521. * len is in bytes, so divide by two to get number of samples.
  522. */
  523. while (i < len / 2) {
  524. val = buf_u16[i];
  525. at91_adc_adjust_val_osr(st, &val);
  526. buf_u16[i] = val;
  527. i++;
  528. }
  529. }
  530. static int at91_adc_configure_touch(struct at91_adc_state *st, bool state)
  531. {
  532. u32 clk_khz = st->current_sample_rate / 1000;
  533. int i = 0;
  534. u16 pendbc;
  535. u32 tsmr, acr;
  536. if (!state) {
  537. /* disabling touch IRQs and setting mode to no touch enabled */
  538. at91_adc_writel(st, AT91_SAMA5D2_IDR,
  539. AT91_SAMA5D2_IER_PEN | AT91_SAMA5D2_IER_NOPEN);
  540. at91_adc_writel(st, AT91_SAMA5D2_TSMR, 0);
  541. return 0;
  542. }
  543. /*
  544. * debounce time is in microseconds, we need it in milliseconds to
  545. * multiply with kilohertz, so, divide by 1000, but after the multiply.
  546. * round up to make sure pendbc is at least 1
  547. */
  548. pendbc = round_up(AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US *
  549. clk_khz / 1000, 1);
  550. /* get the required exponent */
  551. while (pendbc >> i++)
  552. ;
  553. pendbc = i;
  554. tsmr = AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS;
  555. tsmr |= AT91_SAMA5D2_TSMR_TSAV(2) & AT91_SAMA5D2_TSMR_TSAV_MASK;
  556. tsmr |= AT91_SAMA5D2_TSMR_PENDBC(pendbc) &
  557. AT91_SAMA5D2_TSMR_PENDBC_MASK;
  558. tsmr |= AT91_SAMA5D2_TSMR_NOTSDMA;
  559. tsmr |= AT91_SAMA5D2_TSMR_PENDET_ENA;
  560. tsmr |= AT91_SAMA5D2_TSMR_TSFREQ(2) & AT91_SAMA5D2_TSMR_TSFREQ_MASK;
  561. at91_adc_writel(st, AT91_SAMA5D2_TSMR, tsmr);
  562. acr = at91_adc_readl(st, AT91_SAMA5D2_ACR);
  563. acr &= ~AT91_SAMA5D2_ACR_PENDETSENS_MASK;
  564. acr |= 0x02 & AT91_SAMA5D2_ACR_PENDETSENS_MASK;
  565. at91_adc_writel(st, AT91_SAMA5D2_ACR, acr);
  566. /* Sample Period Time = (TRGPER + 1) / ADCClock */
  567. st->touch_st.sample_period_val =
  568. round_up((AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US *
  569. clk_khz / 1000) - 1, 1);
  570. /* enable pen detect IRQ */
  571. at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN);
  572. return 0;
  573. }
  574. static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg)
  575. {
  576. u32 val;
  577. u32 scale, result, pos;
  578. /*
  579. * to obtain the actual position we must divide by scale
  580. * and multiply with max, where
  581. * max = 2^AT91_SAMA5D2_MAX_POS_BITS - 1
  582. */
  583. /* first half of register is the x or y, second half is the scale */
  584. val = at91_adc_readl(st, reg);
  585. if (!val)
  586. dev_dbg(&st->indio_dev->dev, "pos is 0\n");
  587. pos = val & AT91_SAMA5D2_XYZ_MASK;
  588. result = (pos << AT91_SAMA5D2_MAX_POS_BITS) - pos;
  589. scale = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
  590. if (scale == 0) {
  591. dev_err(&st->indio_dev->dev, "scale is 0\n");
  592. return 0;
  593. }
  594. result /= scale;
  595. return result;
  596. }
  597. static u16 at91_adc_touch_x_pos(struct at91_adc_state *st)
  598. {
  599. st->touch_st.x_pos = at91_adc_touch_pos(st, AT91_SAMA5D2_XPOSR);
  600. return st->touch_st.x_pos;
  601. }
  602. static u16 at91_adc_touch_y_pos(struct at91_adc_state *st)
  603. {
  604. return at91_adc_touch_pos(st, AT91_SAMA5D2_YPOSR);
  605. }
  606. static u16 at91_adc_touch_pressure(struct at91_adc_state *st)
  607. {
  608. u32 val;
  609. u32 z1, z2;
  610. u32 pres;
  611. u32 rxp = 1;
  612. u32 factor = 1000;
  613. /* calculate the pressure */
  614. val = at91_adc_readl(st, AT91_SAMA5D2_PRESSR);
  615. z1 = val & AT91_SAMA5D2_XYZ_MASK;
  616. z2 = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
  617. if (z1 != 0)
  618. pres = rxp * (st->touch_st.x_pos * factor / 1024) *
  619. (z2 * factor / z1 - factor) /
  620. factor;
  621. else
  622. pres = 0xFFFF; /* no pen contact */
  623. /*
  624. * The pressure from device grows down, minimum is 0xFFFF, maximum 0x0.
  625. * We compute it this way, but let's return it in the expected way,
  626. * growing from 0 to 0xFFFF.
  627. */
  628. return 0xFFFF - pres;
  629. }
  630. static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val)
  631. {
  632. *val = 0;
  633. if (!st->touch_st.touching)
  634. return -ENODATA;
  635. if (chan == AT91_SAMA5D2_TOUCH_X_CHAN_IDX)
  636. *val = at91_adc_touch_x_pos(st);
  637. else if (chan == AT91_SAMA5D2_TOUCH_Y_CHAN_IDX)
  638. *val = at91_adc_touch_y_pos(st);
  639. else
  640. return -ENODATA;
  641. return IIO_VAL_INT;
  642. }
  643. static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val)
  644. {
  645. *val = 0;
  646. if (!st->touch_st.touching)
  647. return -ENODATA;
  648. if (chan == AT91_SAMA5D2_TOUCH_P_CHAN_IDX)
  649. *val = at91_adc_touch_pressure(st);
  650. else
  651. return -ENODATA;
  652. return IIO_VAL_INT;
  653. }
  654. static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
  655. {
  656. struct iio_dev *indio = iio_trigger_get_drvdata(trig);
  657. struct at91_adc_state *st = iio_priv(indio);
  658. u32 status = at91_adc_readl(st, AT91_SAMA5D2_TRGR);
  659. /* clear TRGMOD */
  660. status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK;
  661. if (state)
  662. status |= st->selected_trig->trgmod_value;
  663. /* set/unset hw trigger */
  664. at91_adc_writel(st, AT91_SAMA5D2_TRGR, status);
  665. return 0;
  666. }
  667. static int at91_adc_reenable_trigger(struct iio_trigger *trig)
  668. {
  669. struct iio_dev *indio = iio_trigger_get_drvdata(trig);
  670. struct at91_adc_state *st = iio_priv(indio);
  671. /* if we are using DMA, we must not reenable irq after each trigger */
  672. if (st->dma_st.dma_chan)
  673. return 0;
  674. enable_irq(st->irq);
  675. /* Needed to ACK the DRDY interruption */
  676. at91_adc_readl(st, AT91_SAMA5D2_LCDR);
  677. return 0;
  678. }
  679. static const struct iio_trigger_ops at91_adc_trigger_ops = {
  680. .set_trigger_state = &at91_adc_configure_trigger,
  681. .try_reenable = &at91_adc_reenable_trigger,
  682. .validate_device = iio_trigger_validate_own_device,
  683. };
  684. static int at91_adc_dma_size_done(struct at91_adc_state *st)
  685. {
  686. struct dma_tx_state state;
  687. enum dma_status status;
  688. int i, size;
  689. status = dmaengine_tx_status(st->dma_st.dma_chan,
  690. st->dma_st.dma_chan->cookie,
  691. &state);
  692. if (status != DMA_IN_PROGRESS)
  693. return 0;
  694. /* Transferred length is size in bytes from end of buffer */
  695. i = st->dma_st.rx_buf_sz - state.residue;
  696. /* Return available bytes */
  697. if (i >= st->dma_st.buf_idx)
  698. size = i - st->dma_st.buf_idx;
  699. else
  700. size = st->dma_st.rx_buf_sz + i - st->dma_st.buf_idx;
  701. return size;
  702. }
  703. static void at91_dma_buffer_done(void *data)
  704. {
  705. struct iio_dev *indio_dev = data;
  706. iio_trigger_poll_chained(indio_dev->trig);
  707. }
  708. static int at91_adc_dma_start(struct iio_dev *indio_dev)
  709. {
  710. struct at91_adc_state *st = iio_priv(indio_dev);
  711. struct dma_async_tx_descriptor *desc;
  712. dma_cookie_t cookie;
  713. int ret;
  714. u8 bit;
  715. if (!st->dma_st.dma_chan)
  716. return 0;
  717. /* we start a new DMA, so set buffer index to start */
  718. st->dma_st.buf_idx = 0;
  719. /*
  720. * compute buffer size w.r.t. watermark and enabled channels.
  721. * scan_bytes is aligned so we need an exact size for DMA
  722. */
  723. st->dma_st.rx_buf_sz = 0;
  724. for_each_set_bit(bit, indio_dev->active_scan_mask,
  725. indio_dev->num_channels) {
  726. struct iio_chan_spec const *chan =
  727. at91_adc_chan_get(indio_dev, bit);
  728. if (!chan)
  729. continue;
  730. st->dma_st.rx_buf_sz += chan->scan_type.storagebits / 8;
  731. }
  732. st->dma_st.rx_buf_sz *= st->dma_st.watermark;
  733. /* Prepare a DMA cyclic transaction */
  734. desc = dmaengine_prep_dma_cyclic(st->dma_st.dma_chan,
  735. st->dma_st.rx_dma_buf,
  736. st->dma_st.rx_buf_sz,
  737. st->dma_st.rx_buf_sz / 2,
  738. DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
  739. if (!desc) {
  740. dev_err(&indio_dev->dev, "cannot prepare DMA cyclic\n");
  741. return -EBUSY;
  742. }
  743. desc->callback = at91_dma_buffer_done;
  744. desc->callback_param = indio_dev;
  745. cookie = dmaengine_submit(desc);
  746. ret = dma_submit_error(cookie);
  747. if (ret) {
  748. dev_err(&indio_dev->dev, "cannot submit DMA cyclic\n");
  749. dmaengine_terminate_async(st->dma_st.dma_chan);
  750. return ret;
  751. }
  752. /* enable general overrun error signaling */
  753. at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_GOVRE);
  754. /* Issue pending DMA requests */
  755. dma_async_issue_pending(st->dma_st.dma_chan);
  756. /* consider current time as DMA start time for timestamps */
  757. st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
  758. dev_dbg(&indio_dev->dev, "DMA cyclic started\n");
  759. return 0;
  760. }
  761. static bool at91_adc_buffer_check_use_irq(struct iio_dev *indio,
  762. struct at91_adc_state *st)
  763. {
  764. /* if using DMA, we do not use our own IRQ (we use DMA-controller) */
  765. if (st->dma_st.dma_chan)
  766. return false;
  767. /* if the trigger is not ours, then it has its own IRQ */
  768. if (iio_trigger_validate_own_device(indio->trig, indio))
  769. return false;
  770. return true;
  771. }
  772. static bool at91_adc_current_chan_is_touch(struct iio_dev *indio_dev)
  773. {
  774. struct at91_adc_state *st = iio_priv(indio_dev);
  775. return !!bitmap_subset(indio_dev->active_scan_mask,
  776. &st->touch_st.channels_bitmask,
  777. AT91_SAMA5D2_MAX_CHAN_IDX + 1);
  778. }
  779. static int at91_adc_buffer_prepare(struct iio_dev *indio_dev)
  780. {
  781. int ret;
  782. u8 bit;
  783. struct at91_adc_state *st = iio_priv(indio_dev);
  784. /* check if we are enabling triggered buffer or the touchscreen */
  785. if (at91_adc_current_chan_is_touch(indio_dev))
  786. return at91_adc_configure_touch(st, true);
  787. /* if we are not in triggered mode, we cannot enable the buffer. */
  788. if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES))
  789. return -EINVAL;
  790. /* we continue with the triggered buffer */
  791. ret = at91_adc_dma_start(indio_dev);
  792. if (ret) {
  793. dev_err(&indio_dev->dev, "buffer prepare failed\n");
  794. return ret;
  795. }
  796. for_each_set_bit(bit, indio_dev->active_scan_mask,
  797. indio_dev->num_channels) {
  798. struct iio_chan_spec const *chan =
  799. at91_adc_chan_get(indio_dev, bit);
  800. u32 cor;
  801. if (!chan)
  802. continue;
  803. /* these channel types cannot be handled by this trigger */
  804. if (chan->type == IIO_POSITIONRELATIVE ||
  805. chan->type == IIO_PRESSURE)
  806. continue;
  807. cor = at91_adc_readl(st, AT91_SAMA5D2_COR);
  808. if (chan->differential)
  809. cor |= (BIT(chan->channel) | BIT(chan->channel2)) <<
  810. AT91_SAMA5D2_COR_DIFF_OFFSET;
  811. else
  812. cor &= ~(BIT(chan->channel) <<
  813. AT91_SAMA5D2_COR_DIFF_OFFSET);
  814. at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
  815. at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel));
  816. }
  817. if (at91_adc_buffer_check_use_irq(indio_dev, st))
  818. at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_DRDY);
  819. return 0;
  820. }
  821. static int at91_adc_buffer_postdisable(struct iio_dev *indio_dev)
  822. {
  823. struct at91_adc_state *st = iio_priv(indio_dev);
  824. u8 bit;
  825. /* check if we are disabling triggered buffer or the touchscreen */
  826. if (at91_adc_current_chan_is_touch(indio_dev))
  827. return at91_adc_configure_touch(st, false);
  828. /* if we are not in triggered mode, nothing to do here */
  829. if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES))
  830. return -EINVAL;
  831. /*
  832. * For each enable channel we must disable it in hardware.
  833. * In the case of DMA, we must read the last converted value
  834. * to clear EOC status and not get a possible interrupt later.
  835. * This value is being read by DMA from LCDR anyway, so it's not lost.
  836. */
  837. for_each_set_bit(bit, indio_dev->active_scan_mask,
  838. indio_dev->num_channels) {
  839. struct iio_chan_spec const *chan =
  840. at91_adc_chan_get(indio_dev, bit);
  841. if (!chan)
  842. continue;
  843. /* these channel types are virtual, no need to do anything */
  844. if (chan->type == IIO_POSITIONRELATIVE ||
  845. chan->type == IIO_PRESSURE)
  846. continue;
  847. at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel));
  848. if (st->dma_st.dma_chan)
  849. at91_adc_readl(st, chan->address);
  850. }
  851. if (at91_adc_buffer_check_use_irq(indio_dev, st))
  852. at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_DRDY);
  853. /* read overflow register to clear possible overflow status */
  854. at91_adc_readl(st, AT91_SAMA5D2_OVER);
  855. /* if we are using DMA we must clear registers and end DMA */
  856. if (st->dma_st.dma_chan)
  857. dmaengine_terminate_sync(st->dma_st.dma_chan);
  858. return 0;
  859. }
  860. static const struct iio_buffer_setup_ops at91_buffer_setup_ops = {
  861. .postdisable = &at91_adc_buffer_postdisable,
  862. };
  863. static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio,
  864. char *trigger_name)
  865. {
  866. struct iio_trigger *trig;
  867. int ret;
  868. trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name,
  869. indio->id, trigger_name);
  870. if (!trig)
  871. return NULL;
  872. trig->dev.parent = indio->dev.parent;
  873. iio_trigger_set_drvdata(trig, indio);
  874. trig->ops = &at91_adc_trigger_ops;
  875. ret = devm_iio_trigger_register(&indio->dev, trig);
  876. if (ret)
  877. return ERR_PTR(ret);
  878. return trig;
  879. }
  880. static int at91_adc_trigger_init(struct iio_dev *indio)
  881. {
  882. struct at91_adc_state *st = iio_priv(indio);
  883. st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name);
  884. if (IS_ERR(st->trig)) {
  885. dev_err(&indio->dev,
  886. "could not allocate trigger\n");
  887. return PTR_ERR(st->trig);
  888. }
  889. return 0;
  890. }
  891. static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev,
  892. struct iio_poll_func *pf)
  893. {
  894. struct at91_adc_state *st = iio_priv(indio_dev);
  895. int i = 0;
  896. int val;
  897. u8 bit;
  898. u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev);
  899. unsigned int timeout = 50;
  900. /*
  901. * Check if the conversion is ready. If not, wait a little bit, and
  902. * in case of timeout exit with an error.
  903. */
  904. while ((at91_adc_readl(st, AT91_SAMA5D2_ISR) & mask) != mask &&
  905. timeout) {
  906. usleep_range(50, 100);
  907. timeout--;
  908. }
  909. /* Cannot read data, not ready. Continue without reporting data */
  910. if (!timeout)
  911. return;
  912. for_each_set_bit(bit, indio_dev->active_scan_mask,
  913. indio_dev->num_channels) {
  914. struct iio_chan_spec const *chan =
  915. at91_adc_chan_get(indio_dev, bit);
  916. if (!chan)
  917. continue;
  918. /*
  919. * Our external trigger only supports the voltage channels.
  920. * In case someone requested a different type of channel
  921. * just put zeroes to buffer.
  922. * This should not happen because we check the scan mode
  923. * and scan mask when we enable the buffer, and we don't allow
  924. * the buffer to start with a mixed mask (voltage and something
  925. * else).
  926. * Thus, emit a warning.
  927. */
  928. if (chan->type == IIO_VOLTAGE) {
  929. val = at91_adc_readl(st, chan->address);
  930. at91_adc_adjust_val_osr(st, &val);
  931. st->buffer[i] = val;
  932. } else {
  933. st->buffer[i] = 0;
  934. WARN(true, "This trigger cannot handle this type of channel");
  935. }
  936. i++;
  937. }
  938. iio_push_to_buffers_with_timestamp(indio_dev, st->buffer,
  939. pf->timestamp);
  940. }
  941. static void at91_adc_trigger_handler_dma(struct iio_dev *indio_dev)
  942. {
  943. struct at91_adc_state *st = iio_priv(indio_dev);
  944. int transferred_len = at91_adc_dma_size_done(st);
  945. s64 ns = iio_get_time_ns(indio_dev);
  946. s64 interval;
  947. int sample_index = 0, sample_count, sample_size;
  948. u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
  949. /* if we reached this point, we cannot sample faster */
  950. if (status & AT91_SAMA5D2_IER_GOVRE)
  951. pr_info_ratelimited("%s: conversion overrun detected\n",
  952. indio_dev->name);
  953. sample_size = div_s64(st->dma_st.rx_buf_sz, st->dma_st.watermark);
  954. sample_count = div_s64(transferred_len, sample_size);
  955. /*
  956. * interval between samples is total time since last transfer handling
  957. * divided by the number of samples (total size divided by sample size)
  958. */
  959. interval = div_s64((ns - st->dma_st.dma_ts), sample_count);
  960. while (transferred_len >= sample_size) {
  961. /*
  962. * for all the values in the current sample,
  963. * adjust the values inside the buffer for oversampling
  964. */
  965. at91_adc_adjust_val_osr_array(st,
  966. &st->dma_st.rx_buf[st->dma_st.buf_idx],
  967. sample_size);
  968. iio_push_to_buffers_with_timestamp(indio_dev,
  969. (st->dma_st.rx_buf + st->dma_st.buf_idx),
  970. (st->dma_st.dma_ts + interval * sample_index));
  971. /* adjust remaining length */
  972. transferred_len -= sample_size;
  973. /* adjust buffer index */
  974. st->dma_st.buf_idx += sample_size;
  975. /* in case of reaching end of buffer, reset index */
  976. if (st->dma_st.buf_idx >= st->dma_st.rx_buf_sz)
  977. st->dma_st.buf_idx = 0;
  978. sample_index++;
  979. }
  980. /* adjust saved time for next transfer handling */
  981. st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
  982. }
  983. static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
  984. {
  985. struct iio_poll_func *pf = p;
  986. struct iio_dev *indio_dev = pf->indio_dev;
  987. struct at91_adc_state *st = iio_priv(indio_dev);
  988. /*
  989. * If it's not our trigger, start a conversion now, as we are
  990. * actually polling the trigger now.
  991. */
  992. if (iio_trigger_validate_own_device(indio_dev->trig, indio_dev))
  993. at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START);
  994. if (st->dma_st.dma_chan)
  995. at91_adc_trigger_handler_dma(indio_dev);
  996. else
  997. at91_adc_trigger_handler_nodma(indio_dev, pf);
  998. iio_trigger_notify_done(indio_dev->trig);
  999. return IRQ_HANDLED;
  1000. }
  1001. static int at91_adc_buffer_init(struct iio_dev *indio)
  1002. {
  1003. return devm_iio_triggered_buffer_setup(&indio->dev, indio,
  1004. &iio_pollfunc_store_time,
  1005. &at91_adc_trigger_handler, &at91_buffer_setup_ops);
  1006. }
  1007. static unsigned at91_adc_startup_time(unsigned startup_time_min,
  1008. unsigned adc_clk_khz)
  1009. {
  1010. static const unsigned int startup_lookup[] = {
  1011. 0, 8, 16, 24,
  1012. 64, 80, 96, 112,
  1013. 512, 576, 640, 704,
  1014. 768, 832, 896, 960
  1015. };
  1016. unsigned ticks_min, i;
  1017. /*
  1018. * Since the adc frequency is checked before, there is no reason
  1019. * to not meet the startup time constraint.
  1020. */
  1021. ticks_min = startup_time_min * adc_clk_khz / 1000;
  1022. for (i = 0; i < ARRAY_SIZE(startup_lookup); i++)
  1023. if (startup_lookup[i] > ticks_min)
  1024. break;
  1025. return i;
  1026. }
  1027. static void at91_adc_setup_samp_freq(struct iio_dev *indio_dev, unsigned freq)
  1028. {
  1029. struct at91_adc_state *st = iio_priv(indio_dev);
  1030. unsigned f_per, prescal, startup, mr;
  1031. f_per = clk_get_rate(st->per_clk);
  1032. prescal = (f_per / (2 * freq)) - 1;
  1033. startup = at91_adc_startup_time(st->soc_info.startup_time,
  1034. freq / 1000);
  1035. mr = at91_adc_readl(st, AT91_SAMA5D2_MR);
  1036. mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK);
  1037. mr |= AT91_SAMA5D2_MR_STARTUP(startup);
  1038. mr |= AT91_SAMA5D2_MR_PRESCAL(prescal);
  1039. at91_adc_writel(st, AT91_SAMA5D2_MR, mr);
  1040. dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n",
  1041. freq, startup, prescal);
  1042. st->current_sample_rate = freq;
  1043. }
  1044. static inline unsigned at91_adc_get_sample_freq(struct at91_adc_state *st)
  1045. {
  1046. return st->current_sample_rate;
  1047. }
  1048. static void at91_adc_touch_data_handler(struct iio_dev *indio_dev)
  1049. {
  1050. struct at91_adc_state *st = iio_priv(indio_dev);
  1051. u8 bit;
  1052. u16 val;
  1053. int i = 0;
  1054. for_each_set_bit(bit, indio_dev->active_scan_mask,
  1055. AT91_SAMA5D2_MAX_CHAN_IDX + 1) {
  1056. struct iio_chan_spec const *chan =
  1057. at91_adc_chan_get(indio_dev, bit);
  1058. if (chan->type == IIO_POSITIONRELATIVE)
  1059. at91_adc_read_position(st, chan->channel, &val);
  1060. else if (chan->type == IIO_PRESSURE)
  1061. at91_adc_read_pressure(st, chan->channel, &val);
  1062. else
  1063. continue;
  1064. st->buffer[i] = val;
  1065. i++;
  1066. }
  1067. /*
  1068. * Schedule work to push to buffers.
  1069. * This is intended to push to the callback buffer that another driver
  1070. * registered. We are still in a handler from our IRQ. If we push
  1071. * directly, it means the other driver has it's callback called
  1072. * from our IRQ context. Which is something we better avoid.
  1073. * Let's schedule it after our IRQ is completed.
  1074. */
  1075. schedule_work(&st->touch_st.workq);
  1076. }
  1077. static void at91_adc_pen_detect_interrupt(struct at91_adc_state *st)
  1078. {
  1079. at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_PEN);
  1080. at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_NOPEN |
  1081. AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
  1082. AT91_SAMA5D2_IER_PRDY);
  1083. at91_adc_writel(st, AT91_SAMA5D2_TRGR,
  1084. AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC |
  1085. AT91_SAMA5D2_TRGR_TRGPER(st->touch_st.sample_period_val));
  1086. st->touch_st.touching = true;
  1087. }
  1088. static void at91_adc_no_pen_detect_interrupt(struct iio_dev *indio_dev)
  1089. {
  1090. struct at91_adc_state *st = iio_priv(indio_dev);
  1091. at91_adc_writel(st, AT91_SAMA5D2_TRGR,
  1092. AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER);
  1093. at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_NOPEN |
  1094. AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
  1095. AT91_SAMA5D2_IER_PRDY);
  1096. st->touch_st.touching = false;
  1097. at91_adc_touch_data_handler(indio_dev);
  1098. at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN);
  1099. }
  1100. static void at91_adc_workq_handler(struct work_struct *workq)
  1101. {
  1102. struct at91_adc_touch *touch_st = container_of(workq,
  1103. struct at91_adc_touch, workq);
  1104. struct at91_adc_state *st = container_of(touch_st,
  1105. struct at91_adc_state, touch_st);
  1106. struct iio_dev *indio_dev = st->indio_dev;
  1107. iio_push_to_buffers(indio_dev, st->buffer);
  1108. }
  1109. static irqreturn_t at91_adc_interrupt(int irq, void *private)
  1110. {
  1111. struct iio_dev *indio = private;
  1112. struct at91_adc_state *st = iio_priv(indio);
  1113. u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
  1114. u32 imr = at91_adc_readl(st, AT91_SAMA5D2_IMR);
  1115. u32 rdy_mask = AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
  1116. AT91_SAMA5D2_IER_PRDY;
  1117. if (!(status & imr))
  1118. return IRQ_NONE;
  1119. if (status & AT91_SAMA5D2_IER_PEN) {
  1120. /* pen detected IRQ */
  1121. at91_adc_pen_detect_interrupt(st);
  1122. } else if ((status & AT91_SAMA5D2_IER_NOPEN)) {
  1123. /* nopen detected IRQ */
  1124. at91_adc_no_pen_detect_interrupt(indio);
  1125. } else if ((status & AT91_SAMA5D2_ISR_PENS) &&
  1126. ((status & rdy_mask) == rdy_mask)) {
  1127. /* periodic trigger IRQ - during pen sense */
  1128. at91_adc_touch_data_handler(indio);
  1129. } else if (status & AT91_SAMA5D2_ISR_PENS) {
  1130. /*
  1131. * touching, but the measurements are not ready yet.
  1132. * read and ignore.
  1133. */
  1134. status = at91_adc_readl(st, AT91_SAMA5D2_XPOSR);
  1135. status = at91_adc_readl(st, AT91_SAMA5D2_YPOSR);
  1136. status = at91_adc_readl(st, AT91_SAMA5D2_PRESSR);
  1137. } else if (iio_buffer_enabled(indio) &&
  1138. (status & AT91_SAMA5D2_IER_DRDY)) {
  1139. /* triggered buffer without DMA */
  1140. disable_irq_nosync(irq);
  1141. iio_trigger_poll(indio->trig);
  1142. } else if (iio_buffer_enabled(indio) && st->dma_st.dma_chan) {
  1143. /* triggered buffer with DMA - should not happen */
  1144. disable_irq_nosync(irq);
  1145. WARN(true, "Unexpected irq occurred\n");
  1146. } else if (!iio_buffer_enabled(indio)) {
  1147. /* software requested conversion */
  1148. st->conversion_value = at91_adc_readl(st, st->chan->address);
  1149. st->conversion_done = true;
  1150. wake_up_interruptible(&st->wq_data_available);
  1151. }
  1152. return IRQ_HANDLED;
  1153. }
  1154. static int at91_adc_read_info_raw(struct iio_dev *indio_dev,
  1155. struct iio_chan_spec const *chan, int *val)
  1156. {
  1157. struct at91_adc_state *st = iio_priv(indio_dev);
  1158. u32 cor = 0;
  1159. u16 tmp_val;
  1160. int ret;
  1161. /*
  1162. * Keep in mind that we cannot use software trigger or touchscreen
  1163. * if external trigger is enabled
  1164. */
  1165. if (chan->type == IIO_POSITIONRELATIVE) {
  1166. ret = iio_device_claim_direct_mode(indio_dev);
  1167. if (ret)
  1168. return ret;
  1169. mutex_lock(&st->lock);
  1170. ret = at91_adc_read_position(st, chan->channel,
  1171. &tmp_val);
  1172. *val = tmp_val;
  1173. mutex_unlock(&st->lock);
  1174. iio_device_release_direct_mode(indio_dev);
  1175. return at91_adc_adjust_val_osr(st, val);
  1176. }
  1177. if (chan->type == IIO_PRESSURE) {
  1178. ret = iio_device_claim_direct_mode(indio_dev);
  1179. if (ret)
  1180. return ret;
  1181. mutex_lock(&st->lock);
  1182. ret = at91_adc_read_pressure(st, chan->channel,
  1183. &tmp_val);
  1184. *val = tmp_val;
  1185. mutex_unlock(&st->lock);
  1186. iio_device_release_direct_mode(indio_dev);
  1187. return at91_adc_adjust_val_osr(st, val);
  1188. }
  1189. /* in this case we have a voltage channel */
  1190. ret = iio_device_claim_direct_mode(indio_dev);
  1191. if (ret)
  1192. return ret;
  1193. mutex_lock(&st->lock);
  1194. st->chan = chan;
  1195. if (chan->differential)
  1196. cor = (BIT(chan->channel) | BIT(chan->channel2)) <<
  1197. AT91_SAMA5D2_COR_DIFF_OFFSET;
  1198. at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
  1199. at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel));
  1200. at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel));
  1201. at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START);
  1202. ret = wait_event_interruptible_timeout(st->wq_data_available,
  1203. st->conversion_done,
  1204. msecs_to_jiffies(1000));
  1205. if (ret == 0)
  1206. ret = -ETIMEDOUT;
  1207. if (ret > 0) {
  1208. *val = st->conversion_value;
  1209. ret = at91_adc_adjust_val_osr(st, val);
  1210. if (chan->scan_type.sign == 's')
  1211. *val = sign_extend32(*val,
  1212. chan->scan_type.realbits - 1);
  1213. st->conversion_done = false;
  1214. }
  1215. at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel));
  1216. at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel));
  1217. /* Needed to ACK the DRDY interruption */
  1218. at91_adc_readl(st, AT91_SAMA5D2_LCDR);
  1219. mutex_unlock(&st->lock);
  1220. iio_device_release_direct_mode(indio_dev);
  1221. return ret;
  1222. }
  1223. static int at91_adc_read_raw(struct iio_dev *indio_dev,
  1224. struct iio_chan_spec const *chan,
  1225. int *val, int *val2, long mask)
  1226. {
  1227. struct at91_adc_state *st = iio_priv(indio_dev);
  1228. switch (mask) {
  1229. case IIO_CHAN_INFO_RAW:
  1230. return at91_adc_read_info_raw(indio_dev, chan, val);
  1231. case IIO_CHAN_INFO_SCALE:
  1232. *val = st->vref_uv / 1000;
  1233. if (chan->differential)
  1234. *val *= 2;
  1235. *val2 = chan->scan_type.realbits;
  1236. return IIO_VAL_FRACTIONAL_LOG2;
  1237. case IIO_CHAN_INFO_SAMP_FREQ:
  1238. *val = at91_adc_get_sample_freq(st);
  1239. return IIO_VAL_INT;
  1240. case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
  1241. *val = st->oversampling_ratio;
  1242. return IIO_VAL_INT;
  1243. default:
  1244. return -EINVAL;
  1245. }
  1246. }
  1247. static int at91_adc_write_raw(struct iio_dev *indio_dev,
  1248. struct iio_chan_spec const *chan,
  1249. int val, int val2, long mask)
  1250. {
  1251. struct at91_adc_state *st = iio_priv(indio_dev);
  1252. switch (mask) {
  1253. case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
  1254. if ((val != AT91_OSR_1SAMPLES) && (val != AT91_OSR_4SAMPLES) &&
  1255. (val != AT91_OSR_16SAMPLES))
  1256. return -EINVAL;
  1257. /* if no change, optimize out */
  1258. if (val == st->oversampling_ratio)
  1259. return 0;
  1260. st->oversampling_ratio = val;
  1261. /* update ratio */
  1262. at91_adc_config_emr(st);
  1263. return 0;
  1264. case IIO_CHAN_INFO_SAMP_FREQ:
  1265. if (val < st->soc_info.min_sample_rate ||
  1266. val > st->soc_info.max_sample_rate)
  1267. return -EINVAL;
  1268. at91_adc_setup_samp_freq(indio_dev, val);
  1269. return 0;
  1270. default:
  1271. return -EINVAL;
  1272. };
  1273. }
  1274. static void at91_adc_dma_init(struct platform_device *pdev)
  1275. {
  1276. struct iio_dev *indio_dev = platform_get_drvdata(pdev);
  1277. struct at91_adc_state *st = iio_priv(indio_dev);
  1278. struct dma_slave_config config = {0};
  1279. /*
  1280. * We make the buffer double the size of the fifo,
  1281. * such that DMA uses one half of the buffer (full fifo size)
  1282. * and the software uses the other half to read/write.
  1283. */
  1284. unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
  1285. AT91_BUFFER_MAX_CONVERSION_BYTES * 2,
  1286. PAGE_SIZE);
  1287. if (st->dma_st.dma_chan)
  1288. return;
  1289. st->dma_st.dma_chan = dma_request_chan(&pdev->dev, "rx");
  1290. if (IS_ERR(st->dma_st.dma_chan)) {
  1291. dev_info(&pdev->dev, "can't get DMA channel\n");
  1292. st->dma_st.dma_chan = NULL;
  1293. goto dma_exit;
  1294. }
  1295. st->dma_st.rx_buf = dma_alloc_coherent(st->dma_st.dma_chan->device->dev,
  1296. pages * PAGE_SIZE,
  1297. &st->dma_st.rx_dma_buf,
  1298. GFP_KERNEL);
  1299. if (!st->dma_st.rx_buf) {
  1300. dev_info(&pdev->dev, "can't allocate coherent DMA area\n");
  1301. goto dma_chan_disable;
  1302. }
  1303. /* Configure DMA channel to read data register */
  1304. config.direction = DMA_DEV_TO_MEM;
  1305. config.src_addr = (phys_addr_t)(st->dma_st.phys_addr
  1306. + AT91_SAMA5D2_LCDR);
  1307. config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  1308. config.src_maxburst = 1;
  1309. config.dst_maxburst = 1;
  1310. if (dmaengine_slave_config(st->dma_st.dma_chan, &config)) {
  1311. dev_info(&pdev->dev, "can't configure DMA slave\n");
  1312. goto dma_free_area;
  1313. }
  1314. dev_info(&pdev->dev, "using %s for rx DMA transfers\n",
  1315. dma_chan_name(st->dma_st.dma_chan));
  1316. return;
  1317. dma_free_area:
  1318. dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
  1319. st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
  1320. dma_chan_disable:
  1321. dma_release_channel(st->dma_st.dma_chan);
  1322. st->dma_st.dma_chan = NULL;
  1323. dma_exit:
  1324. dev_info(&pdev->dev, "continuing without DMA support\n");
  1325. }
  1326. static void at91_adc_dma_disable(struct platform_device *pdev)
  1327. {
  1328. struct iio_dev *indio_dev = platform_get_drvdata(pdev);
  1329. struct at91_adc_state *st = iio_priv(indio_dev);
  1330. unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
  1331. AT91_BUFFER_MAX_CONVERSION_BYTES * 2,
  1332. PAGE_SIZE);
  1333. /* if we are not using DMA, just return */
  1334. if (!st->dma_st.dma_chan)
  1335. return;
  1336. /* wait for all transactions to be terminated first*/
  1337. dmaengine_terminate_sync(st->dma_st.dma_chan);
  1338. dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
  1339. st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
  1340. dma_release_channel(st->dma_st.dma_chan);
  1341. st->dma_st.dma_chan = NULL;
  1342. dev_info(&pdev->dev, "continuing without DMA support\n");
  1343. }
  1344. static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
  1345. {
  1346. struct at91_adc_state *st = iio_priv(indio_dev);
  1347. int ret;
  1348. if (val > AT91_HWFIFO_MAX_SIZE)
  1349. return -EINVAL;
  1350. if (!st->selected_trig->hw_trig) {
  1351. dev_dbg(&indio_dev->dev, "we need hw trigger for DMA\n");
  1352. return 0;
  1353. }
  1354. dev_dbg(&indio_dev->dev, "new watermark is %u\n", val);
  1355. st->dma_st.watermark = val;
  1356. /*
  1357. * The logic here is: if we have watermark 1, it means we do
  1358. * each conversion with it's own IRQ, thus we don't need DMA.
  1359. * If the watermark is higher, we do DMA to do all the transfers in bulk
  1360. */
  1361. if (val == 1)
  1362. at91_adc_dma_disable(to_platform_device(&indio_dev->dev));
  1363. else if (val > 1)
  1364. at91_adc_dma_init(to_platform_device(&indio_dev->dev));
  1365. /*
  1366. * We can start the DMA only after setting the watermark and
  1367. * having the DMA initialization completed
  1368. */
  1369. ret = at91_adc_buffer_prepare(indio_dev);
  1370. if (ret)
  1371. at91_adc_dma_disable(to_platform_device(&indio_dev->dev));
  1372. return ret;
  1373. }
  1374. static int at91_adc_update_scan_mode(struct iio_dev *indio_dev,
  1375. const unsigned long *scan_mask)
  1376. {
  1377. struct at91_adc_state *st = iio_priv(indio_dev);
  1378. if (bitmap_subset(scan_mask, &st->touch_st.channels_bitmask,
  1379. AT91_SAMA5D2_MAX_CHAN_IDX + 1))
  1380. return 0;
  1381. /*
  1382. * if the new bitmap is a combination of touchscreen and regular
  1383. * channels, then we are not fine
  1384. */
  1385. if (bitmap_intersects(&st->touch_st.channels_bitmask, scan_mask,
  1386. AT91_SAMA5D2_MAX_CHAN_IDX + 1))
  1387. return -EINVAL;
  1388. return 0;
  1389. }
  1390. static void at91_adc_hw_init(struct iio_dev *indio_dev)
  1391. {
  1392. struct at91_adc_state *st = iio_priv(indio_dev);
  1393. at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
  1394. at91_adc_writel(st, AT91_SAMA5D2_IDR, 0xffffffff);
  1395. /*
  1396. * Transfer field must be set to 2 according to the datasheet and
  1397. * allows different analog settings for each channel.
  1398. */
  1399. at91_adc_writel(st, AT91_SAMA5D2_MR,
  1400. AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH);
  1401. at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate);
  1402. /* configure extended mode register */
  1403. at91_adc_config_emr(st);
  1404. }
  1405. static ssize_t at91_adc_get_fifo_state(struct device *dev,
  1406. struct device_attribute *attr, char *buf)
  1407. {
  1408. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  1409. struct at91_adc_state *st = iio_priv(indio_dev);
  1410. return scnprintf(buf, PAGE_SIZE, "%d\n", !!st->dma_st.dma_chan);
  1411. }
  1412. static ssize_t at91_adc_get_watermark(struct device *dev,
  1413. struct device_attribute *attr, char *buf)
  1414. {
  1415. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  1416. struct at91_adc_state *st = iio_priv(indio_dev);
  1417. return scnprintf(buf, PAGE_SIZE, "%d\n", st->dma_st.watermark);
  1418. }
  1419. static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
  1420. at91_adc_get_fifo_state, NULL, 0);
  1421. static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
  1422. at91_adc_get_watermark, NULL, 0);
  1423. static IIO_CONST_ATTR(hwfifo_watermark_min, "2");
  1424. static IIO_CONST_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR);
  1425. static IIO_CONST_ATTR(oversampling_ratio_available,
  1426. __stringify(AT91_OSR_1SAMPLES) " "
  1427. __stringify(AT91_OSR_4SAMPLES) " "
  1428. __stringify(AT91_OSR_16SAMPLES));
  1429. static struct attribute *at91_adc_attributes[] = {
  1430. &iio_const_attr_oversampling_ratio_available.dev_attr.attr,
  1431. NULL,
  1432. };
  1433. static const struct attribute_group at91_adc_attribute_group = {
  1434. .attrs = at91_adc_attributes,
  1435. };
  1436. static const struct attribute *at91_adc_fifo_attributes[] = {
  1437. &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
  1438. &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
  1439. &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
  1440. &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
  1441. NULL,
  1442. };
  1443. static const struct iio_info at91_adc_info = {
  1444. .attrs = &at91_adc_attribute_group,
  1445. .read_raw = &at91_adc_read_raw,
  1446. .write_raw = &at91_adc_write_raw,
  1447. .update_scan_mode = &at91_adc_update_scan_mode,
  1448. .of_xlate = &at91_adc_of_xlate,
  1449. .hwfifo_set_watermark = &at91_adc_set_watermark,
  1450. };
  1451. static int at91_adc_probe(struct platform_device *pdev)
  1452. {
  1453. struct iio_dev *indio_dev;
  1454. struct at91_adc_state *st;
  1455. struct resource *res;
  1456. int ret, i;
  1457. u32 edge_type = IRQ_TYPE_NONE;
  1458. indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
  1459. if (!indio_dev)
  1460. return -ENOMEM;
  1461. indio_dev->name = dev_name(&pdev->dev);
  1462. indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
  1463. indio_dev->info = &at91_adc_info;
  1464. indio_dev->channels = at91_adc_channels;
  1465. indio_dev->num_channels = ARRAY_SIZE(at91_adc_channels);
  1466. st = iio_priv(indio_dev);
  1467. st->indio_dev = indio_dev;
  1468. bitmap_set(&st->touch_st.channels_bitmask,
  1469. AT91_SAMA5D2_TOUCH_X_CHAN_IDX, 1);
  1470. bitmap_set(&st->touch_st.channels_bitmask,
  1471. AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, 1);
  1472. bitmap_set(&st->touch_st.channels_bitmask,
  1473. AT91_SAMA5D2_TOUCH_P_CHAN_IDX, 1);
  1474. st->oversampling_ratio = AT91_OSR_1SAMPLES;
  1475. ret = of_property_read_u32(pdev->dev.of_node,
  1476. "atmel,min-sample-rate-hz",
  1477. &st->soc_info.min_sample_rate);
  1478. if (ret) {
  1479. dev_err(&pdev->dev,
  1480. "invalid or missing value for atmel,min-sample-rate-hz\n");
  1481. return ret;
  1482. }
  1483. ret = of_property_read_u32(pdev->dev.of_node,
  1484. "atmel,max-sample-rate-hz",
  1485. &st->soc_info.max_sample_rate);
  1486. if (ret) {
  1487. dev_err(&pdev->dev,
  1488. "invalid or missing value for atmel,max-sample-rate-hz\n");
  1489. return ret;
  1490. }
  1491. ret = of_property_read_u32(pdev->dev.of_node, "atmel,startup-time-ms",
  1492. &st->soc_info.startup_time);
  1493. if (ret) {
  1494. dev_err(&pdev->dev,
  1495. "invalid or missing value for atmel,startup-time-ms\n");
  1496. return ret;
  1497. }
  1498. ret = of_property_read_u32(pdev->dev.of_node,
  1499. "atmel,trigger-edge-type", &edge_type);
  1500. if (ret) {
  1501. dev_dbg(&pdev->dev,
  1502. "atmel,trigger-edge-type not specified, only software trigger available\n");
  1503. }
  1504. st->selected_trig = NULL;
  1505. /* find the right trigger, or no trigger at all */
  1506. for (i = 0; i < AT91_SAMA5D2_HW_TRIG_CNT + 1; i++)
  1507. if (at91_adc_trigger_list[i].edge_type == edge_type) {
  1508. st->selected_trig = &at91_adc_trigger_list[i];
  1509. break;
  1510. }
  1511. if (!st->selected_trig) {
  1512. dev_err(&pdev->dev, "invalid external trigger edge value\n");
  1513. return -EINVAL;
  1514. }
  1515. init_waitqueue_head(&st->wq_data_available);
  1516. mutex_init(&st->lock);
  1517. INIT_WORK(&st->touch_st.workq, at91_adc_workq_handler);
  1518. st->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
  1519. if (IS_ERR(st->base))
  1520. return PTR_ERR(st->base);
  1521. /* if we plan to use DMA, we need the physical address of the regs */
  1522. st->dma_st.phys_addr = res->start;
  1523. st->irq = platform_get_irq(pdev, 0);
  1524. if (st->irq <= 0) {
  1525. if (!st->irq)
  1526. st->irq = -ENXIO;
  1527. return st->irq;
  1528. }
  1529. st->per_clk = devm_clk_get(&pdev->dev, "adc_clk");
  1530. if (IS_ERR(st->per_clk))
  1531. return PTR_ERR(st->per_clk);
  1532. st->reg = devm_regulator_get(&pdev->dev, "vddana");
  1533. if (IS_ERR(st->reg))
  1534. return PTR_ERR(st->reg);
  1535. st->vref = devm_regulator_get(&pdev->dev, "vref");
  1536. if (IS_ERR(st->vref))
  1537. return PTR_ERR(st->vref);
  1538. ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0,
  1539. pdev->dev.driver->name, indio_dev);
  1540. if (ret)
  1541. return ret;
  1542. ret = regulator_enable(st->reg);
  1543. if (ret)
  1544. return ret;
  1545. ret = regulator_enable(st->vref);
  1546. if (ret)
  1547. goto reg_disable;
  1548. st->vref_uv = regulator_get_voltage(st->vref);
  1549. if (st->vref_uv <= 0) {
  1550. ret = -EINVAL;
  1551. goto vref_disable;
  1552. }
  1553. at91_adc_hw_init(indio_dev);
  1554. ret = clk_prepare_enable(st->per_clk);
  1555. if (ret)
  1556. goto vref_disable;
  1557. platform_set_drvdata(pdev, indio_dev);
  1558. ret = at91_adc_buffer_init(indio_dev);
  1559. if (ret < 0) {
  1560. dev_err(&pdev->dev, "couldn't initialize the buffer.\n");
  1561. goto per_clk_disable_unprepare;
  1562. }
  1563. if (st->selected_trig->hw_trig) {
  1564. ret = at91_adc_trigger_init(indio_dev);
  1565. if (ret < 0) {
  1566. dev_err(&pdev->dev, "couldn't setup the triggers.\n");
  1567. goto per_clk_disable_unprepare;
  1568. }
  1569. /*
  1570. * Initially the iio buffer has a length of 2 and
  1571. * a watermark of 1
  1572. */
  1573. st->dma_st.watermark = 1;
  1574. iio_buffer_set_attrs(indio_dev->buffer,
  1575. at91_adc_fifo_attributes);
  1576. }
  1577. if (dma_coerce_mask_and_coherent(&indio_dev->dev, DMA_BIT_MASK(32)))
  1578. dev_info(&pdev->dev, "cannot set DMA mask to 32-bit\n");
  1579. ret = iio_device_register(indio_dev);
  1580. if (ret < 0)
  1581. goto dma_disable;
  1582. if (st->selected_trig->hw_trig)
  1583. dev_info(&pdev->dev, "setting up trigger as %s\n",
  1584. st->selected_trig->name);
  1585. dev_info(&pdev->dev, "version: %x\n",
  1586. readl_relaxed(st->base + AT91_SAMA5D2_VERSION));
  1587. return 0;
  1588. dma_disable:
  1589. at91_adc_dma_disable(pdev);
  1590. per_clk_disable_unprepare:
  1591. clk_disable_unprepare(st->per_clk);
  1592. vref_disable:
  1593. regulator_disable(st->vref);
  1594. reg_disable:
  1595. regulator_disable(st->reg);
  1596. return ret;
  1597. }
  1598. static int at91_adc_remove(struct platform_device *pdev)
  1599. {
  1600. struct iio_dev *indio_dev = platform_get_drvdata(pdev);
  1601. struct at91_adc_state *st = iio_priv(indio_dev);
  1602. iio_device_unregister(indio_dev);
  1603. at91_adc_dma_disable(pdev);
  1604. clk_disable_unprepare(st->per_clk);
  1605. regulator_disable(st->vref);
  1606. regulator_disable(st->reg);
  1607. return 0;
  1608. }
  1609. static __maybe_unused int at91_adc_suspend(struct device *dev)
  1610. {
  1611. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  1612. struct at91_adc_state *st = iio_priv(indio_dev);
  1613. /*
  1614. * Do a sofware reset of the ADC before we go to suspend.
  1615. * this will ensure that all pins are free from being muxed by the ADC
  1616. * and can be used by for other devices.
  1617. * Otherwise, ADC will hog them and we can't go to suspend mode.
  1618. */
  1619. at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
  1620. clk_disable_unprepare(st->per_clk);
  1621. regulator_disable(st->vref);
  1622. regulator_disable(st->reg);
  1623. return pinctrl_pm_select_sleep_state(dev);
  1624. }
  1625. static __maybe_unused int at91_adc_resume(struct device *dev)
  1626. {
  1627. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  1628. struct at91_adc_state *st = iio_priv(indio_dev);
  1629. int ret;
  1630. ret = pinctrl_pm_select_default_state(dev);
  1631. if (ret)
  1632. goto resume_failed;
  1633. ret = regulator_enable(st->reg);
  1634. if (ret)
  1635. goto resume_failed;
  1636. ret = regulator_enable(st->vref);
  1637. if (ret)
  1638. goto reg_disable_resume;
  1639. ret = clk_prepare_enable(st->per_clk);
  1640. if (ret)
  1641. goto vref_disable_resume;
  1642. at91_adc_hw_init(indio_dev);
  1643. /* reconfiguring trigger hardware state */
  1644. if (!iio_buffer_enabled(indio_dev))
  1645. return 0;
  1646. /* check if we are enabling triggered buffer or the touchscreen */
  1647. if (at91_adc_current_chan_is_touch(indio_dev))
  1648. return at91_adc_configure_touch(st, true);
  1649. else
  1650. return at91_adc_configure_trigger(st->trig, true);
  1651. /* not needed but more explicit */
  1652. return 0;
  1653. vref_disable_resume:
  1654. regulator_disable(st->vref);
  1655. reg_disable_resume:
  1656. regulator_disable(st->reg);
  1657. resume_failed:
  1658. dev_err(&indio_dev->dev, "failed to resume\n");
  1659. return ret;
  1660. }
  1661. static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume);
  1662. static const struct of_device_id at91_adc_dt_match[] = {
  1663. {
  1664. .compatible = "atmel,sama5d2-adc",
  1665. }, {
  1666. /* sentinel */
  1667. }
  1668. };
  1669. MODULE_DEVICE_TABLE(of, at91_adc_dt_match);
  1670. static struct platform_driver at91_adc_driver = {
  1671. .probe = at91_adc_probe,
  1672. .remove = at91_adc_remove,
  1673. .driver = {
  1674. .name = "at91-sama5d2_adc",
  1675. .of_match_table = at91_adc_dt_match,
  1676. .pm = &at91_adc_pm_ops,
  1677. },
  1678. };
  1679. module_platform_driver(at91_adc_driver)
  1680. MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
  1681. MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC");
  1682. MODULE_LICENSE("GPL v2");