aspeed_adc.c 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Aspeed AST2400/2500 ADC
  4. *
  5. * Copyright (C) 2017 Google, Inc.
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/clk-provider.h>
  9. #include <linux/err.h>
  10. #include <linux/errno.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/reset.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/types.h>
  18. #include <linux/iio/iio.h>
  19. #include <linux/iio/driver.h>
  20. #include <linux/iopoll.h>
  21. #define ASPEED_RESOLUTION_BITS 10
  22. #define ASPEED_CLOCKS_PER_SAMPLE 12
  23. #define ASPEED_REG_ENGINE_CONTROL 0x00
  24. #define ASPEED_REG_INTERRUPT_CONTROL 0x04
  25. #define ASPEED_REG_VGA_DETECT_CONTROL 0x08
  26. #define ASPEED_REG_CLOCK_CONTROL 0x0C
  27. #define ASPEED_REG_MAX 0xC0
  28. #define ASPEED_OPERATION_MODE_POWER_DOWN (0x0 << 1)
  29. #define ASPEED_OPERATION_MODE_STANDBY (0x1 << 1)
  30. #define ASPEED_OPERATION_MODE_NORMAL (0x7 << 1)
  31. #define ASPEED_ENGINE_ENABLE BIT(0)
  32. #define ASPEED_ADC_CTRL_INIT_RDY BIT(8)
  33. #define ASPEED_ADC_INIT_POLLING_TIME 500
  34. #define ASPEED_ADC_INIT_TIMEOUT 500000
  35. struct aspeed_adc_model_data {
  36. const char *model_name;
  37. unsigned int min_sampling_rate; // Hz
  38. unsigned int max_sampling_rate; // Hz
  39. unsigned int vref_voltage; // mV
  40. bool wait_init_sequence;
  41. };
  42. struct aspeed_adc_data {
  43. struct device *dev;
  44. void __iomem *base;
  45. spinlock_t clk_lock;
  46. struct clk_hw *clk_prescaler;
  47. struct clk_hw *clk_scaler;
  48. struct reset_control *rst;
  49. };
  50. #define ASPEED_CHAN(_idx, _data_reg_addr) { \
  51. .type = IIO_VOLTAGE, \
  52. .indexed = 1, \
  53. .channel = (_idx), \
  54. .address = (_data_reg_addr), \
  55. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  56. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
  57. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  58. }
  59. static const struct iio_chan_spec aspeed_adc_iio_channels[] = {
  60. ASPEED_CHAN(0, 0x10),
  61. ASPEED_CHAN(1, 0x12),
  62. ASPEED_CHAN(2, 0x14),
  63. ASPEED_CHAN(3, 0x16),
  64. ASPEED_CHAN(4, 0x18),
  65. ASPEED_CHAN(5, 0x1A),
  66. ASPEED_CHAN(6, 0x1C),
  67. ASPEED_CHAN(7, 0x1E),
  68. ASPEED_CHAN(8, 0x20),
  69. ASPEED_CHAN(9, 0x22),
  70. ASPEED_CHAN(10, 0x24),
  71. ASPEED_CHAN(11, 0x26),
  72. ASPEED_CHAN(12, 0x28),
  73. ASPEED_CHAN(13, 0x2A),
  74. ASPEED_CHAN(14, 0x2C),
  75. ASPEED_CHAN(15, 0x2E),
  76. };
  77. static int aspeed_adc_read_raw(struct iio_dev *indio_dev,
  78. struct iio_chan_spec const *chan,
  79. int *val, int *val2, long mask)
  80. {
  81. struct aspeed_adc_data *data = iio_priv(indio_dev);
  82. const struct aspeed_adc_model_data *model_data =
  83. of_device_get_match_data(data->dev);
  84. switch (mask) {
  85. case IIO_CHAN_INFO_RAW:
  86. *val = readw(data->base + chan->address);
  87. return IIO_VAL_INT;
  88. case IIO_CHAN_INFO_SCALE:
  89. *val = model_data->vref_voltage;
  90. *val2 = ASPEED_RESOLUTION_BITS;
  91. return IIO_VAL_FRACTIONAL_LOG2;
  92. case IIO_CHAN_INFO_SAMP_FREQ:
  93. *val = clk_get_rate(data->clk_scaler->clk) /
  94. ASPEED_CLOCKS_PER_SAMPLE;
  95. return IIO_VAL_INT;
  96. default:
  97. return -EINVAL;
  98. }
  99. }
  100. static int aspeed_adc_write_raw(struct iio_dev *indio_dev,
  101. struct iio_chan_spec const *chan,
  102. int val, int val2, long mask)
  103. {
  104. struct aspeed_adc_data *data = iio_priv(indio_dev);
  105. const struct aspeed_adc_model_data *model_data =
  106. of_device_get_match_data(data->dev);
  107. switch (mask) {
  108. case IIO_CHAN_INFO_SAMP_FREQ:
  109. if (val < model_data->min_sampling_rate ||
  110. val > model_data->max_sampling_rate)
  111. return -EINVAL;
  112. clk_set_rate(data->clk_scaler->clk,
  113. val * ASPEED_CLOCKS_PER_SAMPLE);
  114. return 0;
  115. case IIO_CHAN_INFO_SCALE:
  116. case IIO_CHAN_INFO_RAW:
  117. /*
  118. * Technically, these could be written but the only reasons
  119. * for doing so seem better handled in userspace. EPERM is
  120. * returned to signal this is a policy choice rather than a
  121. * hardware limitation.
  122. */
  123. return -EPERM;
  124. default:
  125. return -EINVAL;
  126. }
  127. }
  128. static int aspeed_adc_reg_access(struct iio_dev *indio_dev,
  129. unsigned int reg, unsigned int writeval,
  130. unsigned int *readval)
  131. {
  132. struct aspeed_adc_data *data = iio_priv(indio_dev);
  133. if (!readval || reg % 4 || reg > ASPEED_REG_MAX)
  134. return -EINVAL;
  135. *readval = readl(data->base + reg);
  136. return 0;
  137. }
  138. static const struct iio_info aspeed_adc_iio_info = {
  139. .read_raw = aspeed_adc_read_raw,
  140. .write_raw = aspeed_adc_write_raw,
  141. .debugfs_reg_access = aspeed_adc_reg_access,
  142. };
  143. static int aspeed_adc_probe(struct platform_device *pdev)
  144. {
  145. struct iio_dev *indio_dev;
  146. struct aspeed_adc_data *data;
  147. const struct aspeed_adc_model_data *model_data;
  148. const char *clk_parent_name;
  149. int ret;
  150. u32 adc_engine_control_reg_val;
  151. indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data));
  152. if (!indio_dev)
  153. return -ENOMEM;
  154. data = iio_priv(indio_dev);
  155. data->dev = &pdev->dev;
  156. platform_set_drvdata(pdev, indio_dev);
  157. data->base = devm_platform_ioremap_resource(pdev, 0);
  158. if (IS_ERR(data->base))
  159. return PTR_ERR(data->base);
  160. /* Register ADC clock prescaler with source specified by device tree. */
  161. spin_lock_init(&data->clk_lock);
  162. clk_parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
  163. data->clk_prescaler = clk_hw_register_divider(
  164. &pdev->dev, "prescaler", clk_parent_name, 0,
  165. data->base + ASPEED_REG_CLOCK_CONTROL,
  166. 17, 15, 0, &data->clk_lock);
  167. if (IS_ERR(data->clk_prescaler))
  168. return PTR_ERR(data->clk_prescaler);
  169. /*
  170. * Register ADC clock scaler downstream from the prescaler. Allow rate
  171. * setting to adjust the prescaler as well.
  172. */
  173. data->clk_scaler = clk_hw_register_divider(
  174. &pdev->dev, "scaler", "prescaler",
  175. CLK_SET_RATE_PARENT,
  176. data->base + ASPEED_REG_CLOCK_CONTROL,
  177. 0, 10, 0, &data->clk_lock);
  178. if (IS_ERR(data->clk_scaler)) {
  179. ret = PTR_ERR(data->clk_scaler);
  180. goto scaler_error;
  181. }
  182. data->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
  183. if (IS_ERR(data->rst)) {
  184. dev_err(&pdev->dev,
  185. "invalid or missing reset controller device tree entry");
  186. ret = PTR_ERR(data->rst);
  187. goto reset_error;
  188. }
  189. reset_control_deassert(data->rst);
  190. model_data = of_device_get_match_data(&pdev->dev);
  191. if (model_data->wait_init_sequence) {
  192. /* Enable engine in normal mode. */
  193. writel(ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE,
  194. data->base + ASPEED_REG_ENGINE_CONTROL);
  195. /* Wait for initial sequence complete. */
  196. ret = readl_poll_timeout(data->base + ASPEED_REG_ENGINE_CONTROL,
  197. adc_engine_control_reg_val,
  198. adc_engine_control_reg_val &
  199. ASPEED_ADC_CTRL_INIT_RDY,
  200. ASPEED_ADC_INIT_POLLING_TIME,
  201. ASPEED_ADC_INIT_TIMEOUT);
  202. if (ret)
  203. goto poll_timeout_error;
  204. }
  205. /* Start all channels in normal mode. */
  206. ret = clk_prepare_enable(data->clk_scaler->clk);
  207. if (ret)
  208. goto clk_enable_error;
  209. adc_engine_control_reg_val = GENMASK(31, 16) |
  210. ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE;
  211. writel(adc_engine_control_reg_val,
  212. data->base + ASPEED_REG_ENGINE_CONTROL);
  213. model_data = of_device_get_match_data(&pdev->dev);
  214. indio_dev->name = model_data->model_name;
  215. indio_dev->info = &aspeed_adc_iio_info;
  216. indio_dev->modes = INDIO_DIRECT_MODE;
  217. indio_dev->channels = aspeed_adc_iio_channels;
  218. indio_dev->num_channels = ARRAY_SIZE(aspeed_adc_iio_channels);
  219. ret = iio_device_register(indio_dev);
  220. if (ret)
  221. goto iio_register_error;
  222. return 0;
  223. iio_register_error:
  224. writel(ASPEED_OPERATION_MODE_POWER_DOWN,
  225. data->base + ASPEED_REG_ENGINE_CONTROL);
  226. clk_disable_unprepare(data->clk_scaler->clk);
  227. clk_enable_error:
  228. poll_timeout_error:
  229. reset_control_assert(data->rst);
  230. reset_error:
  231. clk_hw_unregister_divider(data->clk_scaler);
  232. scaler_error:
  233. clk_hw_unregister_divider(data->clk_prescaler);
  234. return ret;
  235. }
  236. static int aspeed_adc_remove(struct platform_device *pdev)
  237. {
  238. struct iio_dev *indio_dev = platform_get_drvdata(pdev);
  239. struct aspeed_adc_data *data = iio_priv(indio_dev);
  240. iio_device_unregister(indio_dev);
  241. writel(ASPEED_OPERATION_MODE_POWER_DOWN,
  242. data->base + ASPEED_REG_ENGINE_CONTROL);
  243. clk_disable_unprepare(data->clk_scaler->clk);
  244. reset_control_assert(data->rst);
  245. clk_hw_unregister_divider(data->clk_scaler);
  246. clk_hw_unregister_divider(data->clk_prescaler);
  247. return 0;
  248. }
  249. static const struct aspeed_adc_model_data ast2400_model_data = {
  250. .model_name = "ast2400-adc",
  251. .vref_voltage = 2500, // mV
  252. .min_sampling_rate = 10000,
  253. .max_sampling_rate = 500000,
  254. };
  255. static const struct aspeed_adc_model_data ast2500_model_data = {
  256. .model_name = "ast2500-adc",
  257. .vref_voltage = 1800, // mV
  258. .min_sampling_rate = 1,
  259. .max_sampling_rate = 1000000,
  260. .wait_init_sequence = true,
  261. };
  262. static const struct of_device_id aspeed_adc_matches[] = {
  263. { .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data },
  264. { .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data },
  265. {},
  266. };
  267. MODULE_DEVICE_TABLE(of, aspeed_adc_matches);
  268. static struct platform_driver aspeed_adc_driver = {
  269. .probe = aspeed_adc_probe,
  270. .remove = aspeed_adc_remove,
  271. .driver = {
  272. .name = KBUILD_MODNAME,
  273. .of_match_table = aspeed_adc_matches,
  274. }
  275. };
  276. module_platform_driver(aspeed_adc_driver);
  277. MODULE_AUTHOR("Rick Altherr <raltherr@google.com>");
  278. MODULE_DESCRIPTION("Aspeed AST2400/2500 ADC Driver");
  279. MODULE_LICENSE("GPL");