adi-axi-adc.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Analog Devices Generic AXI ADC IP core
  4. * Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
  5. *
  6. * Copyright 2012-2020 Analog Devices Inc.
  7. */
  8. #include <linux/bitfield.h>
  9. #include <linux/clk.h>
  10. #include <linux/io.h>
  11. #include <linux/delay.h>
  12. #include <linux/module.h>
  13. #include <linux/of_device.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/slab.h>
  16. #include <linux/iio/iio.h>
  17. #include <linux/iio/sysfs.h>
  18. #include <linux/iio/buffer.h>
  19. #include <linux/iio/buffer-dmaengine.h>
  20. #include <linux/fpga/adi-axi-common.h>
  21. #include <linux/iio/adc/adi-axi-adc.h>
  22. /**
  23. * Register definitions:
  24. * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map
  25. */
  26. /* ADC controls */
  27. #define ADI_AXI_REG_RSTN 0x0040
  28. #define ADI_AXI_REG_RSTN_CE_N BIT(2)
  29. #define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1)
  30. #define ADI_AXI_REG_RSTN_RSTN BIT(0)
  31. /* ADC Channel controls */
  32. #define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40)
  33. #define ADI_AXI_REG_CHAN_CTRL_LB_OWR BIT(11)
  34. #define ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR BIT(10)
  35. #define ADI_AXI_REG_CHAN_CTRL_IQCOR_EN BIT(9)
  36. #define ADI_AXI_REG_CHAN_CTRL_DCFILT_EN BIT(8)
  37. #define ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT BIT(6)
  38. #define ADI_AXI_REG_CHAN_CTRL_FMT_TYPE BIT(5)
  39. #define ADI_AXI_REG_CHAN_CTRL_FMT_EN BIT(4)
  40. #define ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR BIT(1)
  41. #define ADI_AXI_REG_CHAN_CTRL_ENABLE BIT(0)
  42. #define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \
  43. (ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT | \
  44. ADI_AXI_REG_CHAN_CTRL_FMT_EN | \
  45. ADI_AXI_REG_CHAN_CTRL_ENABLE)
  46. struct adi_axi_adc_core_info {
  47. unsigned int version;
  48. };
  49. struct adi_axi_adc_state {
  50. struct mutex lock;
  51. struct adi_axi_adc_client *client;
  52. void __iomem *regs;
  53. };
  54. struct adi_axi_adc_client {
  55. struct list_head entry;
  56. struct adi_axi_adc_conv conv;
  57. struct adi_axi_adc_state *state;
  58. struct device *dev;
  59. const struct adi_axi_adc_core_info *info;
  60. };
  61. static LIST_HEAD(registered_clients);
  62. static DEFINE_MUTEX(registered_clients_lock);
  63. static struct adi_axi_adc_client *conv_to_client(struct adi_axi_adc_conv *conv)
  64. {
  65. return container_of(conv, struct adi_axi_adc_client, conv);
  66. }
  67. void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv)
  68. {
  69. struct adi_axi_adc_client *cl = conv_to_client(conv);
  70. return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN);
  71. }
  72. EXPORT_SYMBOL_GPL(adi_axi_adc_conv_priv);
  73. static void adi_axi_adc_write(struct adi_axi_adc_state *st,
  74. unsigned int reg,
  75. unsigned int val)
  76. {
  77. iowrite32(val, st->regs + reg);
  78. }
  79. static unsigned int adi_axi_adc_read(struct adi_axi_adc_state *st,
  80. unsigned int reg)
  81. {
  82. return ioread32(st->regs + reg);
  83. }
  84. static int adi_axi_adc_config_dma_buffer(struct device *dev,
  85. struct iio_dev *indio_dev)
  86. {
  87. struct iio_buffer *buffer;
  88. const char *dma_name;
  89. if (!device_property_present(dev, "dmas"))
  90. return 0;
  91. if (device_property_read_string(dev, "dma-names", &dma_name))
  92. dma_name = "rx";
  93. buffer = devm_iio_dmaengine_buffer_alloc(indio_dev->dev.parent,
  94. dma_name);
  95. if (IS_ERR(buffer))
  96. return PTR_ERR(buffer);
  97. indio_dev->modes |= INDIO_BUFFER_HARDWARE;
  98. iio_device_attach_buffer(indio_dev, buffer);
  99. return 0;
  100. }
  101. static int adi_axi_adc_read_raw(struct iio_dev *indio_dev,
  102. struct iio_chan_spec const *chan,
  103. int *val, int *val2, long mask)
  104. {
  105. struct adi_axi_adc_state *st = iio_priv(indio_dev);
  106. struct adi_axi_adc_conv *conv = &st->client->conv;
  107. if (!conv->read_raw)
  108. return -EOPNOTSUPP;
  109. return conv->read_raw(conv, chan, val, val2, mask);
  110. }
  111. static int adi_axi_adc_write_raw(struct iio_dev *indio_dev,
  112. struct iio_chan_spec const *chan,
  113. int val, int val2, long mask)
  114. {
  115. struct adi_axi_adc_state *st = iio_priv(indio_dev);
  116. struct adi_axi_adc_conv *conv = &st->client->conv;
  117. if (!conv->write_raw)
  118. return -EOPNOTSUPP;
  119. return conv->write_raw(conv, chan, val, val2, mask);
  120. }
  121. static int adi_axi_adc_update_scan_mode(struct iio_dev *indio_dev,
  122. const unsigned long *scan_mask)
  123. {
  124. struct adi_axi_adc_state *st = iio_priv(indio_dev);
  125. struct adi_axi_adc_conv *conv = &st->client->conv;
  126. unsigned int i, ctrl;
  127. for (i = 0; i < conv->chip_info->num_channels; i++) {
  128. ctrl = adi_axi_adc_read(st, ADI_AXI_REG_CHAN_CTRL(i));
  129. if (test_bit(i, scan_mask))
  130. ctrl |= ADI_AXI_REG_CHAN_CTRL_ENABLE;
  131. else
  132. ctrl &= ~ADI_AXI_REG_CHAN_CTRL_ENABLE;
  133. adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i), ctrl);
  134. }
  135. return 0;
  136. }
  137. static struct adi_axi_adc_conv *adi_axi_adc_conv_register(struct device *dev,
  138. size_t sizeof_priv)
  139. {
  140. struct adi_axi_adc_client *cl;
  141. size_t alloc_size;
  142. alloc_size = ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN);
  143. if (sizeof_priv)
  144. alloc_size += ALIGN(sizeof_priv, IIO_ALIGN);
  145. cl = kzalloc(alloc_size, GFP_KERNEL);
  146. if (!cl)
  147. return ERR_PTR(-ENOMEM);
  148. mutex_lock(&registered_clients_lock);
  149. cl->dev = get_device(dev);
  150. list_add_tail(&cl->entry, &registered_clients);
  151. mutex_unlock(&registered_clients_lock);
  152. return &cl->conv;
  153. }
  154. static void adi_axi_adc_conv_unregister(struct adi_axi_adc_conv *conv)
  155. {
  156. struct adi_axi_adc_client *cl = conv_to_client(conv);
  157. mutex_lock(&registered_clients_lock);
  158. list_del(&cl->entry);
  159. put_device(cl->dev);
  160. mutex_unlock(&registered_clients_lock);
  161. kfree(cl);
  162. }
  163. static void devm_adi_axi_adc_conv_release(struct device *dev, void *res)
  164. {
  165. adi_axi_adc_conv_unregister(*(struct adi_axi_adc_conv **)res);
  166. }
  167. struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev,
  168. size_t sizeof_priv)
  169. {
  170. struct adi_axi_adc_conv **ptr, *conv;
  171. ptr = devres_alloc(devm_adi_axi_adc_conv_release, sizeof(*ptr),
  172. GFP_KERNEL);
  173. if (!ptr)
  174. return ERR_PTR(-ENOMEM);
  175. conv = adi_axi_adc_conv_register(dev, sizeof_priv);
  176. if (IS_ERR(conv)) {
  177. devres_free(ptr);
  178. return ERR_CAST(conv);
  179. }
  180. *ptr = conv;
  181. devres_add(dev, ptr);
  182. return conv;
  183. }
  184. EXPORT_SYMBOL_GPL(devm_adi_axi_adc_conv_register);
  185. static ssize_t in_voltage_scale_available_show(struct device *dev,
  186. struct device_attribute *attr,
  187. char *buf)
  188. {
  189. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  190. struct adi_axi_adc_state *st = iio_priv(indio_dev);
  191. struct adi_axi_adc_conv *conv = &st->client->conv;
  192. size_t len = 0;
  193. int i;
  194. for (i = 0; i < conv->chip_info->num_scales; i++) {
  195. const unsigned int *s = conv->chip_info->scale_table[i];
  196. len += scnprintf(buf + len, PAGE_SIZE - len,
  197. "%u.%06u ", s[0], s[1]);
  198. }
  199. buf[len - 1] = '\n';
  200. return len;
  201. }
  202. static IIO_DEVICE_ATTR_RO(in_voltage_scale_available, 0);
  203. enum {
  204. ADI_AXI_ATTR_SCALE_AVAIL,
  205. };
  206. #define ADI_AXI_ATTR(_en_, _file_) \
  207. [ADI_AXI_ATTR_##_en_] = &iio_dev_attr_##_file_.dev_attr.attr
  208. static struct attribute *adi_axi_adc_attributes[] = {
  209. ADI_AXI_ATTR(SCALE_AVAIL, in_voltage_scale_available),
  210. NULL
  211. };
  212. static umode_t axi_adc_attr_is_visible(struct kobject *kobj,
  213. struct attribute *attr, int n)
  214. {
  215. struct device *dev = kobj_to_dev(kobj);
  216. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  217. struct adi_axi_adc_state *st = iio_priv(indio_dev);
  218. struct adi_axi_adc_conv *conv = &st->client->conv;
  219. switch (n) {
  220. case ADI_AXI_ATTR_SCALE_AVAIL:
  221. if (!conv->chip_info->num_scales)
  222. return 0;
  223. return attr->mode;
  224. default:
  225. return attr->mode;
  226. }
  227. }
  228. static const struct attribute_group adi_axi_adc_attribute_group = {
  229. .attrs = adi_axi_adc_attributes,
  230. .is_visible = axi_adc_attr_is_visible,
  231. };
  232. static const struct iio_info adi_axi_adc_info = {
  233. .read_raw = &adi_axi_adc_read_raw,
  234. .write_raw = &adi_axi_adc_write_raw,
  235. .attrs = &adi_axi_adc_attribute_group,
  236. .update_scan_mode = &adi_axi_adc_update_scan_mode,
  237. };
  238. static const struct adi_axi_adc_core_info adi_axi_adc_10_0_a_info = {
  239. .version = ADI_AXI_PCORE_VER(10, 0, 'a'),
  240. };
  241. static struct adi_axi_adc_client *adi_axi_adc_attach_client(struct device *dev)
  242. {
  243. const struct adi_axi_adc_core_info *info;
  244. struct adi_axi_adc_client *cl;
  245. struct device_node *cln;
  246. info = of_device_get_match_data(dev);
  247. if (!info)
  248. return ERR_PTR(-ENODEV);
  249. cln = of_parse_phandle(dev->of_node, "adi,adc-dev", 0);
  250. if (!cln) {
  251. dev_err(dev, "No 'adi,adc-dev' node defined\n");
  252. return ERR_PTR(-ENODEV);
  253. }
  254. mutex_lock(&registered_clients_lock);
  255. list_for_each_entry(cl, &registered_clients, entry) {
  256. if (!cl->dev)
  257. continue;
  258. if (cl->dev->of_node != cln)
  259. continue;
  260. if (!try_module_get(cl->dev->driver->owner)) {
  261. mutex_unlock(&registered_clients_lock);
  262. return ERR_PTR(-ENODEV);
  263. }
  264. get_device(cl->dev);
  265. cl->info = info;
  266. mutex_unlock(&registered_clients_lock);
  267. return cl;
  268. }
  269. mutex_unlock(&registered_clients_lock);
  270. return ERR_PTR(-EPROBE_DEFER);
  271. }
  272. static int adi_axi_adc_setup_channels(struct device *dev,
  273. struct adi_axi_adc_state *st)
  274. {
  275. struct adi_axi_adc_conv *conv = &st->client->conv;
  276. int i, ret;
  277. if (conv->preenable_setup) {
  278. ret = conv->preenable_setup(conv);
  279. if (ret)
  280. return ret;
  281. }
  282. for (i = 0; i < conv->chip_info->num_channels; i++) {
  283. adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i),
  284. ADI_AXI_REG_CHAN_CTRL_DEFAULTS);
  285. }
  286. return 0;
  287. }
  288. static void axi_adc_reset(struct adi_axi_adc_state *st)
  289. {
  290. adi_axi_adc_write(st, ADI_AXI_REG_RSTN, 0);
  291. mdelay(10);
  292. adi_axi_adc_write(st, ADI_AXI_REG_RSTN, ADI_AXI_REG_RSTN_MMCM_RSTN);
  293. mdelay(10);
  294. adi_axi_adc_write(st, ADI_AXI_REG_RSTN,
  295. ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN);
  296. }
  297. static void adi_axi_adc_cleanup(void *data)
  298. {
  299. struct adi_axi_adc_client *cl = data;
  300. put_device(cl->dev);
  301. module_put(cl->dev->driver->owner);
  302. }
  303. static int adi_axi_adc_probe(struct platform_device *pdev)
  304. {
  305. struct adi_axi_adc_conv *conv;
  306. struct iio_dev *indio_dev;
  307. struct adi_axi_adc_client *cl;
  308. struct adi_axi_adc_state *st;
  309. unsigned int ver;
  310. int ret;
  311. cl = adi_axi_adc_attach_client(&pdev->dev);
  312. if (IS_ERR(cl))
  313. return PTR_ERR(cl);
  314. ret = devm_add_action_or_reset(&pdev->dev, adi_axi_adc_cleanup, cl);
  315. if (ret)
  316. return ret;
  317. indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
  318. if (indio_dev == NULL)
  319. return -ENOMEM;
  320. st = iio_priv(indio_dev);
  321. st->client = cl;
  322. cl->state = st;
  323. mutex_init(&st->lock);
  324. st->regs = devm_platform_ioremap_resource(pdev, 0);
  325. if (IS_ERR(st->regs))
  326. return PTR_ERR(st->regs);
  327. conv = &st->client->conv;
  328. axi_adc_reset(st);
  329. ver = adi_axi_adc_read(st, ADI_AXI_REG_VERSION);
  330. if (cl->info->version > ver) {
  331. dev_err(&pdev->dev,
  332. "IP core version is too old. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
  333. ADI_AXI_PCORE_VER_MAJOR(cl->info->version),
  334. ADI_AXI_PCORE_VER_MINOR(cl->info->version),
  335. ADI_AXI_PCORE_VER_PATCH(cl->info->version),
  336. ADI_AXI_PCORE_VER_MAJOR(ver),
  337. ADI_AXI_PCORE_VER_MINOR(ver),
  338. ADI_AXI_PCORE_VER_PATCH(ver));
  339. return -ENODEV;
  340. }
  341. indio_dev->info = &adi_axi_adc_info;
  342. indio_dev->name = "adi-axi-adc";
  343. indio_dev->modes = INDIO_DIRECT_MODE;
  344. indio_dev->num_channels = conv->chip_info->num_channels;
  345. indio_dev->channels = conv->chip_info->channels;
  346. ret = adi_axi_adc_config_dma_buffer(&pdev->dev, indio_dev);
  347. if (ret)
  348. return ret;
  349. ret = adi_axi_adc_setup_channels(&pdev->dev, st);
  350. if (ret)
  351. return ret;
  352. ret = devm_iio_device_register(&pdev->dev, indio_dev);
  353. if (ret)
  354. return ret;
  355. dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n",
  356. ADI_AXI_PCORE_VER_MAJOR(ver),
  357. ADI_AXI_PCORE_VER_MINOR(ver),
  358. ADI_AXI_PCORE_VER_PATCH(ver));
  359. return 0;
  360. }
  361. /* Match table for of_platform binding */
  362. static const struct of_device_id adi_axi_adc_of_match[] = {
  363. { .compatible = "adi,axi-adc-10.0.a", .data = &adi_axi_adc_10_0_a_info },
  364. { /* end of list */ }
  365. };
  366. MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match);
  367. static struct platform_driver adi_axi_adc_driver = {
  368. .driver = {
  369. .name = KBUILD_MODNAME,
  370. .of_match_table = adi_axi_adc_of_match,
  371. },
  372. .probe = adi_axi_adc_probe,
  373. };
  374. module_platform_driver(adi_axi_adc_driver);
  375. MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
  376. MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver");
  377. MODULE_LICENSE("GPL v2");