ad9467.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Analog Devices AD9467 SPI ADC driver
  4. *
  5. * Copyright 2012-2020 Analog Devices Inc.
  6. */
  7. #include <linux/module.h>
  8. #include <linux/device.h>
  9. #include <linux/kernel.h>
  10. #include <linux/slab.h>
  11. #include <linux/spi/spi.h>
  12. #include <linux/err.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio/consumer.h>
  15. #include <linux/of_device.h>
  16. #include <linux/iio/iio.h>
  17. #include <linux/iio/sysfs.h>
  18. #include <linux/clk.h>
  19. #include <linux/iio/adc/adi-axi-adc.h>
  20. /*
  21. * ADI High-Speed ADC common spi interface registers
  22. * See Application-Note AN-877:
  23. * https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf
  24. */
  25. #define AN877_ADC_REG_CHIP_PORT_CONF 0x00
  26. #define AN877_ADC_REG_CHIP_ID 0x01
  27. #define AN877_ADC_REG_CHIP_GRADE 0x02
  28. #define AN877_ADC_REG_CHAN_INDEX 0x05
  29. #define AN877_ADC_REG_TRANSFER 0xFF
  30. #define AN877_ADC_REG_MODES 0x08
  31. #define AN877_ADC_REG_TEST_IO 0x0D
  32. #define AN877_ADC_REG_ADC_INPUT 0x0F
  33. #define AN877_ADC_REG_OFFSET 0x10
  34. #define AN877_ADC_REG_OUTPUT_MODE 0x14
  35. #define AN877_ADC_REG_OUTPUT_ADJUST 0x15
  36. #define AN877_ADC_REG_OUTPUT_PHASE 0x16
  37. #define AN877_ADC_REG_OUTPUT_DELAY 0x17
  38. #define AN877_ADC_REG_VREF 0x18
  39. #define AN877_ADC_REG_ANALOG_INPUT 0x2C
  40. /* AN877_ADC_REG_TEST_IO */
  41. #define AN877_ADC_TESTMODE_OFF 0x0
  42. #define AN877_ADC_TESTMODE_MIDSCALE_SHORT 0x1
  43. #define AN877_ADC_TESTMODE_POS_FULLSCALE 0x2
  44. #define AN877_ADC_TESTMODE_NEG_FULLSCALE 0x3
  45. #define AN877_ADC_TESTMODE_ALT_CHECKERBOARD 0x4
  46. #define AN877_ADC_TESTMODE_PN23_SEQ 0x5
  47. #define AN877_ADC_TESTMODE_PN9_SEQ 0x6
  48. #define AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE 0x7
  49. #define AN877_ADC_TESTMODE_USER 0x8
  50. #define AN877_ADC_TESTMODE_BIT_TOGGLE 0x9
  51. #define AN877_ADC_TESTMODE_SYNC 0xA
  52. #define AN877_ADC_TESTMODE_ONE_BIT_HIGH 0xB
  53. #define AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY 0xC
  54. #define AN877_ADC_TESTMODE_RAMP 0xF
  55. /* AN877_ADC_REG_TRANSFER */
  56. #define AN877_ADC_TRANSFER_SYNC 0x1
  57. /* AN877_ADC_REG_OUTPUT_MODE */
  58. #define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY 0x0
  59. #define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT 0x1
  60. #define AN877_ADC_OUTPUT_MODE_GRAY_CODE 0x2
  61. /* AN877_ADC_REG_OUTPUT_PHASE */
  62. #define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN 0x20
  63. #define AN877_ADC_INVERT_DCO_CLK 0x80
  64. /* AN877_ADC_REG_OUTPUT_DELAY */
  65. #define AN877_ADC_DCO_DELAY_ENABLE 0x80
  66. /*
  67. * Analog Devices AD9265 16-Bit, 125/105/80 MSPS ADC
  68. */
  69. #define CHIPID_AD9265 0x64
  70. #define AD9265_DEF_OUTPUT_MODE 0x40
  71. #define AD9265_REG_VREF_MASK 0xC0
  72. /*
  73. * Analog Devices AD9434 12-Bit, 370/500 MSPS ADC
  74. */
  75. #define CHIPID_AD9434 0x6A
  76. #define AD9434_DEF_OUTPUT_MODE 0x00
  77. #define AD9434_REG_VREF_MASK 0xC0
  78. /*
  79. * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC
  80. */
  81. #define CHIPID_AD9467 0x50
  82. #define AD9467_DEF_OUTPUT_MODE 0x08
  83. #define AD9467_REG_VREF_MASK 0x0F
  84. enum {
  85. ID_AD9265,
  86. ID_AD9434,
  87. ID_AD9467,
  88. };
  89. struct ad9467_chip_info {
  90. struct adi_axi_adc_chip_info axi_adc_info;
  91. unsigned int default_output_mode;
  92. unsigned int vref_mask;
  93. };
  94. #define to_ad9467_chip_info(_info) \
  95. container_of(_info, struct ad9467_chip_info, axi_adc_info)
  96. struct ad9467_state {
  97. struct spi_device *spi;
  98. struct clk *clk;
  99. unsigned int output_mode;
  100. struct gpio_desc *pwrdown_gpio;
  101. struct gpio_desc *reset_gpio;
  102. };
  103. static int ad9467_spi_read(struct spi_device *spi, unsigned int reg)
  104. {
  105. unsigned char tbuf[2], rbuf[1];
  106. int ret;
  107. tbuf[0] = 0x80 | (reg >> 8);
  108. tbuf[1] = reg & 0xFF;
  109. ret = spi_write_then_read(spi,
  110. tbuf, ARRAY_SIZE(tbuf),
  111. rbuf, ARRAY_SIZE(rbuf));
  112. if (ret < 0)
  113. return ret;
  114. return rbuf[0];
  115. }
  116. static int ad9467_spi_write(struct spi_device *spi, unsigned int reg,
  117. unsigned int val)
  118. {
  119. unsigned char buf[3];
  120. buf[0] = reg >> 8;
  121. buf[1] = reg & 0xFF;
  122. buf[2] = val;
  123. return spi_write(spi, buf, ARRAY_SIZE(buf));
  124. }
  125. static int ad9467_reg_access(struct adi_axi_adc_conv *conv, unsigned int reg,
  126. unsigned int writeval, unsigned int *readval)
  127. {
  128. struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
  129. struct spi_device *spi = st->spi;
  130. int ret;
  131. if (readval == NULL) {
  132. ret = ad9467_spi_write(spi, reg, writeval);
  133. ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER,
  134. AN877_ADC_TRANSFER_SYNC);
  135. return ret;
  136. }
  137. ret = ad9467_spi_read(spi, reg);
  138. if (ret < 0)
  139. return ret;
  140. *readval = ret;
  141. return 0;
  142. }
  143. static const unsigned int ad9265_scale_table[][2] = {
  144. {1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0},
  145. };
  146. static const unsigned int ad9434_scale_table[][2] = {
  147. {1600, 0x1C}, {1580, 0x1D}, {1550, 0x1E}, {1520, 0x1F}, {1500, 0x00},
  148. {1470, 0x01}, {1440, 0x02}, {1420, 0x03}, {1390, 0x04}, {1360, 0x05},
  149. {1340, 0x06}, {1310, 0x07}, {1280, 0x08}, {1260, 0x09}, {1230, 0x0A},
  150. {1200, 0x0B}, {1180, 0x0C},
  151. };
  152. static const unsigned int ad9467_scale_table[][2] = {
  153. {2000, 0}, {2100, 6}, {2200, 7},
  154. {2300, 8}, {2400, 9}, {2500, 10},
  155. };
  156. static void __ad9467_get_scale(struct adi_axi_adc_conv *conv, int index,
  157. unsigned int *val, unsigned int *val2)
  158. {
  159. const struct adi_axi_adc_chip_info *info = conv->chip_info;
  160. const struct iio_chan_spec *chan = &info->channels[0];
  161. unsigned int tmp;
  162. tmp = (info->scale_table[index][0] * 1000000ULL) >>
  163. chan->scan_type.realbits;
  164. *val = tmp / 1000000;
  165. *val2 = tmp % 1000000;
  166. }
  167. #define AD9467_CHAN(_chan, _si, _bits, _sign) \
  168. { \
  169. .type = IIO_VOLTAGE, \
  170. .indexed = 1, \
  171. .channel = _chan, \
  172. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
  173. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  174. .scan_index = _si, \
  175. .scan_type = { \
  176. .sign = _sign, \
  177. .realbits = _bits, \
  178. .storagebits = 16, \
  179. }, \
  180. }
  181. static const struct iio_chan_spec ad9434_channels[] = {
  182. AD9467_CHAN(0, 0, 12, 'S'),
  183. };
  184. static const struct iio_chan_spec ad9467_channels[] = {
  185. AD9467_CHAN(0, 0, 16, 'S'),
  186. };
  187. static const struct ad9467_chip_info ad9467_chip_tbl[] = {
  188. [ID_AD9265] = {
  189. .axi_adc_info = {
  190. .id = CHIPID_AD9265,
  191. .max_rate = 125000000UL,
  192. .scale_table = ad9265_scale_table,
  193. .num_scales = ARRAY_SIZE(ad9265_scale_table),
  194. .channels = ad9467_channels,
  195. .num_channels = ARRAY_SIZE(ad9467_channels),
  196. },
  197. .default_output_mode = AD9265_DEF_OUTPUT_MODE,
  198. .vref_mask = AD9265_REG_VREF_MASK,
  199. },
  200. [ID_AD9434] = {
  201. .axi_adc_info = {
  202. .id = CHIPID_AD9434,
  203. .max_rate = 500000000UL,
  204. .scale_table = ad9434_scale_table,
  205. .num_scales = ARRAY_SIZE(ad9434_scale_table),
  206. .channels = ad9434_channels,
  207. .num_channels = ARRAY_SIZE(ad9434_channels),
  208. },
  209. .default_output_mode = AD9434_DEF_OUTPUT_MODE,
  210. .vref_mask = AD9434_REG_VREF_MASK,
  211. },
  212. [ID_AD9467] = {
  213. .axi_adc_info = {
  214. .id = CHIPID_AD9467,
  215. .max_rate = 250000000UL,
  216. .scale_table = ad9467_scale_table,
  217. .num_scales = ARRAY_SIZE(ad9467_scale_table),
  218. .channels = ad9467_channels,
  219. .num_channels = ARRAY_SIZE(ad9467_channels),
  220. },
  221. .default_output_mode = AD9467_DEF_OUTPUT_MODE,
  222. .vref_mask = AD9467_REG_VREF_MASK,
  223. },
  224. };
  225. static int ad9467_get_scale(struct adi_axi_adc_conv *conv, int *val, int *val2)
  226. {
  227. const struct adi_axi_adc_chip_info *info = conv->chip_info;
  228. const struct ad9467_chip_info *info1 = to_ad9467_chip_info(info);
  229. struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
  230. unsigned int i, vref_val;
  231. vref_val = ad9467_spi_read(st->spi, AN877_ADC_REG_VREF);
  232. vref_val &= info1->vref_mask;
  233. for (i = 0; i < info->num_scales; i++) {
  234. if (vref_val == info->scale_table[i][1])
  235. break;
  236. }
  237. if (i == info->num_scales)
  238. return -ERANGE;
  239. __ad9467_get_scale(conv, i, val, val2);
  240. return IIO_VAL_INT_PLUS_MICRO;
  241. }
  242. static int ad9467_set_scale(struct adi_axi_adc_conv *conv, int val, int val2)
  243. {
  244. const struct adi_axi_adc_chip_info *info = conv->chip_info;
  245. struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
  246. unsigned int scale_val[2];
  247. unsigned int i;
  248. if (val != 0)
  249. return -EINVAL;
  250. for (i = 0; i < info->num_scales; i++) {
  251. __ad9467_get_scale(conv, i, &scale_val[0], &scale_val[1]);
  252. if (scale_val[0] != val || scale_val[1] != val2)
  253. continue;
  254. ad9467_spi_write(st->spi, AN877_ADC_REG_VREF,
  255. info->scale_table[i][1]);
  256. ad9467_spi_write(st->spi, AN877_ADC_REG_TRANSFER,
  257. AN877_ADC_TRANSFER_SYNC);
  258. return 0;
  259. }
  260. return -EINVAL;
  261. }
  262. static int ad9467_read_raw(struct adi_axi_adc_conv *conv,
  263. struct iio_chan_spec const *chan,
  264. int *val, int *val2, long m)
  265. {
  266. struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
  267. switch (m) {
  268. case IIO_CHAN_INFO_SCALE:
  269. return ad9467_get_scale(conv, val, val2);
  270. case IIO_CHAN_INFO_SAMP_FREQ:
  271. *val = clk_get_rate(st->clk);
  272. return IIO_VAL_INT;
  273. default:
  274. return -EINVAL;
  275. }
  276. }
  277. static int ad9467_write_raw(struct adi_axi_adc_conv *conv,
  278. struct iio_chan_spec const *chan,
  279. int val, int val2, long mask)
  280. {
  281. const struct adi_axi_adc_chip_info *info = conv->chip_info;
  282. struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
  283. long r_clk;
  284. switch (mask) {
  285. case IIO_CHAN_INFO_SCALE:
  286. return ad9467_set_scale(conv, val, val2);
  287. case IIO_CHAN_INFO_SAMP_FREQ:
  288. r_clk = clk_round_rate(st->clk, val);
  289. if (r_clk < 0 || r_clk > info->max_rate) {
  290. dev_warn(&st->spi->dev,
  291. "Error setting ADC sample rate %ld", r_clk);
  292. return -EINVAL;
  293. }
  294. return clk_set_rate(st->clk, r_clk);
  295. default:
  296. return -EINVAL;
  297. }
  298. }
  299. static int ad9467_outputmode_set(struct spi_device *spi, unsigned int mode)
  300. {
  301. int ret;
  302. ret = ad9467_spi_write(spi, AN877_ADC_REG_OUTPUT_MODE, mode);
  303. if (ret < 0)
  304. return ret;
  305. return ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER,
  306. AN877_ADC_TRANSFER_SYNC);
  307. }
  308. static int ad9467_preenable_setup(struct adi_axi_adc_conv *conv)
  309. {
  310. struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
  311. return ad9467_outputmode_set(st->spi, st->output_mode);
  312. }
  313. static void ad9467_clk_disable(void *data)
  314. {
  315. struct ad9467_state *st = data;
  316. clk_disable_unprepare(st->clk);
  317. }
  318. static int ad9467_probe(struct spi_device *spi)
  319. {
  320. const struct ad9467_chip_info *info;
  321. struct adi_axi_adc_conv *conv;
  322. struct ad9467_state *st;
  323. unsigned int id;
  324. int ret;
  325. info = of_device_get_match_data(&spi->dev);
  326. if (!info)
  327. return -ENODEV;
  328. conv = devm_adi_axi_adc_conv_register(&spi->dev, sizeof(*st));
  329. if (IS_ERR(conv))
  330. return PTR_ERR(conv);
  331. st = adi_axi_adc_conv_priv(conv);
  332. st->spi = spi;
  333. st->clk = devm_clk_get(&spi->dev, "adc-clk");
  334. if (IS_ERR(st->clk))
  335. return PTR_ERR(st->clk);
  336. ret = clk_prepare_enable(st->clk);
  337. if (ret < 0)
  338. return ret;
  339. ret = devm_add_action_or_reset(&spi->dev, ad9467_clk_disable, st);
  340. if (ret)
  341. return ret;
  342. st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown",
  343. GPIOD_OUT_LOW);
  344. if (IS_ERR(st->pwrdown_gpio))
  345. return PTR_ERR(st->pwrdown_gpio);
  346. st->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset",
  347. GPIOD_OUT_LOW);
  348. if (IS_ERR(st->reset_gpio))
  349. return PTR_ERR(st->reset_gpio);
  350. if (st->reset_gpio) {
  351. udelay(1);
  352. ret = gpiod_direction_output(st->reset_gpio, 1);
  353. if (ret)
  354. return ret;
  355. mdelay(10);
  356. }
  357. spi_set_drvdata(spi, st);
  358. conv->chip_info = &info->axi_adc_info;
  359. id = ad9467_spi_read(spi, AN877_ADC_REG_CHIP_ID);
  360. if (id != conv->chip_info->id) {
  361. dev_err(&spi->dev, "Mismatch CHIP_ID, got 0x%X, expected 0x%X\n",
  362. id, conv->chip_info->id);
  363. return -ENODEV;
  364. }
  365. conv->reg_access = ad9467_reg_access;
  366. conv->write_raw = ad9467_write_raw;
  367. conv->read_raw = ad9467_read_raw;
  368. conv->preenable_setup = ad9467_preenable_setup;
  369. st->output_mode = info->default_output_mode |
  370. AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT;
  371. return 0;
  372. }
  373. static const struct of_device_id ad9467_of_match[] = {
  374. { .compatible = "adi,ad9265", .data = &ad9467_chip_tbl[ID_AD9265], },
  375. { .compatible = "adi,ad9434", .data = &ad9467_chip_tbl[ID_AD9434], },
  376. { .compatible = "adi,ad9467", .data = &ad9467_chip_tbl[ID_AD9467], },
  377. {}
  378. };
  379. MODULE_DEVICE_TABLE(of, ad9467_of_match);
  380. static struct spi_driver ad9467_driver = {
  381. .driver = {
  382. .name = "ad9467",
  383. .of_match_table = ad9467_of_match,
  384. },
  385. .probe = ad9467_probe,
  386. };
  387. module_spi_driver(ad9467_driver);
  388. MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
  389. MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver");
  390. MODULE_LICENSE("GPL v2");