ad7793.c 26 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * AD7785/AD7792/AD7793/AD7794/AD7795 SPI ADC driver
  4. *
  5. * Copyright 2011-2012 Analog Devices Inc.
  6. */
  7. #include <linux/interrupt.h>
  8. #include <linux/device.h>
  9. #include <linux/kernel.h>
  10. #include <linux/slab.h>
  11. #include <linux/sysfs.h>
  12. #include <linux/spi/spi.h>
  13. #include <linux/regulator/consumer.h>
  14. #include <linux/err.h>
  15. #include <linux/sched.h>
  16. #include <linux/delay.h>
  17. #include <linux/module.h>
  18. #include <linux/iio/iio.h>
  19. #include <linux/iio/sysfs.h>
  20. #include <linux/iio/buffer.h>
  21. #include <linux/iio/trigger.h>
  22. #include <linux/iio/trigger_consumer.h>
  23. #include <linux/iio/triggered_buffer.h>
  24. #include <linux/iio/adc/ad_sigma_delta.h>
  25. #include <linux/platform_data/ad7793.h>
  26. /* Registers */
  27. #define AD7793_REG_COMM 0 /* Communications Register (WO, 8-bit) */
  28. #define AD7793_REG_STAT 0 /* Status Register (RO, 8-bit) */
  29. #define AD7793_REG_MODE 1 /* Mode Register (RW, 16-bit */
  30. #define AD7793_REG_CONF 2 /* Configuration Register (RW, 16-bit) */
  31. #define AD7793_REG_DATA 3 /* Data Register (RO, 16-/24-bit) */
  32. #define AD7793_REG_ID 4 /* ID Register (RO, 8-bit) */
  33. #define AD7793_REG_IO 5 /* IO Register (RO, 8-bit) */
  34. #define AD7793_REG_OFFSET 6 /* Offset Register (RW, 16-bit
  35. * (AD7792)/24-bit (AD7793)) */
  36. #define AD7793_REG_FULLSALE 7 /* Full-Scale Register
  37. * (RW, 16-bit (AD7792)/24-bit (AD7793)) */
  38. /* Communications Register Bit Designations (AD7793_REG_COMM) */
  39. #define AD7793_COMM_WEN (1 << 7) /* Write Enable */
  40. #define AD7793_COMM_WRITE (0 << 6) /* Write Operation */
  41. #define AD7793_COMM_READ (1 << 6) /* Read Operation */
  42. #define AD7793_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
  43. #define AD7793_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */
  44. /* Status Register Bit Designations (AD7793_REG_STAT) */
  45. #define AD7793_STAT_RDY (1 << 7) /* Ready */
  46. #define AD7793_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */
  47. #define AD7793_STAT_CH3 (1 << 2) /* Channel 3 */
  48. #define AD7793_STAT_CH2 (1 << 1) /* Channel 2 */
  49. #define AD7793_STAT_CH1 (1 << 0) /* Channel 1 */
  50. /* Mode Register Bit Designations (AD7793_REG_MODE) */
  51. #define AD7793_MODE_SEL(x) (((x) & 0x7) << 13) /* Operation Mode Select */
  52. #define AD7793_MODE_SEL_MASK (0x7 << 13) /* Operation Mode Select mask */
  53. #define AD7793_MODE_CLKSRC(x) (((x) & 0x3) << 6) /* ADC Clock Source Select */
  54. #define AD7793_MODE_RATE(x) ((x) & 0xF) /* Filter Update Rate Select */
  55. #define AD7793_MODE_CONT 0 /* Continuous Conversion Mode */
  56. #define AD7793_MODE_SINGLE 1 /* Single Conversion Mode */
  57. #define AD7793_MODE_IDLE 2 /* Idle Mode */
  58. #define AD7793_MODE_PWRDN 3 /* Power-Down Mode */
  59. #define AD7793_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
  60. #define AD7793_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
  61. #define AD7793_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
  62. #define AD7793_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
  63. #define AD7793_CLK_INT 0 /* Internal 64 kHz Clock not
  64. * available at the CLK pin */
  65. #define AD7793_CLK_INT_CO 1 /* Internal 64 kHz Clock available
  66. * at the CLK pin */
  67. #define AD7793_CLK_EXT 2 /* External 64 kHz Clock */
  68. #define AD7793_CLK_EXT_DIV2 3 /* External Clock divided by 2 */
  69. /* Configuration Register Bit Designations (AD7793_REG_CONF) */
  70. #define AD7793_CONF_VBIAS(x) (((x) & 0x3) << 14) /* Bias Voltage
  71. * Generator Enable */
  72. #define AD7793_CONF_BO_EN (1 << 13) /* Burnout Current Enable */
  73. #define AD7793_CONF_UNIPOLAR (1 << 12) /* Unipolar/Bipolar Enable */
  74. #define AD7793_CONF_BOOST (1 << 11) /* Boost Enable */
  75. #define AD7793_CONF_GAIN(x) (((x) & 0x7) << 8) /* Gain Select */
  76. #define AD7793_CONF_REFSEL(x) ((x) << 6) /* INT/EXT Reference Select */
  77. #define AD7793_CONF_BUF (1 << 4) /* Buffered Mode Enable */
  78. #define AD7793_CONF_CHAN(x) ((x) & 0xf) /* Channel select */
  79. #define AD7793_CONF_CHAN_MASK 0xf /* Channel select mask */
  80. #define AD7793_CH_AIN1P_AIN1M 0 /* AIN1(+) - AIN1(-) */
  81. #define AD7793_CH_AIN2P_AIN2M 1 /* AIN2(+) - AIN2(-) */
  82. #define AD7793_CH_AIN3P_AIN3M 2 /* AIN3(+) - AIN3(-) */
  83. #define AD7793_CH_AIN1M_AIN1M 3 /* AIN1(-) - AIN1(-) */
  84. #define AD7793_CH_TEMP 6 /* Temp Sensor */
  85. #define AD7793_CH_AVDD_MONITOR 7 /* AVDD Monitor */
  86. #define AD7795_CH_AIN4P_AIN4M 4 /* AIN4(+) - AIN4(-) */
  87. #define AD7795_CH_AIN5P_AIN5M 5 /* AIN5(+) - AIN5(-) */
  88. #define AD7795_CH_AIN6P_AIN6M 6 /* AIN6(+) - AIN6(-) */
  89. #define AD7795_CH_AIN1M_AIN1M 8 /* AIN1(-) - AIN1(-) */
  90. /* ID Register Bit Designations (AD7793_REG_ID) */
  91. #define AD7785_ID 0x3
  92. #define AD7792_ID 0xA
  93. #define AD7793_ID 0xB
  94. #define AD7794_ID 0xF
  95. #define AD7795_ID 0xF
  96. #define AD7796_ID 0xA
  97. #define AD7797_ID 0xB
  98. #define AD7798_ID 0x8
  99. #define AD7799_ID 0x9
  100. #define AD7793_ID_MASK 0xF
  101. /* IO (Excitation Current Sources) Register Bit Designations (AD7793_REG_IO) */
  102. #define AD7793_IO_IEXC1_IOUT1_IEXC2_IOUT2 0 /* IEXC1 connect to IOUT1,
  103. * IEXC2 connect to IOUT2 */
  104. #define AD7793_IO_IEXC1_IOUT2_IEXC2_IOUT1 1 /* IEXC1 connect to IOUT2,
  105. * IEXC2 connect to IOUT1 */
  106. #define AD7793_IO_IEXC1_IEXC2_IOUT1 2 /* Both current sources
  107. * IEXC1,2 connect to IOUT1 */
  108. #define AD7793_IO_IEXC1_IEXC2_IOUT2 3 /* Both current sources
  109. * IEXC1,2 connect to IOUT2 */
  110. #define AD7793_IO_IXCEN_10uA (1 << 0) /* Excitation Current 10uA */
  111. #define AD7793_IO_IXCEN_210uA (2 << 0) /* Excitation Current 210uA */
  112. #define AD7793_IO_IXCEN_1mA (3 << 0) /* Excitation Current 1mA */
  113. /* NOTE:
  114. * The AD7792/AD7793 features a dual use data out ready DOUT/RDY output.
  115. * In order to avoid contentions on the SPI bus, it's therefore necessary
  116. * to use spi bus locking.
  117. *
  118. * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
  119. */
  120. #define AD7793_FLAG_HAS_CLKSEL BIT(0)
  121. #define AD7793_FLAG_HAS_REFSEL BIT(1)
  122. #define AD7793_FLAG_HAS_VBIAS BIT(2)
  123. #define AD7793_HAS_EXITATION_CURRENT BIT(3)
  124. #define AD7793_FLAG_HAS_GAIN BIT(4)
  125. #define AD7793_FLAG_HAS_BUFFER BIT(5)
  126. struct ad7793_chip_info {
  127. unsigned int id;
  128. const struct iio_chan_spec *channels;
  129. unsigned int num_channels;
  130. unsigned int flags;
  131. const struct iio_info *iio_info;
  132. const u16 *sample_freq_avail;
  133. };
  134. struct ad7793_state {
  135. const struct ad7793_chip_info *chip_info;
  136. struct regulator *reg;
  137. u16 int_vref_mv;
  138. u16 mode;
  139. u16 conf;
  140. u32 scale_avail[8][2];
  141. struct ad_sigma_delta sd;
  142. };
  143. enum ad7793_supported_device_ids {
  144. ID_AD7785,
  145. ID_AD7792,
  146. ID_AD7793,
  147. ID_AD7794,
  148. ID_AD7795,
  149. ID_AD7796,
  150. ID_AD7797,
  151. ID_AD7798,
  152. ID_AD7799,
  153. };
  154. static struct ad7793_state *ad_sigma_delta_to_ad7793(struct ad_sigma_delta *sd)
  155. {
  156. return container_of(sd, struct ad7793_state, sd);
  157. }
  158. static int ad7793_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
  159. {
  160. struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);
  161. st->conf &= ~AD7793_CONF_CHAN_MASK;
  162. st->conf |= AD7793_CONF_CHAN(channel);
  163. return ad_sd_write_reg(&st->sd, AD7793_REG_CONF, 2, st->conf);
  164. }
  165. static int ad7793_set_mode(struct ad_sigma_delta *sd,
  166. enum ad_sigma_delta_mode mode)
  167. {
  168. struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);
  169. st->mode &= ~AD7793_MODE_SEL_MASK;
  170. st->mode |= AD7793_MODE_SEL(mode);
  171. return ad_sd_write_reg(&st->sd, AD7793_REG_MODE, 2, st->mode);
  172. }
  173. static const struct ad_sigma_delta_info ad7793_sigma_delta_info = {
  174. .set_channel = ad7793_set_channel,
  175. .set_mode = ad7793_set_mode,
  176. .has_registers = true,
  177. .addr_shift = 3,
  178. .read_mask = BIT(6),
  179. .irq_flags = IRQF_TRIGGER_FALLING,
  180. };
  181. static const struct ad_sd_calib_data ad7793_calib_arr[6] = {
  182. {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN1P_AIN1M},
  183. {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN1P_AIN1M},
  184. {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN2P_AIN2M},
  185. {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN2P_AIN2M},
  186. {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN3P_AIN3M},
  187. {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN3P_AIN3M}
  188. };
  189. static int ad7793_calibrate_all(struct ad7793_state *st)
  190. {
  191. return ad_sd_calibrate_all(&st->sd, ad7793_calib_arr,
  192. ARRAY_SIZE(ad7793_calib_arr));
  193. }
  194. static int ad7793_check_platform_data(struct ad7793_state *st,
  195. const struct ad7793_platform_data *pdata)
  196. {
  197. if ((pdata->current_source_direction == AD7793_IEXEC1_IEXEC2_IOUT1 ||
  198. pdata->current_source_direction == AD7793_IEXEC1_IEXEC2_IOUT2) &&
  199. ((pdata->exitation_current != AD7793_IX_10uA) &&
  200. (pdata->exitation_current != AD7793_IX_210uA)))
  201. return -EINVAL;
  202. if (!(st->chip_info->flags & AD7793_FLAG_HAS_CLKSEL) &&
  203. pdata->clock_src != AD7793_CLK_SRC_INT)
  204. return -EINVAL;
  205. if (!(st->chip_info->flags & AD7793_FLAG_HAS_REFSEL) &&
  206. pdata->refsel != AD7793_REFSEL_REFIN1)
  207. return -EINVAL;
  208. if (!(st->chip_info->flags & AD7793_FLAG_HAS_VBIAS) &&
  209. pdata->bias_voltage != AD7793_BIAS_VOLTAGE_DISABLED)
  210. return -EINVAL;
  211. if (!(st->chip_info->flags & AD7793_HAS_EXITATION_CURRENT) &&
  212. pdata->exitation_current != AD7793_IX_DISABLED)
  213. return -EINVAL;
  214. return 0;
  215. }
  216. static int ad7793_setup(struct iio_dev *indio_dev,
  217. const struct ad7793_platform_data *pdata,
  218. unsigned int vref_mv)
  219. {
  220. struct ad7793_state *st = iio_priv(indio_dev);
  221. int i, ret;
  222. unsigned long long scale_uv;
  223. u32 id;
  224. ret = ad7793_check_platform_data(st, pdata);
  225. if (ret)
  226. return ret;
  227. /* reset the serial interface */
  228. ret = ad_sd_reset(&st->sd, 32);
  229. if (ret < 0)
  230. goto out;
  231. usleep_range(500, 2000); /* Wait for at least 500us */
  232. /* write/read test for device presence */
  233. ret = ad_sd_read_reg(&st->sd, AD7793_REG_ID, 1, &id);
  234. if (ret)
  235. goto out;
  236. id &= AD7793_ID_MASK;
  237. if (id != st->chip_info->id) {
  238. ret = -ENODEV;
  239. dev_err(&st->sd.spi->dev, "device ID query failed\n");
  240. goto out;
  241. }
  242. st->mode = AD7793_MODE_RATE(1);
  243. st->conf = 0;
  244. if (st->chip_info->flags & AD7793_FLAG_HAS_CLKSEL)
  245. st->mode |= AD7793_MODE_CLKSRC(pdata->clock_src);
  246. if (st->chip_info->flags & AD7793_FLAG_HAS_REFSEL)
  247. st->conf |= AD7793_CONF_REFSEL(pdata->refsel);
  248. if (st->chip_info->flags & AD7793_FLAG_HAS_VBIAS)
  249. st->conf |= AD7793_CONF_VBIAS(pdata->bias_voltage);
  250. if (pdata->buffered || !(st->chip_info->flags & AD7793_FLAG_HAS_BUFFER))
  251. st->conf |= AD7793_CONF_BUF;
  252. if (pdata->boost_enable &&
  253. (st->chip_info->flags & AD7793_FLAG_HAS_VBIAS))
  254. st->conf |= AD7793_CONF_BOOST;
  255. if (pdata->burnout_current)
  256. st->conf |= AD7793_CONF_BO_EN;
  257. if (pdata->unipolar)
  258. st->conf |= AD7793_CONF_UNIPOLAR;
  259. if (!(st->chip_info->flags & AD7793_FLAG_HAS_GAIN))
  260. st->conf |= AD7793_CONF_GAIN(7);
  261. ret = ad7793_set_mode(&st->sd, AD_SD_MODE_IDLE);
  262. if (ret)
  263. goto out;
  264. ret = ad7793_set_channel(&st->sd, 0);
  265. if (ret)
  266. goto out;
  267. if (st->chip_info->flags & AD7793_HAS_EXITATION_CURRENT) {
  268. ret = ad_sd_write_reg(&st->sd, AD7793_REG_IO, 1,
  269. pdata->exitation_current |
  270. (pdata->current_source_direction << 2));
  271. if (ret)
  272. goto out;
  273. }
  274. ret = ad7793_calibrate_all(st);
  275. if (ret)
  276. goto out;
  277. /* Populate available ADC input ranges */
  278. for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
  279. scale_uv = ((u64)vref_mv * 100000000)
  280. >> (st->chip_info->channels[0].scan_type.realbits -
  281. (!!(st->conf & AD7793_CONF_UNIPOLAR) ? 0 : 1));
  282. scale_uv >>= i;
  283. st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
  284. st->scale_avail[i][0] = scale_uv;
  285. }
  286. return 0;
  287. out:
  288. dev_err(&st->sd.spi->dev, "setup failed\n");
  289. return ret;
  290. }
  291. static const u16 ad7793_sample_freq_avail[16] = {0, 470, 242, 123, 62, 50, 39,
  292. 33, 19, 17, 16, 12, 10, 8, 6, 4};
  293. static const u16 ad7797_sample_freq_avail[16] = {0, 0, 0, 123, 62, 50, 0,
  294. 33, 0, 17, 16, 12, 10, 8, 6, 4};
  295. static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
  296. "470 242 123 62 50 39 33 19 17 16 12 10 8 6 4");
  297. static IIO_CONST_ATTR_NAMED(sampling_frequency_available_ad7797,
  298. sampling_frequency_available, "123 62 50 33 17 16 12 10 8 6 4");
  299. static int ad7793_read_avail(struct iio_dev *indio_dev,
  300. struct iio_chan_spec const *chan,
  301. const int **vals, int *type, int *length,
  302. long mask)
  303. {
  304. struct ad7793_state *st = iio_priv(indio_dev);
  305. switch (mask) {
  306. case IIO_CHAN_INFO_SCALE:
  307. *vals = (int *)st->scale_avail;
  308. *type = IIO_VAL_INT_PLUS_NANO;
  309. /* Values are stored in a 2D matrix */
  310. *length = ARRAY_SIZE(st->scale_avail) * 2;
  311. return IIO_AVAIL_LIST;
  312. default:
  313. return -EINVAL;
  314. }
  315. }
  316. static struct attribute *ad7793_attributes[] = {
  317. &iio_const_attr_sampling_frequency_available.dev_attr.attr,
  318. NULL
  319. };
  320. static const struct attribute_group ad7793_attribute_group = {
  321. .attrs = ad7793_attributes,
  322. };
  323. static struct attribute *ad7797_attributes[] = {
  324. &iio_const_attr_sampling_frequency_available_ad7797.dev_attr.attr,
  325. NULL
  326. };
  327. static const struct attribute_group ad7797_attribute_group = {
  328. .attrs = ad7797_attributes,
  329. };
  330. static int ad7793_read_raw(struct iio_dev *indio_dev,
  331. struct iio_chan_spec const *chan,
  332. int *val,
  333. int *val2,
  334. long m)
  335. {
  336. struct ad7793_state *st = iio_priv(indio_dev);
  337. int ret;
  338. unsigned long long scale_uv;
  339. bool unipolar = !!(st->conf & AD7793_CONF_UNIPOLAR);
  340. switch (m) {
  341. case IIO_CHAN_INFO_RAW:
  342. ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
  343. if (ret < 0)
  344. return ret;
  345. return IIO_VAL_INT;
  346. case IIO_CHAN_INFO_SCALE:
  347. switch (chan->type) {
  348. case IIO_VOLTAGE:
  349. if (chan->differential) {
  350. *val = st->
  351. scale_avail[(st->conf >> 8) & 0x7][0];
  352. *val2 = st->
  353. scale_avail[(st->conf >> 8) & 0x7][1];
  354. return IIO_VAL_INT_PLUS_NANO;
  355. }
  356. /* 1170mV / 2^23 * 6 */
  357. scale_uv = (1170ULL * 1000000000ULL * 6ULL);
  358. break;
  359. case IIO_TEMP:
  360. /* 1170mV / 0.81 mV/C / 2^23 */
  361. scale_uv = 1444444444444444ULL;
  362. break;
  363. default:
  364. return -EINVAL;
  365. }
  366. scale_uv >>= (chan->scan_type.realbits - (unipolar ? 0 : 1));
  367. *val = 0;
  368. *val2 = scale_uv;
  369. return IIO_VAL_INT_PLUS_NANO;
  370. case IIO_CHAN_INFO_OFFSET:
  371. if (!unipolar)
  372. *val = -(1 << (chan->scan_type.realbits - 1));
  373. else
  374. *val = 0;
  375. /* Kelvin to Celsius */
  376. if (chan->type == IIO_TEMP) {
  377. unsigned long long offset;
  378. unsigned int shift;
  379. shift = chan->scan_type.realbits - (unipolar ? 0 : 1);
  380. offset = 273ULL << shift;
  381. do_div(offset, 1444);
  382. *val -= offset;
  383. }
  384. return IIO_VAL_INT;
  385. case IIO_CHAN_INFO_SAMP_FREQ:
  386. *val = st->chip_info
  387. ->sample_freq_avail[AD7793_MODE_RATE(st->mode)];
  388. return IIO_VAL_INT;
  389. }
  390. return -EINVAL;
  391. }
  392. static int ad7793_write_raw(struct iio_dev *indio_dev,
  393. struct iio_chan_spec const *chan,
  394. int val,
  395. int val2,
  396. long mask)
  397. {
  398. struct ad7793_state *st = iio_priv(indio_dev);
  399. int ret, i;
  400. unsigned int tmp;
  401. ret = iio_device_claim_direct_mode(indio_dev);
  402. if (ret)
  403. return ret;
  404. switch (mask) {
  405. case IIO_CHAN_INFO_SCALE:
  406. ret = -EINVAL;
  407. for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
  408. if (val2 == st->scale_avail[i][1]) {
  409. ret = 0;
  410. tmp = st->conf;
  411. st->conf &= ~AD7793_CONF_GAIN(-1);
  412. st->conf |= AD7793_CONF_GAIN(i);
  413. if (tmp == st->conf)
  414. break;
  415. ad_sd_write_reg(&st->sd, AD7793_REG_CONF,
  416. sizeof(st->conf), st->conf);
  417. ad7793_calibrate_all(st);
  418. break;
  419. }
  420. break;
  421. case IIO_CHAN_INFO_SAMP_FREQ:
  422. if (!val) {
  423. ret = -EINVAL;
  424. break;
  425. }
  426. for (i = 0; i < 16; i++)
  427. if (val == st->chip_info->sample_freq_avail[i])
  428. break;
  429. if (i == 16) {
  430. ret = -EINVAL;
  431. break;
  432. }
  433. st->mode &= ~AD7793_MODE_RATE(-1);
  434. st->mode |= AD7793_MODE_RATE(i);
  435. ad_sd_write_reg(&st->sd, AD7793_REG_MODE, sizeof(st->mode),
  436. st->mode);
  437. break;
  438. default:
  439. ret = -EINVAL;
  440. }
  441. iio_device_release_direct_mode(indio_dev);
  442. return ret;
  443. }
  444. static int ad7793_write_raw_get_fmt(struct iio_dev *indio_dev,
  445. struct iio_chan_spec const *chan,
  446. long mask)
  447. {
  448. return IIO_VAL_INT_PLUS_NANO;
  449. }
  450. static const struct iio_info ad7793_info = {
  451. .read_raw = &ad7793_read_raw,
  452. .write_raw = &ad7793_write_raw,
  453. .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
  454. .read_avail = ad7793_read_avail,
  455. .attrs = &ad7793_attribute_group,
  456. .validate_trigger = ad_sd_validate_trigger,
  457. };
  458. static const struct iio_info ad7797_info = {
  459. .read_raw = &ad7793_read_raw,
  460. .write_raw = &ad7793_write_raw,
  461. .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
  462. .attrs = &ad7797_attribute_group,
  463. .validate_trigger = ad_sd_validate_trigger,
  464. };
  465. #define __AD7793_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
  466. _storagebits, _shift, _extend_name, _type, _mask_type_av, _mask_all) \
  467. { \
  468. .type = (_type), \
  469. .differential = (_channel2 == -1 ? 0 : 1), \
  470. .indexed = 1, \
  471. .channel = (_channel1), \
  472. .channel2 = (_channel2), \
  473. .address = (_address), \
  474. .extend_name = (_extend_name), \
  475. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  476. BIT(IIO_CHAN_INFO_OFFSET), \
  477. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  478. .info_mask_shared_by_type_available = (_mask_type_av), \
  479. .info_mask_shared_by_all = _mask_all, \
  480. .scan_index = (_si), \
  481. .scan_type = { \
  482. .sign = 'u', \
  483. .realbits = (_bits), \
  484. .storagebits = (_storagebits), \
  485. .shift = (_shift), \
  486. .endianness = IIO_BE, \
  487. }, \
  488. }
  489. #define AD7793_DIFF_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
  490. _storagebits, _shift) \
  491. __AD7793_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
  492. _storagebits, _shift, NULL, IIO_VOLTAGE, \
  493. BIT(IIO_CHAN_INFO_SCALE), \
  494. BIT(IIO_CHAN_INFO_SAMP_FREQ))
  495. #define AD7793_SHORTED_CHANNEL(_si, _channel, _address, _bits, \
  496. _storagebits, _shift) \
  497. __AD7793_CHANNEL(_si, _channel, _channel, _address, _bits, \
  498. _storagebits, _shift, "shorted", IIO_VOLTAGE, \
  499. BIT(IIO_CHAN_INFO_SCALE), \
  500. BIT(IIO_CHAN_INFO_SAMP_FREQ))
  501. #define AD7793_TEMP_CHANNEL(_si, _address, _bits, _storagebits, _shift) \
  502. __AD7793_CHANNEL(_si, 0, -1, _address, _bits, \
  503. _storagebits, _shift, NULL, IIO_TEMP, \
  504. 0, \
  505. BIT(IIO_CHAN_INFO_SAMP_FREQ))
  506. #define AD7793_SUPPLY_CHANNEL(_si, _channel, _address, _bits, _storagebits, \
  507. _shift) \
  508. __AD7793_CHANNEL(_si, _channel, -1, _address, _bits, \
  509. _storagebits, _shift, "supply", IIO_VOLTAGE, \
  510. 0, \
  511. BIT(IIO_CHAN_INFO_SAMP_FREQ))
  512. #define AD7797_DIFF_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
  513. _storagebits, _shift) \
  514. __AD7793_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
  515. _storagebits, _shift, NULL, IIO_VOLTAGE, \
  516. 0, \
  517. BIT(IIO_CHAN_INFO_SAMP_FREQ))
  518. #define AD7797_SHORTED_CHANNEL(_si, _channel, _address, _bits, \
  519. _storagebits, _shift) \
  520. __AD7793_CHANNEL(_si, _channel, _channel, _address, _bits, \
  521. _storagebits, _shift, "shorted", IIO_VOLTAGE, \
  522. 0, \
  523. BIT(IIO_CHAN_INFO_SAMP_FREQ))
  524. #define DECLARE_AD7793_CHANNELS(_name, _b, _sb, _s) \
  525. const struct iio_chan_spec _name##_channels[] = { \
  526. AD7793_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), (_s)), \
  527. AD7793_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), (_s)), \
  528. AD7793_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), (_s)), \
  529. AD7793_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), (_s)), \
  530. AD7793_TEMP_CHANNEL(4, AD7793_CH_TEMP, (_b), (_sb), (_s)), \
  531. AD7793_SUPPLY_CHANNEL(5, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), (_s)), \
  532. IIO_CHAN_SOFT_TIMESTAMP(6), \
  533. }
  534. #define DECLARE_AD7795_CHANNELS(_name, _b, _sb) \
  535. const struct iio_chan_spec _name##_channels[] = { \
  536. AD7793_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
  537. AD7793_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \
  538. AD7793_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \
  539. AD7793_DIFF_CHANNEL(3, 3, 3, AD7795_CH_AIN4P_AIN4M, (_b), (_sb), 0), \
  540. AD7793_DIFF_CHANNEL(4, 4, 4, AD7795_CH_AIN5P_AIN5M, (_b), (_sb), 0), \
  541. AD7793_DIFF_CHANNEL(5, 5, 5, AD7795_CH_AIN6P_AIN6M, (_b), (_sb), 0), \
  542. AD7793_SHORTED_CHANNEL(6, 0, AD7795_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
  543. AD7793_TEMP_CHANNEL(7, AD7793_CH_TEMP, (_b), (_sb), 0), \
  544. AD7793_SUPPLY_CHANNEL(8, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
  545. IIO_CHAN_SOFT_TIMESTAMP(9), \
  546. }
  547. #define DECLARE_AD7797_CHANNELS(_name, _b, _sb) \
  548. const struct iio_chan_spec _name##_channels[] = { \
  549. AD7797_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
  550. AD7797_SHORTED_CHANNEL(1, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
  551. AD7793_TEMP_CHANNEL(2, AD7793_CH_TEMP, (_b), (_sb), 0), \
  552. AD7793_SUPPLY_CHANNEL(3, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
  553. IIO_CHAN_SOFT_TIMESTAMP(4), \
  554. }
  555. #define DECLARE_AD7799_CHANNELS(_name, _b, _sb) \
  556. const struct iio_chan_spec _name##_channels[] = { \
  557. AD7793_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
  558. AD7793_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \
  559. AD7793_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \
  560. AD7793_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
  561. AD7793_SUPPLY_CHANNEL(4, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
  562. IIO_CHAN_SOFT_TIMESTAMP(5), \
  563. }
  564. static DECLARE_AD7793_CHANNELS(ad7785, 20, 32, 4);
  565. static DECLARE_AD7793_CHANNELS(ad7792, 16, 32, 0);
  566. static DECLARE_AD7793_CHANNELS(ad7793, 24, 32, 0);
  567. static DECLARE_AD7795_CHANNELS(ad7794, 16, 32);
  568. static DECLARE_AD7795_CHANNELS(ad7795, 24, 32);
  569. static DECLARE_AD7797_CHANNELS(ad7796, 16, 16);
  570. static DECLARE_AD7797_CHANNELS(ad7797, 24, 32);
  571. static DECLARE_AD7799_CHANNELS(ad7798, 16, 16);
  572. static DECLARE_AD7799_CHANNELS(ad7799, 24, 32);
  573. static const struct ad7793_chip_info ad7793_chip_info_tbl[] = {
  574. [ID_AD7785] = {
  575. .id = AD7785_ID,
  576. .channels = ad7785_channels,
  577. .num_channels = ARRAY_SIZE(ad7785_channels),
  578. .iio_info = &ad7793_info,
  579. .sample_freq_avail = ad7793_sample_freq_avail,
  580. .flags = AD7793_FLAG_HAS_CLKSEL |
  581. AD7793_FLAG_HAS_REFSEL |
  582. AD7793_FLAG_HAS_VBIAS |
  583. AD7793_HAS_EXITATION_CURRENT |
  584. AD7793_FLAG_HAS_GAIN |
  585. AD7793_FLAG_HAS_BUFFER,
  586. },
  587. [ID_AD7792] = {
  588. .id = AD7792_ID,
  589. .channels = ad7792_channels,
  590. .num_channels = ARRAY_SIZE(ad7792_channels),
  591. .iio_info = &ad7793_info,
  592. .sample_freq_avail = ad7793_sample_freq_avail,
  593. .flags = AD7793_FLAG_HAS_CLKSEL |
  594. AD7793_FLAG_HAS_REFSEL |
  595. AD7793_FLAG_HAS_VBIAS |
  596. AD7793_HAS_EXITATION_CURRENT |
  597. AD7793_FLAG_HAS_GAIN |
  598. AD7793_FLAG_HAS_BUFFER,
  599. },
  600. [ID_AD7793] = {
  601. .id = AD7793_ID,
  602. .channels = ad7793_channels,
  603. .num_channels = ARRAY_SIZE(ad7793_channels),
  604. .iio_info = &ad7793_info,
  605. .sample_freq_avail = ad7793_sample_freq_avail,
  606. .flags = AD7793_FLAG_HAS_CLKSEL |
  607. AD7793_FLAG_HAS_REFSEL |
  608. AD7793_FLAG_HAS_VBIAS |
  609. AD7793_HAS_EXITATION_CURRENT |
  610. AD7793_FLAG_HAS_GAIN |
  611. AD7793_FLAG_HAS_BUFFER,
  612. },
  613. [ID_AD7794] = {
  614. .id = AD7794_ID,
  615. .channels = ad7794_channels,
  616. .num_channels = ARRAY_SIZE(ad7794_channels),
  617. .iio_info = &ad7793_info,
  618. .sample_freq_avail = ad7793_sample_freq_avail,
  619. .flags = AD7793_FLAG_HAS_CLKSEL |
  620. AD7793_FLAG_HAS_REFSEL |
  621. AD7793_FLAG_HAS_VBIAS |
  622. AD7793_HAS_EXITATION_CURRENT |
  623. AD7793_FLAG_HAS_GAIN |
  624. AD7793_FLAG_HAS_BUFFER,
  625. },
  626. [ID_AD7795] = {
  627. .id = AD7795_ID,
  628. .channels = ad7795_channels,
  629. .num_channels = ARRAY_SIZE(ad7795_channels),
  630. .iio_info = &ad7793_info,
  631. .sample_freq_avail = ad7793_sample_freq_avail,
  632. .flags = AD7793_FLAG_HAS_CLKSEL |
  633. AD7793_FLAG_HAS_REFSEL |
  634. AD7793_FLAG_HAS_VBIAS |
  635. AD7793_HAS_EXITATION_CURRENT |
  636. AD7793_FLAG_HAS_GAIN |
  637. AD7793_FLAG_HAS_BUFFER,
  638. },
  639. [ID_AD7796] = {
  640. .id = AD7796_ID,
  641. .channels = ad7796_channels,
  642. .num_channels = ARRAY_SIZE(ad7796_channels),
  643. .iio_info = &ad7797_info,
  644. .sample_freq_avail = ad7797_sample_freq_avail,
  645. .flags = AD7793_FLAG_HAS_CLKSEL,
  646. },
  647. [ID_AD7797] = {
  648. .id = AD7797_ID,
  649. .channels = ad7797_channels,
  650. .num_channels = ARRAY_SIZE(ad7797_channels),
  651. .iio_info = &ad7797_info,
  652. .sample_freq_avail = ad7797_sample_freq_avail,
  653. .flags = AD7793_FLAG_HAS_CLKSEL,
  654. },
  655. [ID_AD7798] = {
  656. .id = AD7798_ID,
  657. .channels = ad7798_channels,
  658. .num_channels = ARRAY_SIZE(ad7798_channels),
  659. .iio_info = &ad7793_info,
  660. .sample_freq_avail = ad7793_sample_freq_avail,
  661. .flags = AD7793_FLAG_HAS_GAIN |
  662. AD7793_FLAG_HAS_BUFFER,
  663. },
  664. [ID_AD7799] = {
  665. .id = AD7799_ID,
  666. .channels = ad7799_channels,
  667. .num_channels = ARRAY_SIZE(ad7799_channels),
  668. .iio_info = &ad7793_info,
  669. .sample_freq_avail = ad7793_sample_freq_avail,
  670. .flags = AD7793_FLAG_HAS_GAIN |
  671. AD7793_FLAG_HAS_BUFFER,
  672. },
  673. };
  674. static int ad7793_probe(struct spi_device *spi)
  675. {
  676. const struct ad7793_platform_data *pdata = spi->dev.platform_data;
  677. struct ad7793_state *st;
  678. struct iio_dev *indio_dev;
  679. int ret, vref_mv = 0;
  680. if (!pdata) {
  681. dev_err(&spi->dev, "no platform data?\n");
  682. return -ENODEV;
  683. }
  684. if (!spi->irq) {
  685. dev_err(&spi->dev, "no IRQ?\n");
  686. return -ENODEV;
  687. }
  688. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  689. if (indio_dev == NULL)
  690. return -ENOMEM;
  691. st = iio_priv(indio_dev);
  692. ad_sd_init(&st->sd, indio_dev, spi, &ad7793_sigma_delta_info);
  693. if (pdata->refsel != AD7793_REFSEL_INTERNAL) {
  694. st->reg = devm_regulator_get(&spi->dev, "refin");
  695. if (IS_ERR(st->reg))
  696. return PTR_ERR(st->reg);
  697. ret = regulator_enable(st->reg);
  698. if (ret)
  699. return ret;
  700. vref_mv = regulator_get_voltage(st->reg);
  701. if (vref_mv < 0) {
  702. ret = vref_mv;
  703. goto error_disable_reg;
  704. }
  705. vref_mv /= 1000;
  706. } else {
  707. vref_mv = 1170; /* Build-in ref */
  708. }
  709. st->chip_info =
  710. &ad7793_chip_info_tbl[spi_get_device_id(spi)->driver_data];
  711. spi_set_drvdata(spi, indio_dev);
  712. indio_dev->name = spi_get_device_id(spi)->name;
  713. indio_dev->modes = INDIO_DIRECT_MODE;
  714. indio_dev->channels = st->chip_info->channels;
  715. indio_dev->num_channels = st->chip_info->num_channels;
  716. indio_dev->info = st->chip_info->iio_info;
  717. ret = ad_sd_setup_buffer_and_trigger(indio_dev);
  718. if (ret)
  719. goto error_disable_reg;
  720. ret = ad7793_setup(indio_dev, pdata, vref_mv);
  721. if (ret)
  722. goto error_remove_trigger;
  723. ret = iio_device_register(indio_dev);
  724. if (ret)
  725. goto error_remove_trigger;
  726. return 0;
  727. error_remove_trigger:
  728. ad_sd_cleanup_buffer_and_trigger(indio_dev);
  729. error_disable_reg:
  730. if (pdata->refsel != AD7793_REFSEL_INTERNAL)
  731. regulator_disable(st->reg);
  732. return ret;
  733. }
  734. static int ad7793_remove(struct spi_device *spi)
  735. {
  736. const struct ad7793_platform_data *pdata = spi->dev.platform_data;
  737. struct iio_dev *indio_dev = spi_get_drvdata(spi);
  738. struct ad7793_state *st = iio_priv(indio_dev);
  739. iio_device_unregister(indio_dev);
  740. ad_sd_cleanup_buffer_and_trigger(indio_dev);
  741. if (pdata->refsel != AD7793_REFSEL_INTERNAL)
  742. regulator_disable(st->reg);
  743. return 0;
  744. }
  745. static const struct spi_device_id ad7793_id[] = {
  746. {"ad7785", ID_AD7785},
  747. {"ad7792", ID_AD7792},
  748. {"ad7793", ID_AD7793},
  749. {"ad7794", ID_AD7794},
  750. {"ad7795", ID_AD7795},
  751. {"ad7796", ID_AD7796},
  752. {"ad7797", ID_AD7797},
  753. {"ad7798", ID_AD7798},
  754. {"ad7799", ID_AD7799},
  755. {}
  756. };
  757. MODULE_DEVICE_TABLE(spi, ad7793_id);
  758. static struct spi_driver ad7793_driver = {
  759. .driver = {
  760. .name = "ad7793",
  761. },
  762. .probe = ad7793_probe,
  763. .remove = ad7793_remove,
  764. .id_table = ad7793_id,
  765. };
  766. module_spi_driver(ad7793_driver);
  767. MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
  768. MODULE_DESCRIPTION("Analog Devices AD7793 and similar ADCs");
  769. MODULE_LICENSE("GPL v2");