ad7768-1.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Analog Devices AD7768-1 SPI ADC driver
  4. *
  5. * Copyright 2017 Analog Devices Inc.
  6. */
  7. #include <linux/bitfield.h>
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/device.h>
  11. #include <linux/err.h>
  12. #include <linux/gpio/consumer.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/regulator/consumer.h>
  16. #include <linux/sysfs.h>
  17. #include <linux/spi/spi.h>
  18. #include <linux/iio/buffer.h>
  19. #include <linux/iio/iio.h>
  20. #include <linux/iio/sysfs.h>
  21. #include <linux/iio/trigger.h>
  22. #include <linux/iio/triggered_buffer.h>
  23. #include <linux/iio/trigger_consumer.h>
  24. /* AD7768 registers definition */
  25. #define AD7768_REG_CHIP_TYPE 0x3
  26. #define AD7768_REG_PROD_ID_L 0x4
  27. #define AD7768_REG_PROD_ID_H 0x5
  28. #define AD7768_REG_CHIP_GRADE 0x6
  29. #define AD7768_REG_SCRATCH_PAD 0x0A
  30. #define AD7768_REG_VENDOR_L 0x0C
  31. #define AD7768_REG_VENDOR_H 0x0D
  32. #define AD7768_REG_INTERFACE_FORMAT 0x14
  33. #define AD7768_REG_POWER_CLOCK 0x15
  34. #define AD7768_REG_ANALOG 0x16
  35. #define AD7768_REG_ANALOG2 0x17
  36. #define AD7768_REG_CONVERSION 0x18
  37. #define AD7768_REG_DIGITAL_FILTER 0x19
  38. #define AD7768_REG_SINC3_DEC_RATE_MSB 0x1A
  39. #define AD7768_REG_SINC3_DEC_RATE_LSB 0x1B
  40. #define AD7768_REG_DUTY_CYCLE_RATIO 0x1C
  41. #define AD7768_REG_SYNC_RESET 0x1D
  42. #define AD7768_REG_GPIO_CONTROL 0x1E
  43. #define AD7768_REG_GPIO_WRITE 0x1F
  44. #define AD7768_REG_GPIO_READ 0x20
  45. #define AD7768_REG_OFFSET_HI 0x21
  46. #define AD7768_REG_OFFSET_MID 0x22
  47. #define AD7768_REG_OFFSET_LO 0x23
  48. #define AD7768_REG_GAIN_HI 0x24
  49. #define AD7768_REG_GAIN_MID 0x25
  50. #define AD7768_REG_GAIN_LO 0x26
  51. #define AD7768_REG_SPI_DIAG_ENABLE 0x28
  52. #define AD7768_REG_ADC_DIAG_ENABLE 0x29
  53. #define AD7768_REG_DIG_DIAG_ENABLE 0x2A
  54. #define AD7768_REG_ADC_DATA 0x2C
  55. #define AD7768_REG_MASTER_STATUS 0x2D
  56. #define AD7768_REG_SPI_DIAG_STATUS 0x2E
  57. #define AD7768_REG_ADC_DIAG_STATUS 0x2F
  58. #define AD7768_REG_DIG_DIAG_STATUS 0x30
  59. #define AD7768_REG_MCLK_COUNTER 0x31
  60. /* AD7768_REG_POWER_CLOCK */
  61. #define AD7768_PWR_MCLK_DIV_MSK GENMASK(5, 4)
  62. #define AD7768_PWR_MCLK_DIV(x) FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x)
  63. #define AD7768_PWR_PWRMODE_MSK GENMASK(1, 0)
  64. #define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x)
  65. /* AD7768_REG_DIGITAL_FILTER */
  66. #define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4)
  67. #define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x)
  68. #define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0)
  69. #define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x)
  70. /* AD7768_REG_CONVERSION */
  71. #define AD7768_CONV_MODE_MSK GENMASK(2, 0)
  72. #define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x)
  73. #define AD7768_RD_FLAG_MSK(x) (BIT(6) | ((x) & 0x3F))
  74. #define AD7768_WR_FLAG_MSK(x) ((x) & 0x3F)
  75. enum ad7768_conv_mode {
  76. AD7768_CONTINUOUS,
  77. AD7768_ONE_SHOT,
  78. AD7768_SINGLE,
  79. AD7768_PERIODIC,
  80. AD7768_STANDBY
  81. };
  82. enum ad7768_pwrmode {
  83. AD7768_ECO_MODE = 0,
  84. AD7768_MED_MODE = 2,
  85. AD7768_FAST_MODE = 3
  86. };
  87. enum ad7768_mclk_div {
  88. AD7768_MCLK_DIV_16,
  89. AD7768_MCLK_DIV_8,
  90. AD7768_MCLK_DIV_4,
  91. AD7768_MCLK_DIV_2
  92. };
  93. enum ad7768_dec_rate {
  94. AD7768_DEC_RATE_32 = 0,
  95. AD7768_DEC_RATE_64 = 1,
  96. AD7768_DEC_RATE_128 = 2,
  97. AD7768_DEC_RATE_256 = 3,
  98. AD7768_DEC_RATE_512 = 4,
  99. AD7768_DEC_RATE_1024 = 5,
  100. AD7768_DEC_RATE_8 = 9,
  101. AD7768_DEC_RATE_16 = 10
  102. };
  103. struct ad7768_clk_configuration {
  104. enum ad7768_mclk_div mclk_div;
  105. enum ad7768_dec_rate dec_rate;
  106. unsigned int clk_div;
  107. enum ad7768_pwrmode pwrmode;
  108. };
  109. static const struct ad7768_clk_configuration ad7768_clk_config[] = {
  110. { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE },
  111. { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE },
  112. { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE },
  113. { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE },
  114. { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE },
  115. { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE },
  116. { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE },
  117. { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE },
  118. { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE },
  119. { AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE },
  120. { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE },
  121. };
  122. static const struct iio_chan_spec ad7768_channels[] = {
  123. {
  124. .type = IIO_VOLTAGE,
  125. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
  126. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
  127. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
  128. .indexed = 1,
  129. .channel = 0,
  130. .scan_index = 0,
  131. .scan_type = {
  132. .sign = 'u',
  133. .realbits = 24,
  134. .storagebits = 32,
  135. .shift = 8,
  136. .endianness = IIO_BE,
  137. },
  138. },
  139. };
  140. struct ad7768_state {
  141. struct spi_device *spi;
  142. struct regulator *vref;
  143. struct mutex lock;
  144. struct clk *mclk;
  145. unsigned int mclk_freq;
  146. unsigned int samp_freq;
  147. struct completion completion;
  148. struct iio_trigger *trig;
  149. struct gpio_desc *gpio_sync_in;
  150. /*
  151. * DMA (thus cache coherency maintenance) requires the
  152. * transfer buffers to live in their own cache lines.
  153. */
  154. union {
  155. struct {
  156. __be32 chan;
  157. s64 timestamp;
  158. } scan;
  159. __be32 d32;
  160. u8 d8[2];
  161. } data ____cacheline_aligned;
  162. };
  163. static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr,
  164. unsigned int len)
  165. {
  166. unsigned int shift;
  167. int ret;
  168. shift = 32 - (8 * len);
  169. st->data.d8[0] = AD7768_RD_FLAG_MSK(addr);
  170. ret = spi_write_then_read(st->spi, st->data.d8, 1,
  171. &st->data.d32, len);
  172. if (ret < 0)
  173. return ret;
  174. return (be32_to_cpu(st->data.d32) >> shift);
  175. }
  176. static int ad7768_spi_reg_write(struct ad7768_state *st,
  177. unsigned int addr,
  178. unsigned int val)
  179. {
  180. st->data.d8[0] = AD7768_WR_FLAG_MSK(addr);
  181. st->data.d8[1] = val & 0xFF;
  182. return spi_write(st->spi, st->data.d8, 2);
  183. }
  184. static int ad7768_set_mode(struct ad7768_state *st,
  185. enum ad7768_conv_mode mode)
  186. {
  187. int regval;
  188. regval = ad7768_spi_reg_read(st, AD7768_REG_CONVERSION, 1);
  189. if (regval < 0)
  190. return regval;
  191. regval &= ~AD7768_CONV_MODE_MSK;
  192. regval |= AD7768_CONV_MODE(mode);
  193. return ad7768_spi_reg_write(st, AD7768_REG_CONVERSION, regval);
  194. }
  195. static int ad7768_scan_direct(struct iio_dev *indio_dev)
  196. {
  197. struct ad7768_state *st = iio_priv(indio_dev);
  198. int readval, ret;
  199. reinit_completion(&st->completion);
  200. ret = ad7768_set_mode(st, AD7768_ONE_SHOT);
  201. if (ret < 0)
  202. return ret;
  203. ret = wait_for_completion_timeout(&st->completion,
  204. msecs_to_jiffies(1000));
  205. if (!ret)
  206. return -ETIMEDOUT;
  207. readval = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3);
  208. if (readval < 0)
  209. return readval;
  210. /*
  211. * Any SPI configuration of the AD7768-1 can only be
  212. * performed in continuous conversion mode.
  213. */
  214. ret = ad7768_set_mode(st, AD7768_CONTINUOUS);
  215. if (ret < 0)
  216. return ret;
  217. return readval;
  218. }
  219. static int ad7768_reg_access(struct iio_dev *indio_dev,
  220. unsigned int reg,
  221. unsigned int writeval,
  222. unsigned int *readval)
  223. {
  224. struct ad7768_state *st = iio_priv(indio_dev);
  225. int ret;
  226. mutex_lock(&st->lock);
  227. if (readval) {
  228. ret = ad7768_spi_reg_read(st, reg, 1);
  229. if (ret < 0)
  230. goto err_unlock;
  231. *readval = ret;
  232. ret = 0;
  233. } else {
  234. ret = ad7768_spi_reg_write(st, reg, writeval);
  235. }
  236. err_unlock:
  237. mutex_unlock(&st->lock);
  238. return ret;
  239. }
  240. static int ad7768_set_dig_fil(struct ad7768_state *st,
  241. enum ad7768_dec_rate dec_rate)
  242. {
  243. unsigned int mode;
  244. int ret;
  245. if (dec_rate == AD7768_DEC_RATE_8 || dec_rate == AD7768_DEC_RATE_16)
  246. mode = AD7768_DIG_FIL_FIL(dec_rate);
  247. else
  248. mode = AD7768_DIG_FIL_DEC_RATE(dec_rate);
  249. ret = ad7768_spi_reg_write(st, AD7768_REG_DIGITAL_FILTER, mode);
  250. if (ret < 0)
  251. return ret;
  252. /* A sync-in pulse is required every time the filter dec rate changes */
  253. gpiod_set_value(st->gpio_sync_in, 1);
  254. gpiod_set_value(st->gpio_sync_in, 0);
  255. return 0;
  256. }
  257. static int ad7768_set_freq(struct ad7768_state *st,
  258. unsigned int freq)
  259. {
  260. unsigned int diff_new, diff_old, pwr_mode, i, idx;
  261. int res, ret;
  262. diff_old = U32_MAX;
  263. idx = 0;
  264. res = DIV_ROUND_CLOSEST(st->mclk_freq, freq);
  265. /* Find the closest match for the desired sampling frequency */
  266. for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
  267. diff_new = abs(res - ad7768_clk_config[i].clk_div);
  268. if (diff_new < diff_old) {
  269. diff_old = diff_new;
  270. idx = i;
  271. }
  272. }
  273. /*
  274. * Set both the mclk_div and pwrmode with a single write to the
  275. * POWER_CLOCK register
  276. */
  277. pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) |
  278. AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode);
  279. ret = ad7768_spi_reg_write(st, AD7768_REG_POWER_CLOCK, pwr_mode);
  280. if (ret < 0)
  281. return ret;
  282. ret = ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate);
  283. if (ret < 0)
  284. return ret;
  285. st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq,
  286. ad7768_clk_config[idx].clk_div);
  287. return 0;
  288. }
  289. static ssize_t ad7768_sampling_freq_avail(struct device *dev,
  290. struct device_attribute *attr,
  291. char *buf)
  292. {
  293. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  294. struct ad7768_state *st = iio_priv(indio_dev);
  295. unsigned int freq;
  296. int i, len = 0;
  297. for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
  298. freq = DIV_ROUND_CLOSEST(st->mclk_freq,
  299. ad7768_clk_config[i].clk_div);
  300. len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", freq);
  301. }
  302. buf[len - 1] = '\n';
  303. return len;
  304. }
  305. static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(ad7768_sampling_freq_avail);
  306. static int ad7768_read_raw(struct iio_dev *indio_dev,
  307. struct iio_chan_spec const *chan,
  308. int *val, int *val2, long info)
  309. {
  310. struct ad7768_state *st = iio_priv(indio_dev);
  311. int scale_uv, ret;
  312. switch (info) {
  313. case IIO_CHAN_INFO_RAW:
  314. ret = iio_device_claim_direct_mode(indio_dev);
  315. if (ret)
  316. return ret;
  317. ret = ad7768_scan_direct(indio_dev);
  318. if (ret >= 0)
  319. *val = ret;
  320. iio_device_release_direct_mode(indio_dev);
  321. if (ret < 0)
  322. return ret;
  323. return IIO_VAL_INT;
  324. case IIO_CHAN_INFO_SCALE:
  325. scale_uv = regulator_get_voltage(st->vref);
  326. if (scale_uv < 0)
  327. return scale_uv;
  328. *val = (scale_uv * 2) / 1000;
  329. *val2 = chan->scan_type.realbits;
  330. return IIO_VAL_FRACTIONAL_LOG2;
  331. case IIO_CHAN_INFO_SAMP_FREQ:
  332. *val = st->samp_freq;
  333. return IIO_VAL_INT;
  334. }
  335. return -EINVAL;
  336. }
  337. static int ad7768_write_raw(struct iio_dev *indio_dev,
  338. struct iio_chan_spec const *chan,
  339. int val, int val2, long info)
  340. {
  341. struct ad7768_state *st = iio_priv(indio_dev);
  342. switch (info) {
  343. case IIO_CHAN_INFO_SAMP_FREQ:
  344. return ad7768_set_freq(st, val);
  345. default:
  346. return -EINVAL;
  347. }
  348. }
  349. static struct attribute *ad7768_attributes[] = {
  350. &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
  351. NULL
  352. };
  353. static const struct attribute_group ad7768_group = {
  354. .attrs = ad7768_attributes,
  355. };
  356. static const struct iio_info ad7768_info = {
  357. .attrs = &ad7768_group,
  358. .read_raw = &ad7768_read_raw,
  359. .write_raw = &ad7768_write_raw,
  360. .debugfs_reg_access = &ad7768_reg_access,
  361. };
  362. static int ad7768_setup(struct ad7768_state *st)
  363. {
  364. int ret;
  365. /*
  366. * Two writes to the SPI_RESET[1:0] bits are required to initiate
  367. * a software reset. The bits must first be set to 11, and then
  368. * to 10. When the sequence is detected, the reset occurs.
  369. * See the datasheet, page 70.
  370. */
  371. ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x3);
  372. if (ret)
  373. return ret;
  374. ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x2);
  375. if (ret)
  376. return ret;
  377. st->gpio_sync_in = devm_gpiod_get(&st->spi->dev, "adi,sync-in",
  378. GPIOD_OUT_LOW);
  379. if (IS_ERR(st->gpio_sync_in))
  380. return PTR_ERR(st->gpio_sync_in);
  381. /* Set the default sampling frequency to 32000 kSPS */
  382. return ad7768_set_freq(st, 32000);
  383. }
  384. static irqreturn_t ad7768_trigger_handler(int irq, void *p)
  385. {
  386. struct iio_poll_func *pf = p;
  387. struct iio_dev *indio_dev = pf->indio_dev;
  388. struct ad7768_state *st = iio_priv(indio_dev);
  389. int ret;
  390. mutex_lock(&st->lock);
  391. ret = spi_read(st->spi, &st->data.scan.chan, 3);
  392. if (ret < 0)
  393. goto err_unlock;
  394. iio_push_to_buffers_with_timestamp(indio_dev, &st->data.scan,
  395. iio_get_time_ns(indio_dev));
  396. err_unlock:
  397. iio_trigger_notify_done(indio_dev->trig);
  398. mutex_unlock(&st->lock);
  399. return IRQ_HANDLED;
  400. }
  401. static irqreturn_t ad7768_interrupt(int irq, void *dev_id)
  402. {
  403. struct iio_dev *indio_dev = dev_id;
  404. struct ad7768_state *st = iio_priv(indio_dev);
  405. if (iio_buffer_enabled(indio_dev))
  406. iio_trigger_poll(st->trig);
  407. else
  408. complete(&st->completion);
  409. return IRQ_HANDLED;
  410. };
  411. static int ad7768_buffer_postenable(struct iio_dev *indio_dev)
  412. {
  413. struct ad7768_state *st = iio_priv(indio_dev);
  414. /*
  415. * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter
  416. * continuous read mode. Subsequent data reads do not require an
  417. * initial 8-bit write to query the ADC_DATA register.
  418. */
  419. return ad7768_spi_reg_write(st, AD7768_REG_INTERFACE_FORMAT, 0x01);
  420. }
  421. static int ad7768_buffer_predisable(struct iio_dev *indio_dev)
  422. {
  423. struct ad7768_state *st = iio_priv(indio_dev);
  424. /*
  425. * To exit continuous read mode, perform a single read of the ADC_DATA
  426. * reg (0x2C), which allows further configuration of the device.
  427. */
  428. return ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3);
  429. }
  430. static const struct iio_buffer_setup_ops ad7768_buffer_ops = {
  431. .postenable = &ad7768_buffer_postenable,
  432. .predisable = &ad7768_buffer_predisable,
  433. };
  434. static const struct iio_trigger_ops ad7768_trigger_ops = {
  435. .validate_device = iio_trigger_validate_own_device,
  436. };
  437. static void ad7768_regulator_disable(void *data)
  438. {
  439. struct ad7768_state *st = data;
  440. regulator_disable(st->vref);
  441. }
  442. static void ad7768_clk_disable(void *data)
  443. {
  444. struct ad7768_state *st = data;
  445. clk_disable_unprepare(st->mclk);
  446. }
  447. static int ad7768_probe(struct spi_device *spi)
  448. {
  449. struct ad7768_state *st;
  450. struct iio_dev *indio_dev;
  451. int ret;
  452. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  453. if (!indio_dev)
  454. return -ENOMEM;
  455. st = iio_priv(indio_dev);
  456. st->spi = spi;
  457. st->vref = devm_regulator_get(&spi->dev, "vref");
  458. if (IS_ERR(st->vref))
  459. return PTR_ERR(st->vref);
  460. ret = regulator_enable(st->vref);
  461. if (ret) {
  462. dev_err(&spi->dev, "Failed to enable specified vref supply\n");
  463. return ret;
  464. }
  465. ret = devm_add_action_or_reset(&spi->dev, ad7768_regulator_disable, st);
  466. if (ret)
  467. return ret;
  468. st->mclk = devm_clk_get(&spi->dev, "mclk");
  469. if (IS_ERR(st->mclk))
  470. return PTR_ERR(st->mclk);
  471. ret = clk_prepare_enable(st->mclk);
  472. if (ret < 0)
  473. return ret;
  474. ret = devm_add_action_or_reset(&spi->dev, ad7768_clk_disable, st);
  475. if (ret)
  476. return ret;
  477. st->mclk_freq = clk_get_rate(st->mclk);
  478. spi_set_drvdata(spi, indio_dev);
  479. mutex_init(&st->lock);
  480. indio_dev->channels = ad7768_channels;
  481. indio_dev->num_channels = ARRAY_SIZE(ad7768_channels);
  482. indio_dev->name = spi_get_device_id(spi)->name;
  483. indio_dev->info = &ad7768_info;
  484. indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_TRIGGERED;
  485. ret = ad7768_setup(st);
  486. if (ret < 0) {
  487. dev_err(&spi->dev, "AD7768 setup failed\n");
  488. return ret;
  489. }
  490. st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d",
  491. indio_dev->name, indio_dev->id);
  492. if (!st->trig)
  493. return -ENOMEM;
  494. st->trig->ops = &ad7768_trigger_ops;
  495. st->trig->dev.parent = &spi->dev;
  496. iio_trigger_set_drvdata(st->trig, indio_dev);
  497. ret = devm_iio_trigger_register(&spi->dev, st->trig);
  498. if (ret)
  499. return ret;
  500. indio_dev->trig = iio_trigger_get(st->trig);
  501. init_completion(&st->completion);
  502. ret = devm_request_irq(&spi->dev, spi->irq,
  503. &ad7768_interrupt,
  504. IRQF_TRIGGER_RISING | IRQF_ONESHOT,
  505. indio_dev->name, indio_dev);
  506. if (ret)
  507. return ret;
  508. ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
  509. &iio_pollfunc_store_time,
  510. &ad7768_trigger_handler,
  511. &ad7768_buffer_ops);
  512. if (ret)
  513. return ret;
  514. return devm_iio_device_register(&spi->dev, indio_dev);
  515. }
  516. static const struct spi_device_id ad7768_id_table[] = {
  517. { "ad7768-1", 0 },
  518. {}
  519. };
  520. MODULE_DEVICE_TABLE(spi, ad7768_id_table);
  521. static const struct of_device_id ad7768_of_match[] = {
  522. { .compatible = "adi,ad7768-1" },
  523. { },
  524. };
  525. MODULE_DEVICE_TABLE(of, ad7768_of_match);
  526. static struct spi_driver ad7768_driver = {
  527. .driver = {
  528. .name = "ad7768-1",
  529. .of_match_table = ad7768_of_match,
  530. },
  531. .probe = ad7768_probe,
  532. .id_table = ad7768_id_table,
  533. };
  534. module_spi_driver(ad7768_driver);
  535. MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
  536. MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver");
  537. MODULE_LICENSE("GPL v2");