ad7192.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * AD7190 AD7192 AD7193 AD7195 SPI ADC driver
  4. *
  5. * Copyright 2011-2015 Analog Devices Inc.
  6. */
  7. #include <linux/interrupt.h>
  8. #include <linux/clk.h>
  9. #include <linux/device.h>
  10. #include <linux/kernel.h>
  11. #include <linux/slab.h>
  12. #include <linux/sysfs.h>
  13. #include <linux/spi/spi.h>
  14. #include <linux/regulator/consumer.h>
  15. #include <linux/err.h>
  16. #include <linux/sched.h>
  17. #include <linux/delay.h>
  18. #include <linux/of_device.h>
  19. #include <linux/iio/iio.h>
  20. #include <linux/iio/sysfs.h>
  21. #include <linux/iio/buffer.h>
  22. #include <linux/iio/trigger.h>
  23. #include <linux/iio/trigger_consumer.h>
  24. #include <linux/iio/triggered_buffer.h>
  25. #include <linux/iio/adc/ad_sigma_delta.h>
  26. /* Registers */
  27. #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
  28. #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
  29. #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
  30. #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
  31. #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
  32. #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
  33. #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
  34. #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
  35. /* (AD7792)/24-bit (AD7192)) */
  36. #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
  37. /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
  38. /* Communications Register Bit Designations (AD7192_REG_COMM) */
  39. #define AD7192_COMM_WEN BIT(7) /* Write Enable */
  40. #define AD7192_COMM_WRITE 0 /* Write Operation */
  41. #define AD7192_COMM_READ BIT(6) /* Read Operation */
  42. #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
  43. #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */
  44. /* Status Register Bit Designations (AD7192_REG_STAT) */
  45. #define AD7192_STAT_RDY BIT(7) /* Ready */
  46. #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */
  47. #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */
  48. #define AD7192_STAT_PARITY BIT(4) /* Parity */
  49. #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */
  50. #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
  51. #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
  52. /* Mode Register Bit Designations (AD7192_REG_MODE) */
  53. #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
  54. #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */
  55. #define AD7192_MODE_DAT_STA BIT(20) /* Status Register transmission */
  56. #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
  57. #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
  58. #define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/
  59. #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
  60. #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
  61. #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
  62. #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */
  63. #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
  64. /* Mode Register: AD7192_MODE_SEL options */
  65. #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
  66. #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
  67. #define AD7192_MODE_IDLE 2 /* Idle Mode */
  68. #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
  69. #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
  70. #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
  71. #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
  72. #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
  73. /* Mode Register: AD7192_MODE_CLKSRC options */
  74. #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/
  75. /* from MCLK1 to MCLK2 */
  76. #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
  77. #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */
  78. /* available at the MCLK2 pin */
  79. #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/
  80. /* at the MCLK2 pin */
  81. /* Configuration Register Bit Designations (AD7192_REG_CONF) */
  82. #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */
  83. #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
  84. #define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */
  85. #define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */
  86. #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */
  87. #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */
  88. #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */
  89. #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */
  90. #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
  91. #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */
  92. #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
  93. #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */
  94. #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */
  95. #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */
  96. #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */
  97. #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */
  98. #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */
  99. #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */
  100. #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */
  101. #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */
  102. #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */
  103. #define AD7193_CH_TEMP 0x100 /* Temp senseor */
  104. #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */
  105. #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */
  106. #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */
  107. #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */
  108. #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */
  109. #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */
  110. #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */
  111. #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */
  112. #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */
  113. #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */
  114. /* ID Register Bit Designations (AD7192_REG_ID) */
  115. #define CHIPID_AD7190 0x4
  116. #define CHIPID_AD7192 0x0
  117. #define CHIPID_AD7193 0x2
  118. #define CHIPID_AD7195 0x6
  119. #define AD7192_ID_MASK 0x0F
  120. /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
  121. #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
  122. #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */
  123. #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */
  124. #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */
  125. #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */
  126. #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
  127. #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
  128. #define AD7192_EXT_FREQ_MHZ_MIN 2457600
  129. #define AD7192_EXT_FREQ_MHZ_MAX 5120000
  130. #define AD7192_INT_FREQ_MHZ 4915200
  131. #define AD7192_NO_SYNC_FILTER 1
  132. #define AD7192_SYNC3_FILTER 3
  133. #define AD7192_SYNC4_FILTER 4
  134. /* NOTE:
  135. * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
  136. * In order to avoid contentions on the SPI bus, it's therefore necessary
  137. * to use spi bus locking.
  138. *
  139. * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
  140. */
  141. enum {
  142. AD7192_SYSCALIB_ZERO_SCALE,
  143. AD7192_SYSCALIB_FULL_SCALE,
  144. };
  145. enum {
  146. ID_AD7190,
  147. ID_AD7192,
  148. ID_AD7193,
  149. ID_AD7195,
  150. };
  151. struct ad7192_chip_info {
  152. unsigned int chip_id;
  153. const char *name;
  154. };
  155. struct ad7192_state {
  156. const struct ad7192_chip_info *chip_info;
  157. struct regulator *avdd;
  158. struct regulator *dvdd;
  159. struct clk *mclk;
  160. u16 int_vref_mv;
  161. u32 fclk;
  162. u32 f_order;
  163. u32 mode;
  164. u32 conf;
  165. u32 scale_avail[8][2];
  166. u8 gpocon;
  167. u8 clock_sel;
  168. struct mutex lock; /* protect sensor state */
  169. u8 syscalib_mode[8];
  170. struct ad_sigma_delta sd;
  171. };
  172. static const char * const ad7192_syscalib_modes[] = {
  173. [AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale",
  174. [AD7192_SYSCALIB_FULL_SCALE] = "full_scale",
  175. };
  176. static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev,
  177. const struct iio_chan_spec *chan,
  178. unsigned int mode)
  179. {
  180. struct ad7192_state *st = iio_priv(indio_dev);
  181. st->syscalib_mode[chan->channel] = mode;
  182. return 0;
  183. }
  184. static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev,
  185. const struct iio_chan_spec *chan)
  186. {
  187. struct ad7192_state *st = iio_priv(indio_dev);
  188. return st->syscalib_mode[chan->channel];
  189. }
  190. static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev,
  191. uintptr_t private,
  192. const struct iio_chan_spec *chan,
  193. const char *buf, size_t len)
  194. {
  195. struct ad7192_state *st = iio_priv(indio_dev);
  196. bool sys_calib;
  197. int ret, temp;
  198. ret = strtobool(buf, &sys_calib);
  199. if (ret)
  200. return ret;
  201. temp = st->syscalib_mode[chan->channel];
  202. if (sys_calib) {
  203. if (temp == AD7192_SYSCALIB_ZERO_SCALE)
  204. ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO,
  205. chan->address);
  206. else
  207. ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL,
  208. chan->address);
  209. }
  210. return ret ? ret : len;
  211. }
  212. static const struct iio_enum ad7192_syscalib_mode_enum = {
  213. .items = ad7192_syscalib_modes,
  214. .num_items = ARRAY_SIZE(ad7192_syscalib_modes),
  215. .set = ad7192_set_syscalib_mode,
  216. .get = ad7192_get_syscalib_mode
  217. };
  218. static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = {
  219. {
  220. .name = "sys_calibration",
  221. .write = ad7192_write_syscalib,
  222. .shared = IIO_SEPARATE,
  223. },
  224. IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,
  225. &ad7192_syscalib_mode_enum),
  226. IIO_ENUM_AVAILABLE("sys_calibration_mode", &ad7192_syscalib_mode_enum),
  227. {}
  228. };
  229. static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
  230. {
  231. return container_of(sd, struct ad7192_state, sd);
  232. }
  233. static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
  234. {
  235. struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
  236. st->conf &= ~AD7192_CONF_CHAN_MASK;
  237. st->conf |= AD7192_CONF_CHAN(channel);
  238. return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
  239. }
  240. static int ad7192_set_mode(struct ad_sigma_delta *sd,
  241. enum ad_sigma_delta_mode mode)
  242. {
  243. struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
  244. st->mode &= ~AD7192_MODE_SEL_MASK;
  245. st->mode |= AD7192_MODE_SEL(mode);
  246. return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
  247. }
  248. static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
  249. .set_channel = ad7192_set_channel,
  250. .set_mode = ad7192_set_mode,
  251. .has_registers = true,
  252. .addr_shift = 3,
  253. .read_mask = BIT(6),
  254. .irq_flags = IRQF_TRIGGER_FALLING,
  255. };
  256. static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
  257. {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
  258. {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
  259. {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
  260. {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
  261. {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
  262. {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
  263. {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
  264. {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
  265. };
  266. static int ad7192_calibrate_all(struct ad7192_state *st)
  267. {
  268. return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
  269. ARRAY_SIZE(ad7192_calib_arr));
  270. }
  271. static inline bool ad7192_valid_external_frequency(u32 freq)
  272. {
  273. return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
  274. freq <= AD7192_EXT_FREQ_MHZ_MAX);
  275. }
  276. static int ad7192_of_clock_select(struct ad7192_state *st)
  277. {
  278. struct device_node *np = st->sd.spi->dev.of_node;
  279. unsigned int clock_sel;
  280. clock_sel = AD7192_CLK_INT;
  281. /* use internal clock */
  282. if (PTR_ERR(st->mclk) == -ENOENT) {
  283. if (of_property_read_bool(np, "adi,int-clock-output-enable"))
  284. clock_sel = AD7192_CLK_INT_CO;
  285. } else {
  286. if (of_property_read_bool(np, "adi,clock-xtal"))
  287. clock_sel = AD7192_CLK_EXT_MCLK1_2;
  288. else
  289. clock_sel = AD7192_CLK_EXT_MCLK2;
  290. }
  291. return clock_sel;
  292. }
  293. static int ad7192_setup(struct ad7192_state *st, struct device_node *np)
  294. {
  295. struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi);
  296. bool rej60_en, refin2_en;
  297. bool buf_en, bipolar, burnout_curr_en;
  298. unsigned long long scale_uv;
  299. int i, ret, id;
  300. /* reset the serial interface */
  301. ret = ad_sd_reset(&st->sd, 48);
  302. if (ret < 0)
  303. return ret;
  304. usleep_range(500, 1000); /* Wait for at least 500us */
  305. /* write/read test for device presence */
  306. ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
  307. if (ret)
  308. return ret;
  309. id &= AD7192_ID_MASK;
  310. if (id != st->chip_info->chip_id)
  311. dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n",
  312. id);
  313. st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
  314. AD7192_MODE_CLKSRC(st->clock_sel) |
  315. AD7192_MODE_RATE(480);
  316. st->conf = AD7192_CONF_GAIN(0);
  317. rej60_en = of_property_read_bool(np, "adi,rejection-60-Hz-enable");
  318. if (rej60_en)
  319. st->mode |= AD7192_MODE_REJ60;
  320. refin2_en = of_property_read_bool(np, "adi,refin2-pins-enable");
  321. if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195)
  322. st->conf |= AD7192_CONF_REFSEL;
  323. st->conf &= ~AD7192_CONF_CHOP;
  324. st->f_order = AD7192_NO_SYNC_FILTER;
  325. buf_en = of_property_read_bool(np, "adi,buffer-enable");
  326. if (buf_en)
  327. st->conf |= AD7192_CONF_BUF;
  328. bipolar = of_property_read_bool(np, "bipolar");
  329. if (!bipolar)
  330. st->conf |= AD7192_CONF_UNIPOLAR;
  331. burnout_curr_en = of_property_read_bool(np,
  332. "adi,burnout-currents-enable");
  333. if (burnout_curr_en && buf_en) {
  334. st->conf |= AD7192_CONF_BURN;
  335. } else if (burnout_curr_en) {
  336. dev_warn(&st->sd.spi->dev,
  337. "Can't enable burnout currents: see CHOP or buffer\n");
  338. }
  339. ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
  340. if (ret)
  341. return ret;
  342. ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
  343. if (ret)
  344. return ret;
  345. ret = ad7192_calibrate_all(st);
  346. if (ret)
  347. return ret;
  348. /* Populate available ADC input ranges */
  349. for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
  350. scale_uv = ((u64)st->int_vref_mv * 100000000)
  351. >> (indio_dev->channels[0].scan_type.realbits -
  352. ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
  353. scale_uv >>= i;
  354. st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
  355. st->scale_avail[i][0] = scale_uv;
  356. }
  357. return 0;
  358. }
  359. static ssize_t ad7192_show_ac_excitation(struct device *dev,
  360. struct device_attribute *attr,
  361. char *buf)
  362. {
  363. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  364. struct ad7192_state *st = iio_priv(indio_dev);
  365. return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
  366. }
  367. static ssize_t ad7192_show_bridge_switch(struct device *dev,
  368. struct device_attribute *attr,
  369. char *buf)
  370. {
  371. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  372. struct ad7192_state *st = iio_priv(indio_dev);
  373. return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
  374. }
  375. static ssize_t ad7192_set(struct device *dev,
  376. struct device_attribute *attr,
  377. const char *buf,
  378. size_t len)
  379. {
  380. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  381. struct ad7192_state *st = iio_priv(indio_dev);
  382. struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
  383. int ret;
  384. bool val;
  385. ret = strtobool(buf, &val);
  386. if (ret < 0)
  387. return ret;
  388. ret = iio_device_claim_direct_mode(indio_dev);
  389. if (ret)
  390. return ret;
  391. switch ((u32)this_attr->address) {
  392. case AD7192_REG_GPOCON:
  393. if (val)
  394. st->gpocon |= AD7192_GPOCON_BPDSW;
  395. else
  396. st->gpocon &= ~AD7192_GPOCON_BPDSW;
  397. ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
  398. break;
  399. case AD7192_REG_MODE:
  400. if (val)
  401. st->mode |= AD7192_MODE_ACX;
  402. else
  403. st->mode &= ~AD7192_MODE_ACX;
  404. ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
  405. break;
  406. default:
  407. ret = -EINVAL;
  408. }
  409. iio_device_release_direct_mode(indio_dev);
  410. return ret ? ret : len;
  411. }
  412. static void ad7192_get_available_filter_freq(struct ad7192_state *st,
  413. int *freq)
  414. {
  415. unsigned int fadc;
  416. /* Formulas for filter at page 25 of the datasheet */
  417. fadc = DIV_ROUND_CLOSEST(st->fclk,
  418. AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode));
  419. freq[0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
  420. fadc = DIV_ROUND_CLOSEST(st->fclk,
  421. AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode));
  422. freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
  423. fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode));
  424. freq[2] = DIV_ROUND_CLOSEST(fadc * 230, 1024);
  425. freq[3] = DIV_ROUND_CLOSEST(fadc * 272, 1024);
  426. }
  427. static ssize_t ad7192_show_filter_avail(struct device *dev,
  428. struct device_attribute *attr,
  429. char *buf)
  430. {
  431. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  432. struct ad7192_state *st = iio_priv(indio_dev);
  433. unsigned int freq_avail[4], i;
  434. size_t len = 0;
  435. ad7192_get_available_filter_freq(st, freq_avail);
  436. for (i = 0; i < ARRAY_SIZE(freq_avail); i++)
  437. len += scnprintf(buf + len, PAGE_SIZE - len,
  438. "%d.%d ", freq_avail[i] / 1000,
  439. freq_avail[i] % 1000);
  440. buf[len - 1] = '\n';
  441. return len;
  442. }
  443. static IIO_DEVICE_ATTR(filter_low_pass_3db_frequency_available,
  444. 0444, ad7192_show_filter_avail, NULL, 0);
  445. static IIO_DEVICE_ATTR(bridge_switch_en, 0644,
  446. ad7192_show_bridge_switch, ad7192_set,
  447. AD7192_REG_GPOCON);
  448. static IIO_DEVICE_ATTR(ac_excitation_en, 0644,
  449. ad7192_show_ac_excitation, ad7192_set,
  450. AD7192_REG_MODE);
  451. static struct attribute *ad7192_attributes[] = {
  452. &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
  453. &iio_dev_attr_bridge_switch_en.dev_attr.attr,
  454. &iio_dev_attr_ac_excitation_en.dev_attr.attr,
  455. NULL
  456. };
  457. static const struct attribute_group ad7192_attribute_group = {
  458. .attrs = ad7192_attributes,
  459. };
  460. static struct attribute *ad7195_attributes[] = {
  461. &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
  462. &iio_dev_attr_bridge_switch_en.dev_attr.attr,
  463. NULL
  464. };
  465. static const struct attribute_group ad7195_attribute_group = {
  466. .attrs = ad7195_attributes,
  467. };
  468. static unsigned int ad7192_get_temp_scale(bool unipolar)
  469. {
  470. return unipolar ? 2815 * 2 : 2815;
  471. }
  472. static int ad7192_set_3db_filter_freq(struct ad7192_state *st,
  473. int val, int val2)
  474. {
  475. int freq_avail[4], i, ret, freq;
  476. unsigned int diff_new, diff_old;
  477. int idx = 0;
  478. diff_old = U32_MAX;
  479. freq = val * 1000 + val2;
  480. ad7192_get_available_filter_freq(st, freq_avail);
  481. for (i = 0; i < ARRAY_SIZE(freq_avail); i++) {
  482. diff_new = abs(freq - freq_avail[i]);
  483. if (diff_new < diff_old) {
  484. diff_old = diff_new;
  485. idx = i;
  486. }
  487. }
  488. switch (idx) {
  489. case 0:
  490. st->f_order = AD7192_SYNC4_FILTER;
  491. st->mode &= ~AD7192_MODE_SINC3;
  492. st->conf |= AD7192_CONF_CHOP;
  493. break;
  494. case 1:
  495. st->f_order = AD7192_SYNC3_FILTER;
  496. st->mode |= AD7192_MODE_SINC3;
  497. st->conf |= AD7192_CONF_CHOP;
  498. break;
  499. case 2:
  500. st->f_order = AD7192_NO_SYNC_FILTER;
  501. st->mode &= ~AD7192_MODE_SINC3;
  502. st->conf &= ~AD7192_CONF_CHOP;
  503. break;
  504. case 3:
  505. st->f_order = AD7192_NO_SYNC_FILTER;
  506. st->mode |= AD7192_MODE_SINC3;
  507. st->conf &= ~AD7192_CONF_CHOP;
  508. break;
  509. }
  510. ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
  511. if (ret < 0)
  512. return ret;
  513. return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
  514. }
  515. static int ad7192_get_3db_filter_freq(struct ad7192_state *st)
  516. {
  517. unsigned int fadc;
  518. fadc = DIV_ROUND_CLOSEST(st->fclk,
  519. st->f_order * AD7192_MODE_RATE(st->mode));
  520. if (st->conf & AD7192_CONF_CHOP)
  521. return DIV_ROUND_CLOSEST(fadc * 240, 1024);
  522. if (st->mode & AD7192_MODE_SINC3)
  523. return DIV_ROUND_CLOSEST(fadc * 272, 1024);
  524. else
  525. return DIV_ROUND_CLOSEST(fadc * 230, 1024);
  526. }
  527. static int ad7192_read_raw(struct iio_dev *indio_dev,
  528. struct iio_chan_spec const *chan,
  529. int *val,
  530. int *val2,
  531. long m)
  532. {
  533. struct ad7192_state *st = iio_priv(indio_dev);
  534. bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
  535. switch (m) {
  536. case IIO_CHAN_INFO_RAW:
  537. return ad_sigma_delta_single_conversion(indio_dev, chan, val);
  538. case IIO_CHAN_INFO_SCALE:
  539. switch (chan->type) {
  540. case IIO_VOLTAGE:
  541. mutex_lock(&st->lock);
  542. *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
  543. *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
  544. mutex_unlock(&st->lock);
  545. return IIO_VAL_INT_PLUS_NANO;
  546. case IIO_TEMP:
  547. *val = 0;
  548. *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
  549. return IIO_VAL_INT_PLUS_NANO;
  550. default:
  551. return -EINVAL;
  552. }
  553. case IIO_CHAN_INFO_OFFSET:
  554. if (!unipolar)
  555. *val = -(1 << (chan->scan_type.realbits - 1));
  556. else
  557. *val = 0;
  558. /* Kelvin to Celsius */
  559. if (chan->type == IIO_TEMP)
  560. *val -= 273 * ad7192_get_temp_scale(unipolar);
  561. return IIO_VAL_INT;
  562. case IIO_CHAN_INFO_SAMP_FREQ:
  563. *val = st->fclk /
  564. (st->f_order * 1024 * AD7192_MODE_RATE(st->mode));
  565. return IIO_VAL_INT;
  566. case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
  567. *val = ad7192_get_3db_filter_freq(st);
  568. *val2 = 1000;
  569. return IIO_VAL_FRACTIONAL;
  570. }
  571. return -EINVAL;
  572. }
  573. static int ad7192_write_raw(struct iio_dev *indio_dev,
  574. struct iio_chan_spec const *chan,
  575. int val,
  576. int val2,
  577. long mask)
  578. {
  579. struct ad7192_state *st = iio_priv(indio_dev);
  580. int ret, i, div;
  581. unsigned int tmp;
  582. ret = iio_device_claim_direct_mode(indio_dev);
  583. if (ret)
  584. return ret;
  585. switch (mask) {
  586. case IIO_CHAN_INFO_SCALE:
  587. ret = -EINVAL;
  588. mutex_lock(&st->lock);
  589. for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
  590. if (val2 == st->scale_avail[i][1]) {
  591. ret = 0;
  592. tmp = st->conf;
  593. st->conf &= ~AD7192_CONF_GAIN(-1);
  594. st->conf |= AD7192_CONF_GAIN(i);
  595. if (tmp == st->conf)
  596. break;
  597. ad_sd_write_reg(&st->sd, AD7192_REG_CONF,
  598. 3, st->conf);
  599. ad7192_calibrate_all(st);
  600. break;
  601. }
  602. mutex_unlock(&st->lock);
  603. break;
  604. case IIO_CHAN_INFO_SAMP_FREQ:
  605. if (!val) {
  606. ret = -EINVAL;
  607. break;
  608. }
  609. div = st->fclk / (val * st->f_order * 1024);
  610. if (div < 1 || div > 1023) {
  611. ret = -EINVAL;
  612. break;
  613. }
  614. st->mode &= ~AD7192_MODE_RATE(-1);
  615. st->mode |= AD7192_MODE_RATE(div);
  616. ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
  617. break;
  618. case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
  619. ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000);
  620. break;
  621. default:
  622. ret = -EINVAL;
  623. }
  624. iio_device_release_direct_mode(indio_dev);
  625. return ret;
  626. }
  627. static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
  628. struct iio_chan_spec const *chan,
  629. long mask)
  630. {
  631. switch (mask) {
  632. case IIO_CHAN_INFO_SCALE:
  633. return IIO_VAL_INT_PLUS_NANO;
  634. case IIO_CHAN_INFO_SAMP_FREQ:
  635. return IIO_VAL_INT;
  636. case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
  637. return IIO_VAL_INT_PLUS_MICRO;
  638. default:
  639. return -EINVAL;
  640. }
  641. }
  642. static int ad7192_read_avail(struct iio_dev *indio_dev,
  643. struct iio_chan_spec const *chan,
  644. const int **vals, int *type, int *length,
  645. long mask)
  646. {
  647. struct ad7192_state *st = iio_priv(indio_dev);
  648. switch (mask) {
  649. case IIO_CHAN_INFO_SCALE:
  650. *vals = (int *)st->scale_avail;
  651. *type = IIO_VAL_INT_PLUS_NANO;
  652. /* Values are stored in a 2D matrix */
  653. *length = ARRAY_SIZE(st->scale_avail) * 2;
  654. return IIO_AVAIL_LIST;
  655. }
  656. return -EINVAL;
  657. }
  658. static const struct iio_info ad7192_info = {
  659. .read_raw = ad7192_read_raw,
  660. .write_raw = ad7192_write_raw,
  661. .write_raw_get_fmt = ad7192_write_raw_get_fmt,
  662. .read_avail = ad7192_read_avail,
  663. .attrs = &ad7192_attribute_group,
  664. .validate_trigger = ad_sd_validate_trigger,
  665. };
  666. static const struct iio_info ad7195_info = {
  667. .read_raw = ad7192_read_raw,
  668. .write_raw = ad7192_write_raw,
  669. .write_raw_get_fmt = ad7192_write_raw_get_fmt,
  670. .read_avail = ad7192_read_avail,
  671. .attrs = &ad7195_attribute_group,
  672. .validate_trigger = ad_sd_validate_trigger,
  673. };
  674. #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _extend_name, \
  675. _type, _mask_type_av, _ext_info) \
  676. { \
  677. .type = (_type), \
  678. .differential = ((_channel2) == -1 ? 0 : 1), \
  679. .indexed = 1, \
  680. .channel = (_channel1), \
  681. .channel2 = (_channel2), \
  682. .address = (_address), \
  683. .extend_name = (_extend_name), \
  684. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  685. BIT(IIO_CHAN_INFO_OFFSET), \
  686. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  687. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
  688. BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
  689. .info_mask_shared_by_type_available = (_mask_type_av), \
  690. .ext_info = (_ext_info), \
  691. .scan_index = (_si), \
  692. .scan_type = { \
  693. .sign = 'u', \
  694. .realbits = 24, \
  695. .storagebits = 32, \
  696. .endianness = IIO_BE, \
  697. }, \
  698. }
  699. #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \
  700. __AD719x_CHANNEL(_si, _channel1, _channel2, _address, NULL, \
  701. IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE), \
  702. ad7192_calibsys_ext_info)
  703. #define AD719x_CHANNEL(_si, _channel1, _address) \
  704. __AD719x_CHANNEL(_si, _channel1, -1, _address, NULL, IIO_VOLTAGE, \
  705. BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info)
  706. #define AD719x_SHORTED_CHANNEL(_si, _channel1, _address) \
  707. __AD719x_CHANNEL(_si, _channel1, -1, _address, "shorted", IIO_VOLTAGE, \
  708. BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info)
  709. #define AD719x_TEMP_CHANNEL(_si, _address) \
  710. __AD719x_CHANNEL(_si, 0, -1, _address, NULL, IIO_TEMP, 0, NULL)
  711. static const struct iio_chan_spec ad7192_channels[] = {
  712. AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M),
  713. AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M),
  714. AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP),
  715. AD719x_SHORTED_CHANNEL(3, 2, AD7192_CH_AIN2P_AIN2M),
  716. AD719x_CHANNEL(4, 1, AD7192_CH_AIN1),
  717. AD719x_CHANNEL(5, 2, AD7192_CH_AIN2),
  718. AD719x_CHANNEL(6, 3, AD7192_CH_AIN3),
  719. AD719x_CHANNEL(7, 4, AD7192_CH_AIN4),
  720. IIO_CHAN_SOFT_TIMESTAMP(8),
  721. };
  722. static const struct iio_chan_spec ad7193_channels[] = {
  723. AD719x_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),
  724. AD719x_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),
  725. AD719x_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M),
  726. AD719x_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M),
  727. AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP),
  728. AD719x_SHORTED_CHANNEL(5, 2, AD7193_CH_AIN2P_AIN2M),
  729. AD719x_CHANNEL(6, 1, AD7193_CH_AIN1),
  730. AD719x_CHANNEL(7, 2, AD7193_CH_AIN2),
  731. AD719x_CHANNEL(8, 3, AD7193_CH_AIN3),
  732. AD719x_CHANNEL(9, 4, AD7193_CH_AIN4),
  733. AD719x_CHANNEL(10, 5, AD7193_CH_AIN5),
  734. AD719x_CHANNEL(11, 6, AD7193_CH_AIN6),
  735. AD719x_CHANNEL(12, 7, AD7193_CH_AIN7),
  736. AD719x_CHANNEL(13, 8, AD7193_CH_AIN8),
  737. IIO_CHAN_SOFT_TIMESTAMP(14),
  738. };
  739. static const struct ad7192_chip_info ad7192_chip_info_tbl[] = {
  740. [ID_AD7190] = {
  741. .chip_id = CHIPID_AD7190,
  742. .name = "ad7190",
  743. },
  744. [ID_AD7192] = {
  745. .chip_id = CHIPID_AD7192,
  746. .name = "ad7192",
  747. },
  748. [ID_AD7193] = {
  749. .chip_id = CHIPID_AD7193,
  750. .name = "ad7193",
  751. },
  752. [ID_AD7195] = {
  753. .chip_id = CHIPID_AD7195,
  754. .name = "ad7195",
  755. },
  756. };
  757. static int ad7192_channels_config(struct iio_dev *indio_dev)
  758. {
  759. struct ad7192_state *st = iio_priv(indio_dev);
  760. switch (st->chip_info->chip_id) {
  761. case CHIPID_AD7193:
  762. indio_dev->channels = ad7193_channels;
  763. indio_dev->num_channels = ARRAY_SIZE(ad7193_channels);
  764. break;
  765. default:
  766. indio_dev->channels = ad7192_channels;
  767. indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
  768. break;
  769. }
  770. return 0;
  771. }
  772. static int ad7192_probe(struct spi_device *spi)
  773. {
  774. struct ad7192_state *st;
  775. struct iio_dev *indio_dev;
  776. int ret;
  777. if (!spi->irq) {
  778. dev_err(&spi->dev, "no IRQ?\n");
  779. return -ENODEV;
  780. }
  781. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  782. if (!indio_dev)
  783. return -ENOMEM;
  784. st = iio_priv(indio_dev);
  785. mutex_init(&st->lock);
  786. st->avdd = devm_regulator_get(&spi->dev, "avdd");
  787. if (IS_ERR(st->avdd))
  788. return PTR_ERR(st->avdd);
  789. ret = regulator_enable(st->avdd);
  790. if (ret) {
  791. dev_err(&spi->dev, "Failed to enable specified AVdd supply\n");
  792. return ret;
  793. }
  794. st->dvdd = devm_regulator_get(&spi->dev, "dvdd");
  795. if (IS_ERR(st->dvdd)) {
  796. ret = PTR_ERR(st->dvdd);
  797. goto error_disable_avdd;
  798. }
  799. ret = regulator_enable(st->dvdd);
  800. if (ret) {
  801. dev_err(&spi->dev, "Failed to enable specified DVdd supply\n");
  802. goto error_disable_avdd;
  803. }
  804. ret = regulator_get_voltage(st->avdd);
  805. if (ret < 0) {
  806. dev_err(&spi->dev, "Device tree error, reference voltage undefined\n");
  807. goto error_disable_avdd;
  808. }
  809. st->int_vref_mv = ret / 1000;
  810. spi_set_drvdata(spi, indio_dev);
  811. st->chip_info = of_device_get_match_data(&spi->dev);
  812. indio_dev->name = st->chip_info->name;
  813. indio_dev->modes = INDIO_DIRECT_MODE;
  814. ret = ad7192_channels_config(indio_dev);
  815. if (ret < 0)
  816. goto error_disable_dvdd;
  817. if (st->chip_info->chip_id == CHIPID_AD7195)
  818. indio_dev->info = &ad7195_info;
  819. else
  820. indio_dev->info = &ad7192_info;
  821. ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info);
  822. ret = ad_sd_setup_buffer_and_trigger(indio_dev);
  823. if (ret)
  824. goto error_disable_dvdd;
  825. st->fclk = AD7192_INT_FREQ_MHZ;
  826. st->mclk = devm_clk_get(&st->sd.spi->dev, "mclk");
  827. if (IS_ERR(st->mclk) && PTR_ERR(st->mclk) != -ENOENT) {
  828. ret = PTR_ERR(st->mclk);
  829. goto error_remove_trigger;
  830. }
  831. st->clock_sel = ad7192_of_clock_select(st);
  832. if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||
  833. st->clock_sel == AD7192_CLK_EXT_MCLK2) {
  834. ret = clk_prepare_enable(st->mclk);
  835. if (ret < 0)
  836. goto error_remove_trigger;
  837. st->fclk = clk_get_rate(st->mclk);
  838. if (!ad7192_valid_external_frequency(st->fclk)) {
  839. ret = -EINVAL;
  840. dev_err(&spi->dev,
  841. "External clock frequency out of bounds\n");
  842. goto error_disable_clk;
  843. }
  844. }
  845. ret = ad7192_setup(st, spi->dev.of_node);
  846. if (ret)
  847. goto error_disable_clk;
  848. ret = iio_device_register(indio_dev);
  849. if (ret < 0)
  850. goto error_disable_clk;
  851. return 0;
  852. error_disable_clk:
  853. if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||
  854. st->clock_sel == AD7192_CLK_EXT_MCLK2)
  855. clk_disable_unprepare(st->mclk);
  856. error_remove_trigger:
  857. ad_sd_cleanup_buffer_and_trigger(indio_dev);
  858. error_disable_dvdd:
  859. regulator_disable(st->dvdd);
  860. error_disable_avdd:
  861. regulator_disable(st->avdd);
  862. return ret;
  863. }
  864. static int ad7192_remove(struct spi_device *spi)
  865. {
  866. struct iio_dev *indio_dev = spi_get_drvdata(spi);
  867. struct ad7192_state *st = iio_priv(indio_dev);
  868. iio_device_unregister(indio_dev);
  869. if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||
  870. st->clock_sel == AD7192_CLK_EXT_MCLK2)
  871. clk_disable_unprepare(st->mclk);
  872. ad_sd_cleanup_buffer_and_trigger(indio_dev);
  873. regulator_disable(st->dvdd);
  874. regulator_disable(st->avdd);
  875. return 0;
  876. }
  877. static const struct of_device_id ad7192_of_match[] = {
  878. { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] },
  879. { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] },
  880. { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] },
  881. { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] },
  882. {}
  883. };
  884. MODULE_DEVICE_TABLE(of, ad7192_of_match);
  885. static struct spi_driver ad7192_driver = {
  886. .driver = {
  887. .name = "ad7192",
  888. .of_match_table = ad7192_of_match,
  889. },
  890. .probe = ad7192_probe,
  891. .remove = ad7192_remove,
  892. };
  893. module_spi_driver(ad7192_driver);
  894. MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
  895. MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC");
  896. MODULE_LICENSE("GPL v2");