ad7124.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * AD7124 SPI ADC driver
  4. *
  5. * Copyright 2018 Analog Devices Inc.
  6. */
  7. #include <linux/bitfield.h>
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/device.h>
  11. #include <linux/err.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/of_device.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/spi/spi.h>
  18. #include <linux/iio/iio.h>
  19. #include <linux/iio/adc/ad_sigma_delta.h>
  20. #include <linux/iio/sysfs.h>
  21. /* AD7124 registers */
  22. #define AD7124_COMMS 0x00
  23. #define AD7124_STATUS 0x00
  24. #define AD7124_ADC_CONTROL 0x01
  25. #define AD7124_DATA 0x02
  26. #define AD7124_IO_CONTROL_1 0x03
  27. #define AD7124_IO_CONTROL_2 0x04
  28. #define AD7124_ID 0x05
  29. #define AD7124_ERROR 0x06
  30. #define AD7124_ERROR_EN 0x07
  31. #define AD7124_MCLK_COUNT 0x08
  32. #define AD7124_CHANNEL(x) (0x09 + (x))
  33. #define AD7124_CONFIG(x) (0x19 + (x))
  34. #define AD7124_FILTER(x) (0x21 + (x))
  35. #define AD7124_OFFSET(x) (0x29 + (x))
  36. #define AD7124_GAIN(x) (0x31 + (x))
  37. /* AD7124_STATUS */
  38. #define AD7124_STATUS_POR_FLAG_MSK BIT(4)
  39. /* AD7124_ADC_CONTROL */
  40. #define AD7124_ADC_CTRL_REF_EN_MSK BIT(8)
  41. #define AD7124_ADC_CTRL_REF_EN(x) FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x)
  42. #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
  43. #define AD7124_ADC_CTRL_PWR(x) FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
  44. #define AD7124_ADC_CTRL_MODE_MSK GENMASK(5, 2)
  45. #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
  46. /* AD7124 ID */
  47. #define AD7124_DEVICE_ID_MSK GENMASK(7, 4)
  48. #define AD7124_DEVICE_ID_GET(x) FIELD_GET(AD7124_DEVICE_ID_MSK, x)
  49. #define AD7124_SILICON_REV_MSK GENMASK(3, 0)
  50. #define AD7124_SILICON_REV_GET(x) FIELD_GET(AD7124_SILICON_REV_MSK, x)
  51. #define CHIPID_AD7124_4 0x0
  52. #define CHIPID_AD7124_8 0x1
  53. /* AD7124_CHANNEL_X */
  54. #define AD7124_CHANNEL_EN_MSK BIT(15)
  55. #define AD7124_CHANNEL_EN(x) FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
  56. #define AD7124_CHANNEL_SETUP_MSK GENMASK(14, 12)
  57. #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
  58. #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
  59. #define AD7124_CHANNEL_AINP(x) FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
  60. #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
  61. #define AD7124_CHANNEL_AINM(x) FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
  62. /* AD7124_CONFIG_X */
  63. #define AD7124_CONFIG_BIPOLAR_MSK BIT(11)
  64. #define AD7124_CONFIG_BIPOLAR(x) FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
  65. #define AD7124_CONFIG_REF_SEL_MSK GENMASK(4, 3)
  66. #define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
  67. #define AD7124_CONFIG_PGA_MSK GENMASK(2, 0)
  68. #define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
  69. #define AD7124_CONFIG_IN_BUFF_MSK GENMASK(6, 5)
  70. #define AD7124_CONFIG_IN_BUFF(x) FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
  71. /* AD7124_FILTER_X */
  72. #define AD7124_FILTER_FS_MSK GENMASK(10, 0)
  73. #define AD7124_FILTER_FS(x) FIELD_PREP(AD7124_FILTER_FS_MSK, x)
  74. #define AD7124_FILTER_TYPE_MSK GENMASK(23, 21)
  75. #define AD7124_FILTER_TYPE_SEL(x) FIELD_PREP(AD7124_FILTER_TYPE_MSK, x)
  76. #define AD7124_SINC3_FILTER 2
  77. #define AD7124_SINC4_FILTER 0
  78. enum ad7124_ids {
  79. ID_AD7124_4,
  80. ID_AD7124_8,
  81. };
  82. enum ad7124_ref_sel {
  83. AD7124_REFIN1,
  84. AD7124_REFIN2,
  85. AD7124_INT_REF,
  86. AD7124_AVDD_REF,
  87. };
  88. enum ad7124_power_mode {
  89. AD7124_LOW_POWER,
  90. AD7124_MID_POWER,
  91. AD7124_FULL_POWER,
  92. };
  93. static const unsigned int ad7124_gain[8] = {
  94. 1, 2, 4, 8, 16, 32, 64, 128
  95. };
  96. static const unsigned int ad7124_reg_size[] = {
  97. 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
  98. 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
  99. 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
  100. 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
  101. 3, 3, 3, 3, 3
  102. };
  103. static const int ad7124_master_clk_freq_hz[3] = {
  104. [AD7124_LOW_POWER] = 76800,
  105. [AD7124_MID_POWER] = 153600,
  106. [AD7124_FULL_POWER] = 614400,
  107. };
  108. static const char * const ad7124_ref_names[] = {
  109. [AD7124_REFIN1] = "refin1",
  110. [AD7124_REFIN2] = "refin2",
  111. [AD7124_INT_REF] = "int",
  112. [AD7124_AVDD_REF] = "avdd",
  113. };
  114. struct ad7124_chip_info {
  115. const char *name;
  116. unsigned int chip_id;
  117. unsigned int num_inputs;
  118. };
  119. struct ad7124_channel_config {
  120. enum ad7124_ref_sel refsel;
  121. bool bipolar;
  122. bool buf_positive;
  123. bool buf_negative;
  124. unsigned int ain;
  125. unsigned int vref_mv;
  126. unsigned int pga_bits;
  127. unsigned int odr;
  128. unsigned int filter_type;
  129. };
  130. struct ad7124_state {
  131. const struct ad7124_chip_info *chip_info;
  132. struct ad_sigma_delta sd;
  133. struct ad7124_channel_config *channel_config;
  134. struct regulator *vref[4];
  135. struct clk *mclk;
  136. unsigned int adc_control;
  137. unsigned int num_channels;
  138. };
  139. static const struct iio_chan_spec ad7124_channel_template = {
  140. .type = IIO_VOLTAGE,
  141. .indexed = 1,
  142. .differential = 1,
  143. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
  144. BIT(IIO_CHAN_INFO_SCALE) |
  145. BIT(IIO_CHAN_INFO_OFFSET) |
  146. BIT(IIO_CHAN_INFO_SAMP_FREQ) |
  147. BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
  148. .scan_type = {
  149. .sign = 'u',
  150. .realbits = 24,
  151. .storagebits = 32,
  152. .shift = 8,
  153. .endianness = IIO_BE,
  154. },
  155. };
  156. static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
  157. [ID_AD7124_4] = {
  158. .name = "ad7124-4",
  159. .chip_id = CHIPID_AD7124_4,
  160. .num_inputs = 8,
  161. },
  162. [ID_AD7124_8] = {
  163. .name = "ad7124-8",
  164. .chip_id = CHIPID_AD7124_8,
  165. .num_inputs = 16,
  166. },
  167. };
  168. static int ad7124_find_closest_match(const int *array,
  169. unsigned int size, int val)
  170. {
  171. int i, idx;
  172. unsigned int diff_new, diff_old;
  173. diff_old = U32_MAX;
  174. idx = 0;
  175. for (i = 0; i < size; i++) {
  176. diff_new = abs(val - array[i]);
  177. if (diff_new < diff_old) {
  178. diff_old = diff_new;
  179. idx = i;
  180. }
  181. }
  182. return idx;
  183. }
  184. static int ad7124_spi_write_mask(struct ad7124_state *st,
  185. unsigned int addr,
  186. unsigned long mask,
  187. unsigned int val,
  188. unsigned int bytes)
  189. {
  190. unsigned int readval;
  191. int ret;
  192. ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
  193. if (ret < 0)
  194. return ret;
  195. readval &= ~mask;
  196. readval |= val;
  197. return ad_sd_write_reg(&st->sd, addr, bytes, readval);
  198. }
  199. static int ad7124_set_mode(struct ad_sigma_delta *sd,
  200. enum ad_sigma_delta_mode mode)
  201. {
  202. struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
  203. st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
  204. st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
  205. return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
  206. }
  207. static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
  208. {
  209. struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
  210. unsigned int val;
  211. val = st->channel_config[channel].ain | AD7124_CHANNEL_EN(1) |
  212. AD7124_CHANNEL_SETUP(channel);
  213. return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(channel), 2, val);
  214. }
  215. static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
  216. .set_channel = ad7124_set_channel,
  217. .set_mode = ad7124_set_mode,
  218. .has_registers = true,
  219. .addr_shift = 0,
  220. .read_mask = BIT(6),
  221. .data_reg = AD7124_DATA,
  222. .irq_flags = IRQF_TRIGGER_FALLING,
  223. };
  224. static int ad7124_set_channel_odr(struct ad7124_state *st,
  225. unsigned int channel,
  226. unsigned int odr)
  227. {
  228. unsigned int fclk, odr_sel_bits;
  229. int ret;
  230. fclk = clk_get_rate(st->mclk);
  231. /*
  232. * FS[10:0] = fCLK / (fADC x 32) where:
  233. * fADC is the output data rate
  234. * fCLK is the master clock frequency
  235. * FS[10:0] are the bits in the filter register
  236. * FS[10:0] can have a value from 1 to 2047
  237. */
  238. odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
  239. if (odr_sel_bits < 1)
  240. odr_sel_bits = 1;
  241. else if (odr_sel_bits > 2047)
  242. odr_sel_bits = 2047;
  243. ret = ad7124_spi_write_mask(st, AD7124_FILTER(channel),
  244. AD7124_FILTER_FS_MSK,
  245. AD7124_FILTER_FS(odr_sel_bits), 3);
  246. if (ret < 0)
  247. return ret;
  248. /* fADC = fCLK / (FS[10:0] x 32) */
  249. st->channel_config[channel].odr =
  250. DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
  251. return 0;
  252. }
  253. static int ad7124_set_channel_gain(struct ad7124_state *st,
  254. unsigned int channel,
  255. unsigned int gain)
  256. {
  257. unsigned int res;
  258. int ret;
  259. res = ad7124_find_closest_match(ad7124_gain,
  260. ARRAY_SIZE(ad7124_gain), gain);
  261. ret = ad7124_spi_write_mask(st, AD7124_CONFIG(channel),
  262. AD7124_CONFIG_PGA_MSK,
  263. AD7124_CONFIG_PGA(res), 2);
  264. if (ret < 0)
  265. return ret;
  266. st->channel_config[channel].pga_bits = res;
  267. return 0;
  268. }
  269. static int ad7124_get_3db_filter_freq(struct ad7124_state *st,
  270. unsigned int channel)
  271. {
  272. unsigned int fadc;
  273. fadc = st->channel_config[channel].odr;
  274. switch (st->channel_config[channel].filter_type) {
  275. case AD7124_SINC3_FILTER:
  276. return DIV_ROUND_CLOSEST(fadc * 230, 1000);
  277. case AD7124_SINC4_FILTER:
  278. return DIV_ROUND_CLOSEST(fadc * 262, 1000);
  279. default:
  280. return -EINVAL;
  281. }
  282. }
  283. static int ad7124_set_3db_filter_freq(struct ad7124_state *st,
  284. unsigned int channel,
  285. unsigned int freq)
  286. {
  287. unsigned int sinc4_3db_odr;
  288. unsigned int sinc3_3db_odr;
  289. unsigned int new_filter;
  290. unsigned int new_odr;
  291. sinc4_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 230);
  292. sinc3_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 262);
  293. if (sinc4_3db_odr > sinc3_3db_odr) {
  294. new_filter = AD7124_SINC3_FILTER;
  295. new_odr = sinc4_3db_odr;
  296. } else {
  297. new_filter = AD7124_SINC4_FILTER;
  298. new_odr = sinc3_3db_odr;
  299. }
  300. if (st->channel_config[channel].filter_type != new_filter) {
  301. int ret;
  302. st->channel_config[channel].filter_type = new_filter;
  303. ret = ad7124_spi_write_mask(st, AD7124_FILTER(channel),
  304. AD7124_FILTER_TYPE_MSK,
  305. AD7124_FILTER_TYPE_SEL(new_filter),
  306. 3);
  307. if (ret < 0)
  308. return ret;
  309. }
  310. return ad7124_set_channel_odr(st, channel, new_odr);
  311. }
  312. static int ad7124_read_raw(struct iio_dev *indio_dev,
  313. struct iio_chan_spec const *chan,
  314. int *val, int *val2, long info)
  315. {
  316. struct ad7124_state *st = iio_priv(indio_dev);
  317. int idx, ret;
  318. switch (info) {
  319. case IIO_CHAN_INFO_RAW:
  320. ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
  321. if (ret < 0)
  322. return ret;
  323. /* After the conversion is performed, disable the channel */
  324. ret = ad_sd_write_reg(&st->sd,
  325. AD7124_CHANNEL(chan->address), 2,
  326. st->channel_config[chan->address].ain |
  327. AD7124_CHANNEL_EN(0));
  328. if (ret < 0)
  329. return ret;
  330. return IIO_VAL_INT;
  331. case IIO_CHAN_INFO_SCALE:
  332. idx = st->channel_config[chan->address].pga_bits;
  333. *val = st->channel_config[chan->address].vref_mv;
  334. if (st->channel_config[chan->address].bipolar)
  335. *val2 = chan->scan_type.realbits - 1 + idx;
  336. else
  337. *val2 = chan->scan_type.realbits + idx;
  338. return IIO_VAL_FRACTIONAL_LOG2;
  339. case IIO_CHAN_INFO_OFFSET:
  340. if (st->channel_config[chan->address].bipolar)
  341. *val = -(1 << (chan->scan_type.realbits - 1));
  342. else
  343. *val = 0;
  344. return IIO_VAL_INT;
  345. case IIO_CHAN_INFO_SAMP_FREQ:
  346. *val = st->channel_config[chan->address].odr;
  347. return IIO_VAL_INT;
  348. case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
  349. *val = ad7124_get_3db_filter_freq(st, chan->scan_index);
  350. return IIO_VAL_INT;
  351. default:
  352. return -EINVAL;
  353. }
  354. }
  355. static int ad7124_write_raw(struct iio_dev *indio_dev,
  356. struct iio_chan_spec const *chan,
  357. int val, int val2, long info)
  358. {
  359. struct ad7124_state *st = iio_priv(indio_dev);
  360. unsigned int res, gain, full_scale, vref;
  361. switch (info) {
  362. case IIO_CHAN_INFO_SAMP_FREQ:
  363. if (val2 != 0)
  364. return -EINVAL;
  365. return ad7124_set_channel_odr(st, chan->address, val);
  366. case IIO_CHAN_INFO_SCALE:
  367. if (val != 0)
  368. return -EINVAL;
  369. if (st->channel_config[chan->address].bipolar)
  370. full_scale = 1 << (chan->scan_type.realbits - 1);
  371. else
  372. full_scale = 1 << chan->scan_type.realbits;
  373. vref = st->channel_config[chan->address].vref_mv * 1000000LL;
  374. res = DIV_ROUND_CLOSEST(vref, full_scale);
  375. gain = DIV_ROUND_CLOSEST(res, val2);
  376. return ad7124_set_channel_gain(st, chan->address, gain);
  377. case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
  378. if (val2 != 0)
  379. return -EINVAL;
  380. return ad7124_set_3db_filter_freq(st, chan->address, val);
  381. default:
  382. return -EINVAL;
  383. }
  384. }
  385. static int ad7124_reg_access(struct iio_dev *indio_dev,
  386. unsigned int reg,
  387. unsigned int writeval,
  388. unsigned int *readval)
  389. {
  390. struct ad7124_state *st = iio_priv(indio_dev);
  391. int ret;
  392. if (reg >= ARRAY_SIZE(ad7124_reg_size))
  393. return -EINVAL;
  394. if (readval)
  395. ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
  396. readval);
  397. else
  398. ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
  399. writeval);
  400. return ret;
  401. }
  402. static IIO_CONST_ATTR(in_voltage_scale_available,
  403. "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
  404. static struct attribute *ad7124_attributes[] = {
  405. &iio_const_attr_in_voltage_scale_available.dev_attr.attr,
  406. NULL,
  407. };
  408. static const struct attribute_group ad7124_attrs_group = {
  409. .attrs = ad7124_attributes,
  410. };
  411. static const struct iio_info ad7124_info = {
  412. .read_raw = ad7124_read_raw,
  413. .write_raw = ad7124_write_raw,
  414. .debugfs_reg_access = &ad7124_reg_access,
  415. .validate_trigger = ad_sd_validate_trigger,
  416. .attrs = &ad7124_attrs_group,
  417. };
  418. static int ad7124_soft_reset(struct ad7124_state *st)
  419. {
  420. unsigned int readval, timeout;
  421. int ret;
  422. ret = ad_sd_reset(&st->sd, 64);
  423. if (ret < 0)
  424. return ret;
  425. timeout = 100;
  426. do {
  427. ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
  428. if (ret < 0)
  429. return ret;
  430. if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
  431. return 0;
  432. /* The AD7124 requires typically 2ms to power up and settle */
  433. usleep_range(100, 2000);
  434. } while (--timeout);
  435. dev_err(&st->sd.spi->dev, "Soft reset failed\n");
  436. return -EIO;
  437. }
  438. static int ad7124_check_chip_id(struct ad7124_state *st)
  439. {
  440. unsigned int readval, chip_id, silicon_rev;
  441. int ret;
  442. ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval);
  443. if (ret < 0)
  444. return ret;
  445. chip_id = AD7124_DEVICE_ID_GET(readval);
  446. silicon_rev = AD7124_SILICON_REV_GET(readval);
  447. if (chip_id != st->chip_info->chip_id) {
  448. dev_err(&st->sd.spi->dev,
  449. "Chip ID mismatch: expected %u, got %u\n",
  450. st->chip_info->chip_id, chip_id);
  451. return -ENODEV;
  452. }
  453. if (silicon_rev == 0) {
  454. dev_err(&st->sd.spi->dev,
  455. "Silicon revision empty. Chip may not be present\n");
  456. return -ENODEV;
  457. }
  458. return 0;
  459. }
  460. static int ad7124_init_channel_vref(struct ad7124_state *st,
  461. unsigned int channel_number)
  462. {
  463. unsigned int refsel = st->channel_config[channel_number].refsel;
  464. switch (refsel) {
  465. case AD7124_REFIN1:
  466. case AD7124_REFIN2:
  467. case AD7124_AVDD_REF:
  468. if (IS_ERR(st->vref[refsel])) {
  469. dev_err(&st->sd.spi->dev,
  470. "Error, trying to use external voltage reference without a %s regulator.\n",
  471. ad7124_ref_names[refsel]);
  472. return PTR_ERR(st->vref[refsel]);
  473. }
  474. st->channel_config[channel_number].vref_mv =
  475. regulator_get_voltage(st->vref[refsel]);
  476. /* Conversion from uV to mV */
  477. st->channel_config[channel_number].vref_mv /= 1000;
  478. break;
  479. case AD7124_INT_REF:
  480. st->channel_config[channel_number].vref_mv = 2500;
  481. st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
  482. st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
  483. return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL,
  484. 2, st->adc_control);
  485. default:
  486. dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
  487. return -EINVAL;
  488. }
  489. return 0;
  490. }
  491. static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev,
  492. struct device_node *np)
  493. {
  494. struct ad7124_state *st = iio_priv(indio_dev);
  495. struct device_node *child;
  496. struct iio_chan_spec *chan;
  497. struct ad7124_channel_config *chan_config;
  498. unsigned int ain[2], channel = 0, tmp;
  499. int ret;
  500. st->num_channels = of_get_available_child_count(np);
  501. if (!st->num_channels) {
  502. dev_err(indio_dev->dev.parent, "no channel children\n");
  503. return -ENODEV;
  504. }
  505. chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
  506. sizeof(*chan), GFP_KERNEL);
  507. if (!chan)
  508. return -ENOMEM;
  509. chan_config = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
  510. sizeof(*chan_config), GFP_KERNEL);
  511. if (!chan_config)
  512. return -ENOMEM;
  513. indio_dev->channels = chan;
  514. indio_dev->num_channels = st->num_channels;
  515. st->channel_config = chan_config;
  516. for_each_available_child_of_node(np, child) {
  517. ret = of_property_read_u32(child, "reg", &channel);
  518. if (ret)
  519. goto err;
  520. if (channel >= indio_dev->num_channels) {
  521. dev_err(indio_dev->dev.parent,
  522. "Channel index >= number of channels\n");
  523. ret = -EINVAL;
  524. goto err;
  525. }
  526. ret = of_property_read_u32_array(child, "diff-channels",
  527. ain, 2);
  528. if (ret)
  529. goto err;
  530. st->channel_config[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
  531. AD7124_CHANNEL_AINM(ain[1]);
  532. st->channel_config[channel].bipolar =
  533. of_property_read_bool(child, "bipolar");
  534. ret = of_property_read_u32(child, "adi,reference-select", &tmp);
  535. if (ret)
  536. st->channel_config[channel].refsel = AD7124_INT_REF;
  537. else
  538. st->channel_config[channel].refsel = tmp;
  539. st->channel_config[channel].buf_positive =
  540. of_property_read_bool(child, "adi,buffered-positive");
  541. st->channel_config[channel].buf_negative =
  542. of_property_read_bool(child, "adi,buffered-negative");
  543. chan[channel] = ad7124_channel_template;
  544. chan[channel].address = channel;
  545. chan[channel].scan_index = channel;
  546. chan[channel].channel = ain[0];
  547. chan[channel].channel2 = ain[1];
  548. }
  549. return 0;
  550. err:
  551. of_node_put(child);
  552. return ret;
  553. }
  554. static int ad7124_setup(struct ad7124_state *st)
  555. {
  556. unsigned int val, fclk, power_mode;
  557. int i, ret, tmp;
  558. fclk = clk_get_rate(st->mclk);
  559. if (!fclk)
  560. return -EINVAL;
  561. /* The power mode changes the master clock frequency */
  562. power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
  563. ARRAY_SIZE(ad7124_master_clk_freq_hz),
  564. fclk);
  565. if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
  566. ret = clk_set_rate(st->mclk, fclk);
  567. if (ret)
  568. return ret;
  569. }
  570. /* Set the power mode */
  571. st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
  572. st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
  573. ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
  574. if (ret < 0)
  575. return ret;
  576. for (i = 0; i < st->num_channels; i++) {
  577. val = st->channel_config[i].ain | AD7124_CHANNEL_SETUP(i);
  578. ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, val);
  579. if (ret < 0)
  580. return ret;
  581. ret = ad7124_init_channel_vref(st, i);
  582. if (ret < 0)
  583. return ret;
  584. tmp = (st->channel_config[i].buf_positive << 1) +
  585. st->channel_config[i].buf_negative;
  586. val = AD7124_CONFIG_BIPOLAR(st->channel_config[i].bipolar) |
  587. AD7124_CONFIG_REF_SEL(st->channel_config[i].refsel) |
  588. AD7124_CONFIG_IN_BUFF(tmp);
  589. ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(i), 2, val);
  590. if (ret < 0)
  591. return ret;
  592. /*
  593. * 9.38 SPS is the minimum output data rate supported
  594. * regardless of the selected power mode. Round it up to 10 and
  595. * set all the enabled channels to this default value.
  596. */
  597. ret = ad7124_set_channel_odr(st, i, 10);
  598. }
  599. return ret;
  600. }
  601. static void ad7124_reg_disable(void *r)
  602. {
  603. regulator_disable(r);
  604. }
  605. static int ad7124_probe(struct spi_device *spi)
  606. {
  607. const struct ad7124_chip_info *info;
  608. struct ad7124_state *st;
  609. struct iio_dev *indio_dev;
  610. int i, ret;
  611. info = of_device_get_match_data(&spi->dev);
  612. if (!info)
  613. return -ENODEV;
  614. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  615. if (!indio_dev)
  616. return -ENOMEM;
  617. st = iio_priv(indio_dev);
  618. st->chip_info = info;
  619. ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
  620. spi_set_drvdata(spi, indio_dev);
  621. indio_dev->name = st->chip_info->name;
  622. indio_dev->modes = INDIO_DIRECT_MODE;
  623. indio_dev->info = &ad7124_info;
  624. ret = ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node);
  625. if (ret < 0)
  626. return ret;
  627. for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
  628. if (i == AD7124_INT_REF)
  629. continue;
  630. st->vref[i] = devm_regulator_get_optional(&spi->dev,
  631. ad7124_ref_names[i]);
  632. if (PTR_ERR(st->vref[i]) == -ENODEV)
  633. continue;
  634. else if (IS_ERR(st->vref[i]))
  635. return PTR_ERR(st->vref[i]);
  636. ret = regulator_enable(st->vref[i]);
  637. if (ret)
  638. return ret;
  639. ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable,
  640. st->vref[i]);
  641. if (ret)
  642. return ret;
  643. }
  644. st->mclk = devm_clk_get(&spi->dev, "mclk");
  645. if (IS_ERR(st->mclk))
  646. return PTR_ERR(st->mclk);
  647. ret = clk_prepare_enable(st->mclk);
  648. if (ret < 0)
  649. return ret;
  650. ret = ad7124_soft_reset(st);
  651. if (ret < 0)
  652. goto error_clk_disable_unprepare;
  653. ret = ad7124_check_chip_id(st);
  654. if (ret)
  655. goto error_clk_disable_unprepare;
  656. ret = ad7124_setup(st);
  657. if (ret < 0)
  658. goto error_clk_disable_unprepare;
  659. ret = ad_sd_setup_buffer_and_trigger(indio_dev);
  660. if (ret < 0)
  661. goto error_clk_disable_unprepare;
  662. ret = iio_device_register(indio_dev);
  663. if (ret < 0) {
  664. dev_err(&spi->dev, "Failed to register iio device\n");
  665. goto error_remove_trigger;
  666. }
  667. return 0;
  668. error_remove_trigger:
  669. ad_sd_cleanup_buffer_and_trigger(indio_dev);
  670. error_clk_disable_unprepare:
  671. clk_disable_unprepare(st->mclk);
  672. return ret;
  673. }
  674. static int ad7124_remove(struct spi_device *spi)
  675. {
  676. struct iio_dev *indio_dev = spi_get_drvdata(spi);
  677. struct ad7124_state *st = iio_priv(indio_dev);
  678. iio_device_unregister(indio_dev);
  679. ad_sd_cleanup_buffer_and_trigger(indio_dev);
  680. clk_disable_unprepare(st->mclk);
  681. return 0;
  682. }
  683. static const struct of_device_id ad7124_of_match[] = {
  684. { .compatible = "adi,ad7124-4",
  685. .data = &ad7124_chip_info_tbl[ID_AD7124_4], },
  686. { .compatible = "adi,ad7124-8",
  687. .data = &ad7124_chip_info_tbl[ID_AD7124_8], },
  688. { },
  689. };
  690. MODULE_DEVICE_TABLE(of, ad7124_of_match);
  691. static struct spi_driver ad71124_driver = {
  692. .driver = {
  693. .name = "ad7124",
  694. .of_match_table = ad7124_of_match,
  695. },
  696. .probe = ad7124_probe,
  697. .remove = ad7124_remove,
  698. };
  699. module_spi_driver(ad71124_driver);
  700. MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
  701. MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
  702. MODULE_LICENSE("GPL");