ab8500-gpadc.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) ST-Ericsson SA 2010
  4. *
  5. * Author: Arun R Murthy <arun.murthy@stericsson.com>
  6. * Author: Daniel Willerud <daniel.willerud@stericsson.com>
  7. * Author: Johan Palsson <johan.palsson@stericsson.com>
  8. * Author: M'boumba Cedric Madianga
  9. * Author: Linus Walleij <linus.walleij@linaro.org>
  10. *
  11. * AB8500 General Purpose ADC driver. The AB8500 uses reference voltages:
  12. * VinVADC, and VADC relative to GND to do its job. It monitors main and backup
  13. * battery voltages, AC (mains) voltage, USB cable voltage, as well as voltages
  14. * representing the temperature of the chip die and battery, accessory
  15. * detection by resistance measurements using relative voltages and GSM burst
  16. * information.
  17. *
  18. * Some of the voltages are measured on external pins on the IC, such as
  19. * battery temperature or "ADC aux" 1 and 2. Other voltages are internal rails
  20. * from other parts of the ASIC such as main charger voltage, main and battery
  21. * backup voltage or USB VBUS voltage. For this reason drivers for other
  22. * parts of the system are required to obtain handles to the ADC to do work
  23. * for them and the IIO driver provides arbitration among these consumers.
  24. */
  25. #include <linux/init.h>
  26. #include <linux/bits.h>
  27. #include <linux/iio/iio.h>
  28. #include <linux/iio/sysfs.h>
  29. #include <linux/device.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/spinlock.h>
  32. #include <linux/delay.h>
  33. #include <linux/pm_runtime.h>
  34. #include <linux/platform_device.h>
  35. #include <linux/completion.h>
  36. #include <linux/regulator/consumer.h>
  37. #include <linux/random.h>
  38. #include <linux/err.h>
  39. #include <linux/slab.h>
  40. #include <linux/mfd/abx500.h>
  41. #include <linux/mfd/abx500/ab8500.h>
  42. /* GPADC register offsets and bit definitions */
  43. #define AB8500_GPADC_CTRL1_REG 0x00
  44. /* GPADC control register 1 bits */
  45. #define AB8500_GPADC_CTRL1_DISABLE 0x00
  46. #define AB8500_GPADC_CTRL1_ENABLE BIT(0)
  47. #define AB8500_GPADC_CTRL1_TRIG_ENA BIT(1)
  48. #define AB8500_GPADC_CTRL1_START_SW_CONV BIT(2)
  49. #define AB8500_GPADC_CTRL1_BTEMP_PULL_UP BIT(3)
  50. /* 0 = use rising edge, 1 = use falling edge */
  51. #define AB8500_GPADC_CTRL1_TRIG_EDGE BIT(4)
  52. /* 0 = use VTVOUT, 1 = use VRTC as pull-up supply for battery temp NTC */
  53. #define AB8500_GPADC_CTRL1_PUPSUPSEL BIT(5)
  54. #define AB8500_GPADC_CTRL1_BUF_ENA BIT(6)
  55. #define AB8500_GPADC_CTRL1_ICHAR_ENA BIT(7)
  56. #define AB8500_GPADC_CTRL2_REG 0x01
  57. #define AB8500_GPADC_CTRL3_REG 0x02
  58. /*
  59. * GPADC control register 2 and 3 bits
  60. * the bit layout is the same for SW and HW conversion set-up
  61. */
  62. #define AB8500_GPADC_CTRL2_AVG_1 0x00
  63. #define AB8500_GPADC_CTRL2_AVG_4 BIT(5)
  64. #define AB8500_GPADC_CTRL2_AVG_8 BIT(6)
  65. #define AB8500_GPADC_CTRL2_AVG_16 (BIT(5) | BIT(6))
  66. enum ab8500_gpadc_channel {
  67. AB8500_GPADC_CHAN_UNUSED = 0x00,
  68. AB8500_GPADC_CHAN_BAT_CTRL = 0x01,
  69. AB8500_GPADC_CHAN_BAT_TEMP = 0x02,
  70. /* This is not used on AB8505 */
  71. AB8500_GPADC_CHAN_MAIN_CHARGER = 0x03,
  72. AB8500_GPADC_CHAN_ACC_DET_1 = 0x04,
  73. AB8500_GPADC_CHAN_ACC_DET_2 = 0x05,
  74. AB8500_GPADC_CHAN_ADC_AUX_1 = 0x06,
  75. AB8500_GPADC_CHAN_ADC_AUX_2 = 0x07,
  76. AB8500_GPADC_CHAN_VBAT_A = 0x08,
  77. AB8500_GPADC_CHAN_VBUS = 0x09,
  78. AB8500_GPADC_CHAN_MAIN_CHARGER_CURRENT = 0x0a,
  79. AB8500_GPADC_CHAN_USB_CHARGER_CURRENT = 0x0b,
  80. AB8500_GPADC_CHAN_BACKUP_BAT = 0x0c,
  81. /* Only on AB8505 */
  82. AB8505_GPADC_CHAN_DIE_TEMP = 0x0d,
  83. AB8500_GPADC_CHAN_ID = 0x0e,
  84. AB8500_GPADC_CHAN_INTERNAL_TEST_1 = 0x0f,
  85. AB8500_GPADC_CHAN_INTERNAL_TEST_2 = 0x10,
  86. AB8500_GPADC_CHAN_INTERNAL_TEST_3 = 0x11,
  87. /* FIXME: Applicable to all ASIC variants? */
  88. AB8500_GPADC_CHAN_XTAL_TEMP = 0x12,
  89. AB8500_GPADC_CHAN_VBAT_TRUE_MEAS = 0x13,
  90. /* FIXME: Doesn't seem to work with pure AB8500 */
  91. AB8500_GPADC_CHAN_BAT_CTRL_AND_IBAT = 0x1c,
  92. AB8500_GPADC_CHAN_VBAT_MEAS_AND_IBAT = 0x1d,
  93. AB8500_GPADC_CHAN_VBAT_TRUE_MEAS_AND_IBAT = 0x1e,
  94. AB8500_GPADC_CHAN_BAT_TEMP_AND_IBAT = 0x1f,
  95. /*
  96. * Virtual channel used only for ibat conversion to ampere.
  97. * Battery current conversion (ibat) cannot be requested as a
  98. * single conversion but it is always requested in combination
  99. * with other input requests.
  100. */
  101. AB8500_GPADC_CHAN_IBAT_VIRTUAL = 0xFF,
  102. };
  103. #define AB8500_GPADC_AUTO_TIMER_REG 0x03
  104. #define AB8500_GPADC_STAT_REG 0x04
  105. #define AB8500_GPADC_STAT_BUSY BIT(0)
  106. #define AB8500_GPADC_MANDATAL_REG 0x05
  107. #define AB8500_GPADC_MANDATAH_REG 0x06
  108. #define AB8500_GPADC_AUTODATAL_REG 0x07
  109. #define AB8500_GPADC_AUTODATAH_REG 0x08
  110. #define AB8500_GPADC_MUX_CTRL_REG 0x09
  111. #define AB8540_GPADC_MANDATA2L_REG 0x09
  112. #define AB8540_GPADC_MANDATA2H_REG 0x0A
  113. #define AB8540_GPADC_APEAAX_REG 0x10
  114. #define AB8540_GPADC_APEAAT_REG 0x11
  115. #define AB8540_GPADC_APEAAM_REG 0x12
  116. #define AB8540_GPADC_APEAAH_REG 0x13
  117. #define AB8540_GPADC_APEAAL_REG 0x14
  118. /*
  119. * OTP register offsets
  120. * Bank : 0x15
  121. */
  122. #define AB8500_GPADC_CAL_1 0x0F
  123. #define AB8500_GPADC_CAL_2 0x10
  124. #define AB8500_GPADC_CAL_3 0x11
  125. #define AB8500_GPADC_CAL_4 0x12
  126. #define AB8500_GPADC_CAL_5 0x13
  127. #define AB8500_GPADC_CAL_6 0x14
  128. #define AB8500_GPADC_CAL_7 0x15
  129. /* New calibration for 8540 */
  130. #define AB8540_GPADC_OTP4_REG_7 0x38
  131. #define AB8540_GPADC_OTP4_REG_6 0x39
  132. #define AB8540_GPADC_OTP4_REG_5 0x3A
  133. #define AB8540_GPADC_DIS_ZERO 0x00
  134. #define AB8540_GPADC_EN_VBIAS_XTAL_TEMP 0x02
  135. /* GPADC constants from AB8500 spec, UM0836 */
  136. #define AB8500_ADC_RESOLUTION 1024
  137. #define AB8500_ADC_CH_BTEMP_MIN 0
  138. #define AB8500_ADC_CH_BTEMP_MAX 1350
  139. #define AB8500_ADC_CH_DIETEMP_MIN 0
  140. #define AB8500_ADC_CH_DIETEMP_MAX 1350
  141. #define AB8500_ADC_CH_CHG_V_MIN 0
  142. #define AB8500_ADC_CH_CHG_V_MAX 20030
  143. #define AB8500_ADC_CH_ACCDET2_MIN 0
  144. #define AB8500_ADC_CH_ACCDET2_MAX 2500
  145. #define AB8500_ADC_CH_VBAT_MIN 2300
  146. #define AB8500_ADC_CH_VBAT_MAX 4800
  147. #define AB8500_ADC_CH_CHG_I_MIN 0
  148. #define AB8500_ADC_CH_CHG_I_MAX 1500
  149. #define AB8500_ADC_CH_BKBAT_MIN 0
  150. #define AB8500_ADC_CH_BKBAT_MAX 3200
  151. /* GPADC constants from AB8540 spec */
  152. #define AB8500_ADC_CH_IBAT_MIN (-6000) /* mA range measured by ADC for ibat */
  153. #define AB8500_ADC_CH_IBAT_MAX 6000
  154. #define AB8500_ADC_CH_IBAT_MIN_V (-60) /* mV range measured by ADC for ibat */
  155. #define AB8500_ADC_CH_IBAT_MAX_V 60
  156. #define AB8500_GPADC_IBAT_VDROP_L (-56) /* mV */
  157. #define AB8500_GPADC_IBAT_VDROP_H 56
  158. /* This is used to not lose precision when dividing to get gain and offset */
  159. #define AB8500_GPADC_CALIB_SCALE 1000
  160. /*
  161. * Number of bits shift used to not lose precision
  162. * when dividing to get ibat gain.
  163. */
  164. #define AB8500_GPADC_CALIB_SHIFT_IBAT 20
  165. /* Time in ms before disabling regulator */
  166. #define AB8500_GPADC_AUTOSUSPEND_DELAY 1
  167. #define AB8500_GPADC_CONVERSION_TIME 500 /* ms */
  168. enum ab8500_cal_channels {
  169. AB8500_CAL_VMAIN = 0,
  170. AB8500_CAL_BTEMP,
  171. AB8500_CAL_VBAT,
  172. AB8500_CAL_IBAT,
  173. AB8500_CAL_NR,
  174. };
  175. /**
  176. * struct ab8500_adc_cal_data - Table for storing gain and offset for the
  177. * calibrated ADC channels
  178. * @gain: Gain of the ADC channel
  179. * @offset: Offset of the ADC channel
  180. * @otp_calib_hi: Calibration from OTP
  181. * @otp_calib_lo: Calibration from OTP
  182. */
  183. struct ab8500_adc_cal_data {
  184. s64 gain;
  185. s64 offset;
  186. u16 otp_calib_hi;
  187. u16 otp_calib_lo;
  188. };
  189. /**
  190. * struct ab8500_gpadc_chan_info - per-channel GPADC info
  191. * @name: name of the channel
  192. * @id: the internal AB8500 ID number for the channel
  193. * @hardware_control: indicate that we want to use hardware ADC control
  194. * on this channel, the default is software ADC control. Hardware control
  195. * is normally only used to test the battery voltage during GSM bursts
  196. * and needs a hardware trigger on the GPADCTrig pin of the ASIC.
  197. * @falling_edge: indicate that we want to trigger on falling edge
  198. * rather than rising edge, rising edge is the default
  199. * @avg_sample: how many samples to average: must be 1, 4, 8 or 16.
  200. * @trig_timer: how long to wait for the trigger, in 32kHz periods:
  201. * 0 .. 255 periods
  202. */
  203. struct ab8500_gpadc_chan_info {
  204. const char *name;
  205. u8 id;
  206. bool hardware_control;
  207. bool falling_edge;
  208. u8 avg_sample;
  209. u8 trig_timer;
  210. };
  211. /**
  212. * struct ab8500_gpadc - AB8500 GPADC device information
  213. * @dev: pointer to the containing device
  214. * @ab8500: pointer to the parent AB8500 device
  215. * @chans: internal per-channel information container
  216. * @nchans: number of channels
  217. * @complete: pointer to the completion that indicates
  218. * the completion of an gpadc conversion cycle
  219. * @vddadc: pointer to the regulator supplying VDDADC
  220. * @irq_sw: interrupt number that is used by gpadc for software ADC conversion
  221. * @irq_hw: interrupt number that is used by gpadc for hardware ADC conversion
  222. * @cal_data: array of ADC calibration data structs
  223. */
  224. struct ab8500_gpadc {
  225. struct device *dev;
  226. struct ab8500 *ab8500;
  227. struct ab8500_gpadc_chan_info *chans;
  228. unsigned int nchans;
  229. struct completion complete;
  230. struct regulator *vddadc;
  231. int irq_sw;
  232. int irq_hw;
  233. struct ab8500_adc_cal_data cal_data[AB8500_CAL_NR];
  234. };
  235. static struct ab8500_gpadc_chan_info *
  236. ab8500_gpadc_get_channel(struct ab8500_gpadc *gpadc, u8 chan)
  237. {
  238. struct ab8500_gpadc_chan_info *ch;
  239. int i;
  240. for (i = 0; i < gpadc->nchans; i++) {
  241. ch = &gpadc->chans[i];
  242. if (ch->id == chan)
  243. break;
  244. }
  245. if (i == gpadc->nchans)
  246. return NULL;
  247. return ch;
  248. }
  249. /**
  250. * ab8500_gpadc_ad_to_voltage() - Convert a raw ADC value to a voltage
  251. * @gpadc: GPADC instance
  252. * @ch: the sampled channel this raw value is coming from
  253. * @ad_value: the raw value
  254. */
  255. static int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc,
  256. enum ab8500_gpadc_channel ch,
  257. int ad_value)
  258. {
  259. int res;
  260. switch (ch) {
  261. case AB8500_GPADC_CHAN_MAIN_CHARGER:
  262. /* No calibration data available: just interpolate */
  263. if (!gpadc->cal_data[AB8500_CAL_VMAIN].gain) {
  264. res = AB8500_ADC_CH_CHG_V_MIN + (AB8500_ADC_CH_CHG_V_MAX -
  265. AB8500_ADC_CH_CHG_V_MIN) * ad_value /
  266. AB8500_ADC_RESOLUTION;
  267. break;
  268. }
  269. /* Here we can use calibration */
  270. res = (int) (ad_value * gpadc->cal_data[AB8500_CAL_VMAIN].gain +
  271. gpadc->cal_data[AB8500_CAL_VMAIN].offset) / AB8500_GPADC_CALIB_SCALE;
  272. break;
  273. case AB8500_GPADC_CHAN_BAT_CTRL:
  274. case AB8500_GPADC_CHAN_BAT_TEMP:
  275. case AB8500_GPADC_CHAN_ACC_DET_1:
  276. case AB8500_GPADC_CHAN_ADC_AUX_1:
  277. case AB8500_GPADC_CHAN_ADC_AUX_2:
  278. case AB8500_GPADC_CHAN_XTAL_TEMP:
  279. /* No calibration data available: just interpolate */
  280. if (!gpadc->cal_data[AB8500_CAL_BTEMP].gain) {
  281. res = AB8500_ADC_CH_BTEMP_MIN + (AB8500_ADC_CH_BTEMP_MAX -
  282. AB8500_ADC_CH_BTEMP_MIN) * ad_value /
  283. AB8500_ADC_RESOLUTION;
  284. break;
  285. }
  286. /* Here we can use calibration */
  287. res = (int) (ad_value * gpadc->cal_data[AB8500_CAL_BTEMP].gain +
  288. gpadc->cal_data[AB8500_CAL_BTEMP].offset) / AB8500_GPADC_CALIB_SCALE;
  289. break;
  290. case AB8500_GPADC_CHAN_VBAT_A:
  291. case AB8500_GPADC_CHAN_VBAT_TRUE_MEAS:
  292. /* No calibration data available: just interpolate */
  293. if (!gpadc->cal_data[AB8500_CAL_VBAT].gain) {
  294. res = AB8500_ADC_CH_VBAT_MIN + (AB8500_ADC_CH_VBAT_MAX -
  295. AB8500_ADC_CH_VBAT_MIN) * ad_value /
  296. AB8500_ADC_RESOLUTION;
  297. break;
  298. }
  299. /* Here we can use calibration */
  300. res = (int) (ad_value * gpadc->cal_data[AB8500_CAL_VBAT].gain +
  301. gpadc->cal_data[AB8500_CAL_VBAT].offset) / AB8500_GPADC_CALIB_SCALE;
  302. break;
  303. case AB8505_GPADC_CHAN_DIE_TEMP:
  304. res = AB8500_ADC_CH_DIETEMP_MIN +
  305. (AB8500_ADC_CH_DIETEMP_MAX - AB8500_ADC_CH_DIETEMP_MIN) * ad_value /
  306. AB8500_ADC_RESOLUTION;
  307. break;
  308. case AB8500_GPADC_CHAN_ACC_DET_2:
  309. res = AB8500_ADC_CH_ACCDET2_MIN +
  310. (AB8500_ADC_CH_ACCDET2_MAX - AB8500_ADC_CH_ACCDET2_MIN) * ad_value /
  311. AB8500_ADC_RESOLUTION;
  312. break;
  313. case AB8500_GPADC_CHAN_VBUS:
  314. res = AB8500_ADC_CH_CHG_V_MIN +
  315. (AB8500_ADC_CH_CHG_V_MAX - AB8500_ADC_CH_CHG_V_MIN) * ad_value /
  316. AB8500_ADC_RESOLUTION;
  317. break;
  318. case AB8500_GPADC_CHAN_MAIN_CHARGER_CURRENT:
  319. case AB8500_GPADC_CHAN_USB_CHARGER_CURRENT:
  320. res = AB8500_ADC_CH_CHG_I_MIN +
  321. (AB8500_ADC_CH_CHG_I_MAX - AB8500_ADC_CH_CHG_I_MIN) * ad_value /
  322. AB8500_ADC_RESOLUTION;
  323. break;
  324. case AB8500_GPADC_CHAN_BACKUP_BAT:
  325. res = AB8500_ADC_CH_BKBAT_MIN +
  326. (AB8500_ADC_CH_BKBAT_MAX - AB8500_ADC_CH_BKBAT_MIN) * ad_value /
  327. AB8500_ADC_RESOLUTION;
  328. break;
  329. case AB8500_GPADC_CHAN_IBAT_VIRTUAL:
  330. /* No calibration data available: just interpolate */
  331. if (!gpadc->cal_data[AB8500_CAL_IBAT].gain) {
  332. res = AB8500_ADC_CH_IBAT_MIN + (AB8500_ADC_CH_IBAT_MAX -
  333. AB8500_ADC_CH_IBAT_MIN) * ad_value /
  334. AB8500_ADC_RESOLUTION;
  335. break;
  336. }
  337. /* Here we can use calibration */
  338. res = (int) (ad_value * gpadc->cal_data[AB8500_CAL_IBAT].gain +
  339. gpadc->cal_data[AB8500_CAL_IBAT].offset)
  340. >> AB8500_GPADC_CALIB_SHIFT_IBAT;
  341. break;
  342. default:
  343. dev_err(gpadc->dev,
  344. "unknown channel ID: %d, not possible to convert\n",
  345. ch);
  346. res = -EINVAL;
  347. break;
  348. }
  349. return res;
  350. }
  351. static int ab8500_gpadc_read(struct ab8500_gpadc *gpadc,
  352. const struct ab8500_gpadc_chan_info *ch,
  353. int *ibat)
  354. {
  355. int ret;
  356. int looplimit = 0;
  357. unsigned long completion_timeout;
  358. u8 val;
  359. u8 low_data, high_data, low_data2, high_data2;
  360. u8 ctrl1;
  361. u8 ctrl23;
  362. unsigned int delay_min = 0;
  363. unsigned int delay_max = 0;
  364. u8 data_low_addr, data_high_addr;
  365. if (!gpadc)
  366. return -ENODEV;
  367. /* check if conversion is supported */
  368. if ((gpadc->irq_sw <= 0) && !ch->hardware_control)
  369. return -ENOTSUPP;
  370. if ((gpadc->irq_hw <= 0) && ch->hardware_control)
  371. return -ENOTSUPP;
  372. /* Enable vddadc by grabbing PM runtime */
  373. pm_runtime_get_sync(gpadc->dev);
  374. /* Check if ADC is not busy, lock and proceed */
  375. do {
  376. ret = abx500_get_register_interruptible(gpadc->dev,
  377. AB8500_GPADC, AB8500_GPADC_STAT_REG, &val);
  378. if (ret < 0)
  379. goto out;
  380. if (!(val & AB8500_GPADC_STAT_BUSY))
  381. break;
  382. msleep(20);
  383. } while (++looplimit < 10);
  384. if (looplimit >= 10 && (val & AB8500_GPADC_STAT_BUSY)) {
  385. dev_err(gpadc->dev, "gpadc_conversion: GPADC busy");
  386. ret = -EINVAL;
  387. goto out;
  388. }
  389. /* Enable GPADC */
  390. ctrl1 = AB8500_GPADC_CTRL1_ENABLE;
  391. /* Select the channel source and set average samples */
  392. switch (ch->avg_sample) {
  393. case 1:
  394. ctrl23 = ch->id | AB8500_GPADC_CTRL2_AVG_1;
  395. break;
  396. case 4:
  397. ctrl23 = ch->id | AB8500_GPADC_CTRL2_AVG_4;
  398. break;
  399. case 8:
  400. ctrl23 = ch->id | AB8500_GPADC_CTRL2_AVG_8;
  401. break;
  402. default:
  403. ctrl23 = ch->id | AB8500_GPADC_CTRL2_AVG_16;
  404. break;
  405. }
  406. if (ch->hardware_control) {
  407. ret = abx500_set_register_interruptible(gpadc->dev,
  408. AB8500_GPADC, AB8500_GPADC_CTRL3_REG, ctrl23);
  409. ctrl1 |= AB8500_GPADC_CTRL1_TRIG_ENA;
  410. if (ch->falling_edge)
  411. ctrl1 |= AB8500_GPADC_CTRL1_TRIG_EDGE;
  412. } else {
  413. ret = abx500_set_register_interruptible(gpadc->dev,
  414. AB8500_GPADC, AB8500_GPADC_CTRL2_REG, ctrl23);
  415. }
  416. if (ret < 0) {
  417. dev_err(gpadc->dev,
  418. "gpadc_conversion: set avg samples failed\n");
  419. goto out;
  420. }
  421. /*
  422. * Enable ADC, buffering, select rising edge and enable ADC path
  423. * charging current sense if it needed, ABB 3.0 needs some special
  424. * treatment too.
  425. */
  426. switch (ch->id) {
  427. case AB8500_GPADC_CHAN_MAIN_CHARGER_CURRENT:
  428. case AB8500_GPADC_CHAN_USB_CHARGER_CURRENT:
  429. ctrl1 |= AB8500_GPADC_CTRL1_BUF_ENA |
  430. AB8500_GPADC_CTRL1_ICHAR_ENA;
  431. break;
  432. case AB8500_GPADC_CHAN_BAT_TEMP:
  433. if (!is_ab8500_2p0_or_earlier(gpadc->ab8500)) {
  434. ctrl1 |= AB8500_GPADC_CTRL1_BUF_ENA |
  435. AB8500_GPADC_CTRL1_BTEMP_PULL_UP;
  436. /*
  437. * Delay might be needed for ABB8500 cut 3.0, if not,
  438. * remove when hardware will be available
  439. */
  440. delay_min = 1000; /* Delay in micro seconds */
  441. delay_max = 10000; /* large range optimises sleepmode */
  442. break;
  443. }
  444. fallthrough;
  445. default:
  446. ctrl1 |= AB8500_GPADC_CTRL1_BUF_ENA;
  447. break;
  448. }
  449. /* Write configuration to control register 1 */
  450. ret = abx500_set_register_interruptible(gpadc->dev,
  451. AB8500_GPADC, AB8500_GPADC_CTRL1_REG, ctrl1);
  452. if (ret < 0) {
  453. dev_err(gpadc->dev,
  454. "gpadc_conversion: set Control register failed\n");
  455. goto out;
  456. }
  457. if (delay_min != 0)
  458. usleep_range(delay_min, delay_max);
  459. if (ch->hardware_control) {
  460. /* Set trigger delay timer */
  461. ret = abx500_set_register_interruptible(gpadc->dev,
  462. AB8500_GPADC, AB8500_GPADC_AUTO_TIMER_REG,
  463. ch->trig_timer);
  464. if (ret < 0) {
  465. dev_err(gpadc->dev,
  466. "gpadc_conversion: trig timer failed\n");
  467. goto out;
  468. }
  469. completion_timeout = 2 * HZ;
  470. data_low_addr = AB8500_GPADC_AUTODATAL_REG;
  471. data_high_addr = AB8500_GPADC_AUTODATAH_REG;
  472. } else {
  473. /* Start SW conversion */
  474. ret = abx500_mask_and_set_register_interruptible(gpadc->dev,
  475. AB8500_GPADC, AB8500_GPADC_CTRL1_REG,
  476. AB8500_GPADC_CTRL1_START_SW_CONV,
  477. AB8500_GPADC_CTRL1_START_SW_CONV);
  478. if (ret < 0) {
  479. dev_err(gpadc->dev,
  480. "gpadc_conversion: start s/w conv failed\n");
  481. goto out;
  482. }
  483. completion_timeout = msecs_to_jiffies(AB8500_GPADC_CONVERSION_TIME);
  484. data_low_addr = AB8500_GPADC_MANDATAL_REG;
  485. data_high_addr = AB8500_GPADC_MANDATAH_REG;
  486. }
  487. /* Wait for completion of conversion */
  488. if (!wait_for_completion_timeout(&gpadc->complete,
  489. completion_timeout)) {
  490. dev_err(gpadc->dev,
  491. "timeout didn't receive GPADC conv interrupt\n");
  492. ret = -EINVAL;
  493. goto out;
  494. }
  495. /* Read the converted RAW data */
  496. ret = abx500_get_register_interruptible(gpadc->dev,
  497. AB8500_GPADC, data_low_addr, &low_data);
  498. if (ret < 0) {
  499. dev_err(gpadc->dev,
  500. "gpadc_conversion: read low data failed\n");
  501. goto out;
  502. }
  503. ret = abx500_get_register_interruptible(gpadc->dev,
  504. AB8500_GPADC, data_high_addr, &high_data);
  505. if (ret < 0) {
  506. dev_err(gpadc->dev,
  507. "gpadc_conversion: read high data failed\n");
  508. goto out;
  509. }
  510. /* Check if double conversion is required */
  511. if ((ch->id == AB8500_GPADC_CHAN_BAT_CTRL_AND_IBAT) ||
  512. (ch->id == AB8500_GPADC_CHAN_VBAT_MEAS_AND_IBAT) ||
  513. (ch->id == AB8500_GPADC_CHAN_VBAT_TRUE_MEAS_AND_IBAT) ||
  514. (ch->id == AB8500_GPADC_CHAN_BAT_TEMP_AND_IBAT)) {
  515. if (ch->hardware_control) {
  516. /* not supported */
  517. ret = -ENOTSUPP;
  518. dev_err(gpadc->dev,
  519. "gpadc_conversion: only SW double conversion supported\n");
  520. goto out;
  521. } else {
  522. /* Read the converted RAW data 2 */
  523. ret = abx500_get_register_interruptible(gpadc->dev,
  524. AB8500_GPADC, AB8540_GPADC_MANDATA2L_REG,
  525. &low_data2);
  526. if (ret < 0) {
  527. dev_err(gpadc->dev,
  528. "gpadc_conversion: read sw low data 2 failed\n");
  529. goto out;
  530. }
  531. ret = abx500_get_register_interruptible(gpadc->dev,
  532. AB8500_GPADC, AB8540_GPADC_MANDATA2H_REG,
  533. &high_data2);
  534. if (ret < 0) {
  535. dev_err(gpadc->dev,
  536. "gpadc_conversion: read sw high data 2 failed\n");
  537. goto out;
  538. }
  539. if (ibat != NULL) {
  540. *ibat = (high_data2 << 8) | low_data2;
  541. } else {
  542. dev_warn(gpadc->dev,
  543. "gpadc_conversion: ibat not stored\n");
  544. }
  545. }
  546. }
  547. /* Disable GPADC */
  548. ret = abx500_set_register_interruptible(gpadc->dev, AB8500_GPADC,
  549. AB8500_GPADC_CTRL1_REG, AB8500_GPADC_CTRL1_DISABLE);
  550. if (ret < 0) {
  551. dev_err(gpadc->dev, "gpadc_conversion: disable gpadc failed\n");
  552. goto out;
  553. }
  554. /* This eventually drops the regulator */
  555. pm_runtime_mark_last_busy(gpadc->dev);
  556. pm_runtime_put_autosuspend(gpadc->dev);
  557. return (high_data << 8) | low_data;
  558. out:
  559. /*
  560. * It has shown to be needed to turn off the GPADC if an error occurs,
  561. * otherwise we might have problem when waiting for the busy bit in the
  562. * GPADC status register to go low. In V1.1 there wait_for_completion
  563. * seems to timeout when waiting for an interrupt.. Not seen in V2.0
  564. */
  565. (void) abx500_set_register_interruptible(gpadc->dev, AB8500_GPADC,
  566. AB8500_GPADC_CTRL1_REG, AB8500_GPADC_CTRL1_DISABLE);
  567. pm_runtime_put(gpadc->dev);
  568. dev_err(gpadc->dev,
  569. "gpadc_conversion: Failed to AD convert channel %d\n", ch->id);
  570. return ret;
  571. }
  572. /**
  573. * ab8500_bm_gpadcconvend_handler() - isr for gpadc conversion completion
  574. * @irq: irq number
  575. * @data: pointer to the data passed during request irq
  576. *
  577. * This is a interrupt service routine for gpadc conversion completion.
  578. * Notifies the gpadc completion is completed and the converted raw value
  579. * can be read from the registers.
  580. * Returns IRQ status(IRQ_HANDLED)
  581. */
  582. static irqreturn_t ab8500_bm_gpadcconvend_handler(int irq, void *data)
  583. {
  584. struct ab8500_gpadc *gpadc = data;
  585. complete(&gpadc->complete);
  586. return IRQ_HANDLED;
  587. }
  588. static int otp_cal_regs[] = {
  589. AB8500_GPADC_CAL_1,
  590. AB8500_GPADC_CAL_2,
  591. AB8500_GPADC_CAL_3,
  592. AB8500_GPADC_CAL_4,
  593. AB8500_GPADC_CAL_5,
  594. AB8500_GPADC_CAL_6,
  595. AB8500_GPADC_CAL_7,
  596. };
  597. static int otp4_cal_regs[] = {
  598. AB8540_GPADC_OTP4_REG_7,
  599. AB8540_GPADC_OTP4_REG_6,
  600. AB8540_GPADC_OTP4_REG_5,
  601. };
  602. static void ab8500_gpadc_read_calibration_data(struct ab8500_gpadc *gpadc)
  603. {
  604. int i;
  605. int ret[ARRAY_SIZE(otp_cal_regs)];
  606. u8 gpadc_cal[ARRAY_SIZE(otp_cal_regs)];
  607. int ret_otp4[ARRAY_SIZE(otp4_cal_regs)];
  608. u8 gpadc_otp4[ARRAY_SIZE(otp4_cal_regs)];
  609. int vmain_high, vmain_low;
  610. int btemp_high, btemp_low;
  611. int vbat_high, vbat_low;
  612. int ibat_high, ibat_low;
  613. s64 V_gain, V_offset, V2A_gain, V2A_offset;
  614. /* First we read all OTP registers and store the error code */
  615. for (i = 0; i < ARRAY_SIZE(otp_cal_regs); i++) {
  616. ret[i] = abx500_get_register_interruptible(gpadc->dev,
  617. AB8500_OTP_EMUL, otp_cal_regs[i], &gpadc_cal[i]);
  618. if (ret[i] < 0) {
  619. /* Continue anyway: maybe the other registers are OK */
  620. dev_err(gpadc->dev, "%s: read otp reg 0x%02x failed\n",
  621. __func__, otp_cal_regs[i]);
  622. } else {
  623. /* Put this in the entropy pool as device-unique */
  624. add_device_randomness(&ret[i], sizeof(ret[i]));
  625. }
  626. }
  627. /*
  628. * The ADC calibration data is stored in OTP registers.
  629. * The layout of the calibration data is outlined below and a more
  630. * detailed description can be found in UM0836
  631. *
  632. * vm_h/l = vmain_high/low
  633. * bt_h/l = btemp_high/low
  634. * vb_h/l = vbat_high/low
  635. *
  636. * Data bits 8500/9540:
  637. * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  638. * |.......|.......|.......|.......|.......|.......|.......|.......
  639. * | | vm_h9 | vm_h8
  640. * |.......|.......|.......|.......|.......|.......|.......|.......
  641. * | | vm_h7 | vm_h6 | vm_h5 | vm_h4 | vm_h3 | vm_h2
  642. * |.......|.......|.......|.......|.......|.......|.......|.......
  643. * | vm_h1 | vm_h0 | vm_l4 | vm_l3 | vm_l2 | vm_l1 | vm_l0 | bt_h9
  644. * |.......|.......|.......|.......|.......|.......|.......|.......
  645. * | bt_h8 | bt_h7 | bt_h6 | bt_h5 | bt_h4 | bt_h3 | bt_h2 | bt_h1
  646. * |.......|.......|.......|.......|.......|.......|.......|.......
  647. * | bt_h0 | bt_l4 | bt_l3 | bt_l2 | bt_l1 | bt_l0 | vb_h9 | vb_h8
  648. * |.......|.......|.......|.......|.......|.......|.......|.......
  649. * | vb_h7 | vb_h6 | vb_h5 | vb_h4 | vb_h3 | vb_h2 | vb_h1 | vb_h0
  650. * |.......|.......|.......|.......|.......|.......|.......|.......
  651. * | vb_l5 | vb_l4 | vb_l3 | vb_l2 | vb_l1 | vb_l0 |
  652. * |.......|.......|.......|.......|.......|.......|.......|.......
  653. *
  654. * Data bits 8540:
  655. * OTP2
  656. * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  657. * |.......|.......|.......|.......|.......|.......|.......|.......
  658. * |
  659. * |.......|.......|.......|.......|.......|.......|.......|.......
  660. * | vm_h9 | vm_h8 | vm_h7 | vm_h6 | vm_h5 | vm_h4 | vm_h3 | vm_h2
  661. * |.......|.......|.......|.......|.......|.......|.......|.......
  662. * | vm_h1 | vm_h0 | vm_l4 | vm_l3 | vm_l2 | vm_l1 | vm_l0 | bt_h9
  663. * |.......|.......|.......|.......|.......|.......|.......|.......
  664. * | bt_h8 | bt_h7 | bt_h6 | bt_h5 | bt_h4 | bt_h3 | bt_h2 | bt_h1
  665. * |.......|.......|.......|.......|.......|.......|.......|.......
  666. * | bt_h0 | bt_l4 | bt_l3 | bt_l2 | bt_l1 | bt_l0 | vb_h9 | vb_h8
  667. * |.......|.......|.......|.......|.......|.......|.......|.......
  668. * | vb_h7 | vb_h6 | vb_h5 | vb_h4 | vb_h3 | vb_h2 | vb_h1 | vb_h0
  669. * |.......|.......|.......|.......|.......|.......|.......|.......
  670. * | vb_l5 | vb_l4 | vb_l3 | vb_l2 | vb_l1 | vb_l0 |
  671. * |.......|.......|.......|.......|.......|.......|.......|.......
  672. *
  673. * Data bits 8540:
  674. * OTP4
  675. * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  676. * |.......|.......|.......|.......|.......|.......|.......|.......
  677. * | | ib_h9 | ib_h8 | ib_h7
  678. * |.......|.......|.......|.......|.......|.......|.......|.......
  679. * | ib_h6 | ib_h5 | ib_h4 | ib_h3 | ib_h2 | ib_h1 | ib_h0 | ib_l5
  680. * |.......|.......|.......|.......|.......|.......|.......|.......
  681. * | ib_l4 | ib_l3 | ib_l2 | ib_l1 | ib_l0 |
  682. *
  683. *
  684. * Ideal output ADC codes corresponding to injected input voltages
  685. * during manufacturing is:
  686. *
  687. * vmain_high: Vin = 19500mV / ADC ideal code = 997
  688. * vmain_low: Vin = 315mV / ADC ideal code = 16
  689. * btemp_high: Vin = 1300mV / ADC ideal code = 985
  690. * btemp_low: Vin = 21mV / ADC ideal code = 16
  691. * vbat_high: Vin = 4700mV / ADC ideal code = 982
  692. * vbat_low: Vin = 2380mV / ADC ideal code = 33
  693. */
  694. if (is_ab8540(gpadc->ab8500)) {
  695. /* Calculate gain and offset for VMAIN if all reads succeeded*/
  696. if (!(ret[1] < 0 || ret[2] < 0)) {
  697. vmain_high = (((gpadc_cal[1] & 0xFF) << 2) |
  698. ((gpadc_cal[2] & 0xC0) >> 6));
  699. vmain_low = ((gpadc_cal[2] & 0x3E) >> 1);
  700. gpadc->cal_data[AB8500_CAL_VMAIN].otp_calib_hi =
  701. (u16)vmain_high;
  702. gpadc->cal_data[AB8500_CAL_VMAIN].otp_calib_lo =
  703. (u16)vmain_low;
  704. gpadc->cal_data[AB8500_CAL_VMAIN].gain = AB8500_GPADC_CALIB_SCALE *
  705. (19500 - 315) / (vmain_high - vmain_low);
  706. gpadc->cal_data[AB8500_CAL_VMAIN].offset = AB8500_GPADC_CALIB_SCALE *
  707. 19500 - (AB8500_GPADC_CALIB_SCALE * (19500 - 315) /
  708. (vmain_high - vmain_low)) * vmain_high;
  709. } else {
  710. gpadc->cal_data[AB8500_CAL_VMAIN].gain = 0;
  711. }
  712. /* Read IBAT calibration Data */
  713. for (i = 0; i < ARRAY_SIZE(otp4_cal_regs); i++) {
  714. ret_otp4[i] = abx500_get_register_interruptible(
  715. gpadc->dev, AB8500_OTP_EMUL,
  716. otp4_cal_regs[i], &gpadc_otp4[i]);
  717. if (ret_otp4[i] < 0)
  718. dev_err(gpadc->dev,
  719. "%s: read otp4 reg 0x%02x failed\n",
  720. __func__, otp4_cal_regs[i]);
  721. }
  722. /* Calculate gain and offset for IBAT if all reads succeeded */
  723. if (!(ret_otp4[0] < 0 || ret_otp4[1] < 0 || ret_otp4[2] < 0)) {
  724. ibat_high = (((gpadc_otp4[0] & 0x07) << 7) |
  725. ((gpadc_otp4[1] & 0xFE) >> 1));
  726. ibat_low = (((gpadc_otp4[1] & 0x01) << 5) |
  727. ((gpadc_otp4[2] & 0xF8) >> 3));
  728. gpadc->cal_data[AB8500_CAL_IBAT].otp_calib_hi =
  729. (u16)ibat_high;
  730. gpadc->cal_data[AB8500_CAL_IBAT].otp_calib_lo =
  731. (u16)ibat_low;
  732. V_gain = ((AB8500_GPADC_IBAT_VDROP_H - AB8500_GPADC_IBAT_VDROP_L)
  733. << AB8500_GPADC_CALIB_SHIFT_IBAT) / (ibat_high - ibat_low);
  734. V_offset = (AB8500_GPADC_IBAT_VDROP_H << AB8500_GPADC_CALIB_SHIFT_IBAT) -
  735. (((AB8500_GPADC_IBAT_VDROP_H - AB8500_GPADC_IBAT_VDROP_L) <<
  736. AB8500_GPADC_CALIB_SHIFT_IBAT) / (ibat_high - ibat_low))
  737. * ibat_high;
  738. /*
  739. * Result obtained is in mV (at a scale factor),
  740. * we need to calculate gain and offset to get mA
  741. */
  742. V2A_gain = (AB8500_ADC_CH_IBAT_MAX - AB8500_ADC_CH_IBAT_MIN)/
  743. (AB8500_ADC_CH_IBAT_MAX_V - AB8500_ADC_CH_IBAT_MIN_V);
  744. V2A_offset = ((AB8500_ADC_CH_IBAT_MAX_V * AB8500_ADC_CH_IBAT_MIN -
  745. AB8500_ADC_CH_IBAT_MAX * AB8500_ADC_CH_IBAT_MIN_V)
  746. << AB8500_GPADC_CALIB_SHIFT_IBAT)
  747. / (AB8500_ADC_CH_IBAT_MAX_V - AB8500_ADC_CH_IBAT_MIN_V);
  748. gpadc->cal_data[AB8500_CAL_IBAT].gain =
  749. V_gain * V2A_gain;
  750. gpadc->cal_data[AB8500_CAL_IBAT].offset =
  751. V_offset * V2A_gain + V2A_offset;
  752. } else {
  753. gpadc->cal_data[AB8500_CAL_IBAT].gain = 0;
  754. }
  755. } else {
  756. /* Calculate gain and offset for VMAIN if all reads succeeded */
  757. if (!(ret[0] < 0 || ret[1] < 0 || ret[2] < 0)) {
  758. vmain_high = (((gpadc_cal[0] & 0x03) << 8) |
  759. ((gpadc_cal[1] & 0x3F) << 2) |
  760. ((gpadc_cal[2] & 0xC0) >> 6));
  761. vmain_low = ((gpadc_cal[2] & 0x3E) >> 1);
  762. gpadc->cal_data[AB8500_CAL_VMAIN].otp_calib_hi =
  763. (u16)vmain_high;
  764. gpadc->cal_data[AB8500_CAL_VMAIN].otp_calib_lo =
  765. (u16)vmain_low;
  766. gpadc->cal_data[AB8500_CAL_VMAIN].gain = AB8500_GPADC_CALIB_SCALE *
  767. (19500 - 315) / (vmain_high - vmain_low);
  768. gpadc->cal_data[AB8500_CAL_VMAIN].offset = AB8500_GPADC_CALIB_SCALE *
  769. 19500 - (AB8500_GPADC_CALIB_SCALE * (19500 - 315) /
  770. (vmain_high - vmain_low)) * vmain_high;
  771. } else {
  772. gpadc->cal_data[AB8500_CAL_VMAIN].gain = 0;
  773. }
  774. }
  775. /* Calculate gain and offset for BTEMP if all reads succeeded */
  776. if (!(ret[2] < 0 || ret[3] < 0 || ret[4] < 0)) {
  777. btemp_high = (((gpadc_cal[2] & 0x01) << 9) |
  778. (gpadc_cal[3] << 1) | ((gpadc_cal[4] & 0x80) >> 7));
  779. btemp_low = ((gpadc_cal[4] & 0x7C) >> 2);
  780. gpadc->cal_data[AB8500_CAL_BTEMP].otp_calib_hi = (u16)btemp_high;
  781. gpadc->cal_data[AB8500_CAL_BTEMP].otp_calib_lo = (u16)btemp_low;
  782. gpadc->cal_data[AB8500_CAL_BTEMP].gain =
  783. AB8500_GPADC_CALIB_SCALE * (1300 - 21) / (btemp_high - btemp_low);
  784. gpadc->cal_data[AB8500_CAL_BTEMP].offset = AB8500_GPADC_CALIB_SCALE * 1300 -
  785. (AB8500_GPADC_CALIB_SCALE * (1300 - 21) / (btemp_high - btemp_low))
  786. * btemp_high;
  787. } else {
  788. gpadc->cal_data[AB8500_CAL_BTEMP].gain = 0;
  789. }
  790. /* Calculate gain and offset for VBAT if all reads succeeded */
  791. if (!(ret[4] < 0 || ret[5] < 0 || ret[6] < 0)) {
  792. vbat_high = (((gpadc_cal[4] & 0x03) << 8) | gpadc_cal[5]);
  793. vbat_low = ((gpadc_cal[6] & 0xFC) >> 2);
  794. gpadc->cal_data[AB8500_CAL_VBAT].otp_calib_hi = (u16)vbat_high;
  795. gpadc->cal_data[AB8500_CAL_VBAT].otp_calib_lo = (u16)vbat_low;
  796. gpadc->cal_data[AB8500_CAL_VBAT].gain = AB8500_GPADC_CALIB_SCALE *
  797. (4700 - 2380) / (vbat_high - vbat_low);
  798. gpadc->cal_data[AB8500_CAL_VBAT].offset = AB8500_GPADC_CALIB_SCALE * 4700 -
  799. (AB8500_GPADC_CALIB_SCALE * (4700 - 2380) /
  800. (vbat_high - vbat_low)) * vbat_high;
  801. } else {
  802. gpadc->cal_data[AB8500_CAL_VBAT].gain = 0;
  803. }
  804. }
  805. static int ab8500_gpadc_read_raw(struct iio_dev *indio_dev,
  806. struct iio_chan_spec const *chan,
  807. int *val, int *val2, long mask)
  808. {
  809. struct ab8500_gpadc *gpadc = iio_priv(indio_dev);
  810. const struct ab8500_gpadc_chan_info *ch;
  811. int raw_val;
  812. int processed;
  813. ch = ab8500_gpadc_get_channel(gpadc, chan->address);
  814. if (!ch) {
  815. dev_err(gpadc->dev, "no such channel %lu\n",
  816. chan->address);
  817. return -EINVAL;
  818. }
  819. raw_val = ab8500_gpadc_read(gpadc, ch, NULL);
  820. if (raw_val < 0)
  821. return raw_val;
  822. if (mask == IIO_CHAN_INFO_RAW) {
  823. *val = raw_val;
  824. return IIO_VAL_INT;
  825. }
  826. if (mask == IIO_CHAN_INFO_PROCESSED) {
  827. processed = ab8500_gpadc_ad_to_voltage(gpadc, ch->id, raw_val);
  828. if (processed < 0)
  829. return processed;
  830. /* Return millivolt or milliamps or millicentigrades */
  831. *val = processed;
  832. return IIO_VAL_INT;
  833. }
  834. return -EINVAL;
  835. }
  836. static int ab8500_gpadc_of_xlate(struct iio_dev *indio_dev,
  837. const struct of_phandle_args *iiospec)
  838. {
  839. int i;
  840. for (i = 0; i < indio_dev->num_channels; i++)
  841. if (indio_dev->channels[i].channel == iiospec->args[0])
  842. return i;
  843. return -EINVAL;
  844. }
  845. static const struct iio_info ab8500_gpadc_info = {
  846. .of_xlate = ab8500_gpadc_of_xlate,
  847. .read_raw = ab8500_gpadc_read_raw,
  848. };
  849. #ifdef CONFIG_PM
  850. static int ab8500_gpadc_runtime_suspend(struct device *dev)
  851. {
  852. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  853. struct ab8500_gpadc *gpadc = iio_priv(indio_dev);
  854. regulator_disable(gpadc->vddadc);
  855. return 0;
  856. }
  857. static int ab8500_gpadc_runtime_resume(struct device *dev)
  858. {
  859. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  860. struct ab8500_gpadc *gpadc = iio_priv(indio_dev);
  861. int ret;
  862. ret = regulator_enable(gpadc->vddadc);
  863. if (ret)
  864. dev_err(dev, "Failed to enable vddadc: %d\n", ret);
  865. return ret;
  866. }
  867. #endif
  868. /**
  869. * ab8500_gpadc_parse_channel() - process devicetree channel configuration
  870. * @dev: pointer to containing device
  871. * @np: device tree node for the channel to configure
  872. * @ch: channel info to fill in
  873. * @iio_chan: IIO channel specification to fill in
  874. *
  875. * The devicetree will set up the channel for use with the specific device,
  876. * and define usage for things like AUX GPADC inputs more precisely.
  877. */
  878. static int ab8500_gpadc_parse_channel(struct device *dev,
  879. struct device_node *np,
  880. struct ab8500_gpadc_chan_info *ch,
  881. struct iio_chan_spec *iio_chan)
  882. {
  883. const char *name = np->name;
  884. u32 chan;
  885. int ret;
  886. ret = of_property_read_u32(np, "reg", &chan);
  887. if (ret) {
  888. dev_err(dev, "invalid channel number %s\n", name);
  889. return ret;
  890. }
  891. if (chan > AB8500_GPADC_CHAN_BAT_TEMP_AND_IBAT) {
  892. dev_err(dev, "%s channel number out of range %d\n", name, chan);
  893. return -EINVAL;
  894. }
  895. iio_chan->channel = chan;
  896. iio_chan->datasheet_name = name;
  897. iio_chan->indexed = 1;
  898. iio_chan->address = chan;
  899. iio_chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
  900. BIT(IIO_CHAN_INFO_PROCESSED);
  901. /* Most are voltages (also temperatures), some are currents */
  902. if ((chan == AB8500_GPADC_CHAN_MAIN_CHARGER_CURRENT) ||
  903. (chan == AB8500_GPADC_CHAN_USB_CHARGER_CURRENT))
  904. iio_chan->type = IIO_CURRENT;
  905. else
  906. iio_chan->type = IIO_VOLTAGE;
  907. ch->id = chan;
  908. /* Sensible defaults */
  909. ch->avg_sample = 16;
  910. ch->hardware_control = false;
  911. ch->falling_edge = false;
  912. ch->trig_timer = 0;
  913. return 0;
  914. }
  915. /**
  916. * ab8500_gpadc_parse_channels() - Parse the GPADC channels from DT
  917. * @gpadc: the GPADC to configure the channels for
  918. * @np: device tree node containing the channel configurations
  919. * @chans: the IIO channels we parsed
  920. * @nchans: the number of IIO channels we parsed
  921. */
  922. static int ab8500_gpadc_parse_channels(struct ab8500_gpadc *gpadc,
  923. struct device_node *np,
  924. struct iio_chan_spec **chans_parsed,
  925. unsigned int *nchans_parsed)
  926. {
  927. struct device_node *child;
  928. struct ab8500_gpadc_chan_info *ch;
  929. struct iio_chan_spec *iio_chans;
  930. unsigned int nchans;
  931. int i;
  932. nchans = of_get_available_child_count(np);
  933. if (!nchans) {
  934. dev_err(gpadc->dev, "no channel children\n");
  935. return -ENODEV;
  936. }
  937. dev_info(gpadc->dev, "found %d ADC channels\n", nchans);
  938. iio_chans = devm_kcalloc(gpadc->dev, nchans,
  939. sizeof(*iio_chans), GFP_KERNEL);
  940. if (!iio_chans)
  941. return -ENOMEM;
  942. gpadc->chans = devm_kcalloc(gpadc->dev, nchans,
  943. sizeof(*gpadc->chans), GFP_KERNEL);
  944. if (!gpadc->chans)
  945. return -ENOMEM;
  946. i = 0;
  947. for_each_available_child_of_node(np, child) {
  948. struct iio_chan_spec *iio_chan;
  949. int ret;
  950. ch = &gpadc->chans[i];
  951. iio_chan = &iio_chans[i];
  952. ret = ab8500_gpadc_parse_channel(gpadc->dev, child, ch,
  953. iio_chan);
  954. if (ret) {
  955. of_node_put(child);
  956. return ret;
  957. }
  958. i++;
  959. }
  960. gpadc->nchans = nchans;
  961. *chans_parsed = iio_chans;
  962. *nchans_parsed = nchans;
  963. return 0;
  964. }
  965. static int ab8500_gpadc_probe(struct platform_device *pdev)
  966. {
  967. struct ab8500_gpadc *gpadc;
  968. struct iio_dev *indio_dev;
  969. struct device *dev = &pdev->dev;
  970. struct device_node *np = pdev->dev.of_node;
  971. struct iio_chan_spec *iio_chans;
  972. unsigned int n_iio_chans;
  973. int ret;
  974. indio_dev = devm_iio_device_alloc(dev, sizeof(*gpadc));
  975. if (!indio_dev)
  976. return -ENOMEM;
  977. platform_set_drvdata(pdev, indio_dev);
  978. gpadc = iio_priv(indio_dev);
  979. gpadc->dev = dev;
  980. gpadc->ab8500 = dev_get_drvdata(dev->parent);
  981. ret = ab8500_gpadc_parse_channels(gpadc, np, &iio_chans, &n_iio_chans);
  982. if (ret)
  983. return ret;
  984. gpadc->irq_sw = platform_get_irq_byname(pdev, "SW_CONV_END");
  985. if (gpadc->irq_sw < 0) {
  986. dev_err(dev, "failed to get platform sw_conv_end irq\n");
  987. return gpadc->irq_sw;
  988. }
  989. gpadc->irq_hw = platform_get_irq_byname(pdev, "HW_CONV_END");
  990. if (gpadc->irq_hw < 0) {
  991. dev_err(dev, "failed to get platform hw_conv_end irq\n");
  992. return gpadc->irq_hw;
  993. }
  994. /* Initialize completion used to notify completion of conversion */
  995. init_completion(&gpadc->complete);
  996. /* Request interrupts */
  997. ret = devm_request_threaded_irq(dev, gpadc->irq_sw, NULL,
  998. ab8500_bm_gpadcconvend_handler, IRQF_NO_SUSPEND | IRQF_ONESHOT,
  999. "ab8500-gpadc-sw", gpadc);
  1000. if (ret < 0) {
  1001. dev_err(dev,
  1002. "failed to request sw conversion irq %d\n",
  1003. gpadc->irq_sw);
  1004. return ret;
  1005. }
  1006. ret = devm_request_threaded_irq(dev, gpadc->irq_hw, NULL,
  1007. ab8500_bm_gpadcconvend_handler, IRQF_NO_SUSPEND | IRQF_ONESHOT,
  1008. "ab8500-gpadc-hw", gpadc);
  1009. if (ret < 0) {
  1010. dev_err(dev,
  1011. "Failed to request hw conversion irq: %d\n",
  1012. gpadc->irq_hw);
  1013. return ret;
  1014. }
  1015. /* The VTVout LDO used to power the AB8500 GPADC */
  1016. gpadc->vddadc = devm_regulator_get(dev, "vddadc");
  1017. if (IS_ERR(gpadc->vddadc)) {
  1018. ret = PTR_ERR(gpadc->vddadc);
  1019. dev_err(dev, "failed to get vddadc\n");
  1020. return ret;
  1021. }
  1022. ret = regulator_enable(gpadc->vddadc);
  1023. if (ret) {
  1024. dev_err(dev, "failed to enable vddadc: %d\n", ret);
  1025. return ret;
  1026. }
  1027. /* Enable runtime PM */
  1028. pm_runtime_get_noresume(dev);
  1029. pm_runtime_set_active(dev);
  1030. pm_runtime_enable(dev);
  1031. pm_runtime_set_autosuspend_delay(dev, AB8500_GPADC_AUTOSUSPEND_DELAY);
  1032. pm_runtime_use_autosuspend(dev);
  1033. ab8500_gpadc_read_calibration_data(gpadc);
  1034. pm_runtime_put(dev);
  1035. indio_dev->name = "ab8500-gpadc";
  1036. indio_dev->modes = INDIO_DIRECT_MODE;
  1037. indio_dev->info = &ab8500_gpadc_info;
  1038. indio_dev->channels = iio_chans;
  1039. indio_dev->num_channels = n_iio_chans;
  1040. ret = devm_iio_device_register(dev, indio_dev);
  1041. if (ret)
  1042. goto out_dis_pm;
  1043. return 0;
  1044. out_dis_pm:
  1045. pm_runtime_get_sync(dev);
  1046. pm_runtime_put_noidle(dev);
  1047. pm_runtime_disable(dev);
  1048. regulator_disable(gpadc->vddadc);
  1049. return ret;
  1050. }
  1051. static int ab8500_gpadc_remove(struct platform_device *pdev)
  1052. {
  1053. struct iio_dev *indio_dev = platform_get_drvdata(pdev);
  1054. struct ab8500_gpadc *gpadc = iio_priv(indio_dev);
  1055. pm_runtime_get_sync(gpadc->dev);
  1056. pm_runtime_put_noidle(gpadc->dev);
  1057. pm_runtime_disable(gpadc->dev);
  1058. regulator_disable(gpadc->vddadc);
  1059. return 0;
  1060. }
  1061. static const struct dev_pm_ops ab8500_gpadc_pm_ops = {
  1062. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  1063. pm_runtime_force_resume)
  1064. SET_RUNTIME_PM_OPS(ab8500_gpadc_runtime_suspend,
  1065. ab8500_gpadc_runtime_resume,
  1066. NULL)
  1067. };
  1068. static struct platform_driver ab8500_gpadc_driver = {
  1069. .probe = ab8500_gpadc_probe,
  1070. .remove = ab8500_gpadc_remove,
  1071. .driver = {
  1072. .name = "ab8500-gpadc",
  1073. .pm = &ab8500_gpadc_pm_ops,
  1074. },
  1075. };
  1076. builtin_platform_driver(ab8500_gpadc_driver);