sl82c105.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * SL82C105/Winbond 553 IDE driver
  4. *
  5. * Maintainer unknown.
  6. *
  7. * Drive tuning added from Rebel.com's kernel sources
  8. * -- Russell King (15/11/98) linux@arm.linux.org.uk
  9. *
  10. * Merge in Russell's HW workarounds, fix various problems
  11. * with the timing registers setup.
  12. * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
  13. *
  14. * Copyright (C) 2006-2007,2009 MontaVista Software, Inc. <source@mvista.com>
  15. * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
  16. */
  17. #include <linux/types.h>
  18. #include <linux/module.h>
  19. #include <linux/kernel.h>
  20. #include <linux/pci.h>
  21. #include <linux/ide.h>
  22. #include <asm/io.h>
  23. #define DRV_NAME "sl82c105"
  24. /*
  25. * SL82C105 PCI config register 0x40 bits.
  26. */
  27. #define CTRL_IDE_IRQB (1 << 30)
  28. #define CTRL_IDE_IRQA (1 << 28)
  29. #define CTRL_LEGIRQ (1 << 11)
  30. #define CTRL_P1F16 (1 << 5)
  31. #define CTRL_P1EN (1 << 4)
  32. #define CTRL_P0F16 (1 << 1)
  33. #define CTRL_P0EN (1 << 0)
  34. /*
  35. * Convert a PIO mode and cycle time to the required on/off times
  36. * for the interface. This has protection against runaway timings.
  37. */
  38. static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio)
  39. {
  40. struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
  41. unsigned int cmd_on, cmd_off;
  42. u8 iordy = 0;
  43. cmd_on = (t->active + 29) / 30;
  44. cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30;
  45. if (cmd_on == 0)
  46. cmd_on = 1;
  47. if (cmd_off == 0)
  48. cmd_off = 1;
  49. if (ide_pio_need_iordy(drive, pio))
  50. iordy = 0x40;
  51. return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy;
  52. }
  53. /*
  54. * Configure the chipset for PIO mode.
  55. */
  56. static void sl82c105_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  57. {
  58. struct pci_dev *dev = to_pci_dev(hwif->dev);
  59. unsigned long timings = (unsigned long)ide_get_drivedata(drive);
  60. int reg = 0x44 + drive->dn * 4;
  61. u16 drv_ctrl;
  62. const u8 pio = drive->pio_mode - XFER_PIO_0;
  63. drv_ctrl = get_pio_timings(drive, pio);
  64. /*
  65. * Store the PIO timings so that we can restore them
  66. * in case DMA will be turned off...
  67. */
  68. timings &= 0xffff0000;
  69. timings |= drv_ctrl;
  70. ide_set_drivedata(drive, (void *)timings);
  71. pci_write_config_word(dev, reg, drv_ctrl);
  72. pci_read_config_word (dev, reg, &drv_ctrl);
  73. printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
  74. ide_xfer_verbose(pio + XFER_PIO_0),
  75. ide_pio_cycle_time(drive, pio), drv_ctrl);
  76. }
  77. /*
  78. * Configure the chipset for DMA mode.
  79. */
  80. static void sl82c105_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  81. {
  82. static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
  83. unsigned long timings = (unsigned long)ide_get_drivedata(drive);
  84. u16 drv_ctrl;
  85. const u8 speed = drive->dma_mode;
  86. drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
  87. /*
  88. * Store the DMA timings so that we can actually program
  89. * them when DMA will be turned on...
  90. */
  91. timings &= 0x0000ffff;
  92. timings |= (unsigned long)drv_ctrl << 16;
  93. ide_set_drivedata(drive, (void *)timings);
  94. }
  95. static int sl82c105_test_irq(ide_hwif_t *hwif)
  96. {
  97. struct pci_dev *dev = to_pci_dev(hwif->dev);
  98. u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
  99. pci_read_config_dword(dev, 0x40, &val);
  100. return (val & mask) ? 1 : 0;
  101. }
  102. /*
  103. * The SL82C105 holds off all IDE interrupts while in DMA mode until
  104. * all DMA activity is completed. Sometimes this causes problems (eg,
  105. * when the drive wants to report an error condition).
  106. *
  107. * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller
  108. * state machine. We need to kick this to work around various bugs.
  109. */
  110. static inline void sl82c105_reset_host(struct pci_dev *dev)
  111. {
  112. u16 val;
  113. pci_read_config_word(dev, 0x7e, &val);
  114. pci_write_config_word(dev, 0x7e, val | (1 << 2));
  115. pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
  116. }
  117. /*
  118. * If we get an IRQ timeout, it might be that the DMA state machine
  119. * got confused. Fix from Todd Inglett. Details from Winbond.
  120. *
  121. * This function is called when the IDE timer expires, the drive
  122. * indicates that it is READY, and we were waiting for DMA to complete.
  123. */
  124. static void sl82c105_dma_lost_irq(ide_drive_t *drive)
  125. {
  126. ide_hwif_t *hwif = drive->hwif;
  127. struct pci_dev *dev = to_pci_dev(hwif->dev);
  128. u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
  129. u8 dma_cmd;
  130. printk(KERN_WARNING "sl82c105: lost IRQ, resetting host\n");
  131. /*
  132. * Check the raw interrupt from the drive.
  133. */
  134. pci_read_config_dword(dev, 0x40, &val);
  135. if (val & mask)
  136. printk(KERN_INFO "sl82c105: drive was requesting IRQ, "
  137. "but host lost it\n");
  138. /*
  139. * Was DMA enabled? If so, disable it - we're resetting the
  140. * host. The IDE layer will be handling the drive for us.
  141. */
  142. dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
  143. if (dma_cmd & 1) {
  144. outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
  145. printk(KERN_INFO "sl82c105: DMA was enabled\n");
  146. }
  147. sl82c105_reset_host(dev);
  148. }
  149. /*
  150. * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
  151. * Winbond recommend that the DMA state machine is reset prior to
  152. * setting the bus master DMA enable bit.
  153. *
  154. * The generic IDE core will have disabled the BMEN bit before this
  155. * function is called.
  156. */
  157. static void sl82c105_dma_start(ide_drive_t *drive)
  158. {
  159. ide_hwif_t *hwif = drive->hwif;
  160. struct pci_dev *dev = to_pci_dev(hwif->dev);
  161. int reg = 0x44 + drive->dn * 4;
  162. pci_write_config_word(dev, reg,
  163. (unsigned long)ide_get_drivedata(drive) >> 16);
  164. sl82c105_reset_host(dev);
  165. ide_dma_start(drive);
  166. }
  167. static void sl82c105_dma_clear(ide_drive_t *drive)
  168. {
  169. struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  170. sl82c105_reset_host(dev);
  171. }
  172. static int sl82c105_dma_end(ide_drive_t *drive)
  173. {
  174. struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  175. int reg = 0x44 + drive->dn * 4;
  176. int ret = ide_dma_end(drive);
  177. pci_write_config_word(dev, reg,
  178. (unsigned long)ide_get_drivedata(drive));
  179. return ret;
  180. }
  181. /*
  182. * ATA reset will clear the 16 bits mode in the control
  183. * register, we need to reprogram it
  184. */
  185. static void sl82c105_resetproc(ide_drive_t *drive)
  186. {
  187. struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  188. u32 val;
  189. pci_read_config_dword(dev, 0x40, &val);
  190. val |= (CTRL_P1F16 | CTRL_P0F16);
  191. pci_write_config_dword(dev, 0x40, val);
  192. }
  193. /*
  194. * Return the revision of the Winbond bridge
  195. * which this function is part of.
  196. */
  197. static u8 sl82c105_bridge_revision(struct pci_dev *dev)
  198. {
  199. struct pci_dev *bridge;
  200. /*
  201. * The bridge should be part of the same device, but function 0.
  202. */
  203. bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus),
  204. dev->bus->number,
  205. PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
  206. if (!bridge)
  207. return -1;
  208. /*
  209. * Make sure it is a Winbond 553 and is an ISA bridge.
  210. */
  211. if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
  212. bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
  213. bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
  214. pci_dev_put(bridge);
  215. return -1;
  216. }
  217. /*
  218. * We need to find function 0's revision, not function 1
  219. */
  220. pci_dev_put(bridge);
  221. return bridge->revision;
  222. }
  223. /*
  224. * Enable the PCI device
  225. *
  226. * --BenH: It's arch fixup code that should enable channels that
  227. * have not been enabled by firmware. I decided we can still enable
  228. * channel 0 here at least, but channel 1 has to be enabled by
  229. * firmware or arch code. We still set both to 16 bits mode.
  230. */
  231. static int init_chipset_sl82c105(struct pci_dev *dev)
  232. {
  233. u32 val;
  234. pci_read_config_dword(dev, 0x40, &val);
  235. val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
  236. pci_write_config_dword(dev, 0x40, val);
  237. return 0;
  238. }
  239. static const struct ide_port_ops sl82c105_port_ops = {
  240. .set_pio_mode = sl82c105_set_pio_mode,
  241. .set_dma_mode = sl82c105_set_dma_mode,
  242. .resetproc = sl82c105_resetproc,
  243. .test_irq = sl82c105_test_irq,
  244. };
  245. static const struct ide_dma_ops sl82c105_dma_ops = {
  246. .dma_host_set = ide_dma_host_set,
  247. .dma_setup = ide_dma_setup,
  248. .dma_start = sl82c105_dma_start,
  249. .dma_end = sl82c105_dma_end,
  250. .dma_test_irq = ide_dma_test_irq,
  251. .dma_lost_irq = sl82c105_dma_lost_irq,
  252. .dma_timer_expiry = ide_dma_sff_timer_expiry,
  253. .dma_clear = sl82c105_dma_clear,
  254. .dma_sff_read_status = ide_dma_sff_read_status,
  255. };
  256. static const struct ide_port_info sl82c105_chipset = {
  257. .name = DRV_NAME,
  258. .init_chipset = init_chipset_sl82c105,
  259. .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
  260. .port_ops = &sl82c105_port_ops,
  261. .dma_ops = &sl82c105_dma_ops,
  262. .host_flags = IDE_HFLAG_IO_32BIT |
  263. IDE_HFLAG_UNMASK_IRQS |
  264. IDE_HFLAG_SERIALIZE_DMA |
  265. IDE_HFLAG_NO_AUTODMA,
  266. .pio_mask = ATA_PIO5,
  267. .mwdma_mask = ATA_MWDMA2,
  268. };
  269. static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  270. {
  271. struct ide_port_info d = sl82c105_chipset;
  272. u8 rev = sl82c105_bridge_revision(dev);
  273. if (rev <= 5) {
  274. /*
  275. * Never ever EVER under any circumstances enable
  276. * DMA when the bridge is this old.
  277. */
  278. printk(KERN_INFO DRV_NAME ": Winbond W83C553 bridge "
  279. "revision %d, BM-DMA disabled\n", rev);
  280. d.dma_ops = NULL;
  281. d.mwdma_mask = 0;
  282. d.host_flags &= ~IDE_HFLAG_SERIALIZE_DMA;
  283. }
  284. return ide_pci_init_one(dev, &d, NULL);
  285. }
  286. static const struct pci_device_id sl82c105_pci_tbl[] = {
  287. { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0 },
  288. { 0, },
  289. };
  290. MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
  291. static struct pci_driver sl82c105_pci_driver = {
  292. .name = "W82C105_IDE",
  293. .id_table = sl82c105_pci_tbl,
  294. .probe = sl82c105_init_one,
  295. .remove = ide_pci_remove,
  296. .suspend = ide_pci_suspend,
  297. .resume = ide_pci_resume,
  298. };
  299. static int __init sl82c105_ide_init(void)
  300. {
  301. return ide_pci_register_driver(&sl82c105_pci_driver);
  302. }
  303. static void __exit sl82c105_ide_exit(void)
  304. {
  305. pci_unregister_driver(&sl82c105_pci_driver);
  306. }
  307. module_init(sl82c105_ide_init);
  308. module_exit(sl82c105_ide_exit);
  309. MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
  310. MODULE_LICENSE("GPL");