sis5513.c 18 KB

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  1. /*
  2. * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
  3. * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
  4. * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
  5. * Copyright (C) 2007-2009 Bartlomiej Zolnierkiewicz
  6. *
  7. * May be copied or modified under the terms of the GNU General Public License
  8. *
  9. *
  10. * Thanks :
  11. *
  12. * SiS Taiwan : for direct support and hardware.
  13. * Daniela Engert : for initial ATA100 advices and numerous others.
  14. * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
  15. * for checking code correctness, providing patches.
  16. *
  17. *
  18. * Original tests and design on the SiS620 chipset.
  19. * ATA100 tests and design on the SiS735 chipset.
  20. * ATA16/33 support from specs
  21. * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
  22. * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
  23. *
  24. * Documentation:
  25. * SiS chipset documentation available under NDA to companies only
  26. * (not to individuals).
  27. */
  28. /*
  29. * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
  30. * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
  31. * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
  32. *
  33. * Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
  34. * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
  35. * can figure out that we have a more modern and more capable 5513 by looking
  36. * for the respective NorthBridge IDs.
  37. *
  38. * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
  39. * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
  40. * ID, while the now ATA-133 capable 5513 still has the same PCI ID.
  41. * Fortunately the 5513 can be 'unmasked' by fiddling with some config space
  42. * bits, changing its device id to the true one - 5517 for 961 and 5518 for
  43. * 962/963.
  44. */
  45. #include <linux/types.h>
  46. #include <linux/module.h>
  47. #include <linux/kernel.h>
  48. #include <linux/pci.h>
  49. #include <linux/init.h>
  50. #include <linux/ide.h>
  51. #define DRV_NAME "sis5513"
  52. /* registers layout and init values are chipset family dependent */
  53. #undef ATA_16
  54. #define ATA_16 0x01
  55. #define ATA_33 0x02
  56. #define ATA_66 0x03
  57. #define ATA_100a 0x04 /* SiS730/SiS550 is ATA100 with ATA66 layout */
  58. #define ATA_100 0x05
  59. #define ATA_133a 0x06 /* SiS961b with 133 support */
  60. #define ATA_133 0x07 /* SiS962/963 */
  61. static u8 chipset_family;
  62. /*
  63. * Devices supported
  64. */
  65. static const struct {
  66. const char *name;
  67. u16 host_id;
  68. u8 chipset_family;
  69. u8 flags;
  70. } SiSHostChipInfo[] = {
  71. { "SiS968", PCI_DEVICE_ID_SI_968, ATA_133 },
  72. { "SiS966", PCI_DEVICE_ID_SI_966, ATA_133 },
  73. { "SiS965", PCI_DEVICE_ID_SI_965, ATA_133 },
  74. { "SiS745", PCI_DEVICE_ID_SI_745, ATA_100 },
  75. { "SiS735", PCI_DEVICE_ID_SI_735, ATA_100 },
  76. { "SiS733", PCI_DEVICE_ID_SI_733, ATA_100 },
  77. { "SiS635", PCI_DEVICE_ID_SI_635, ATA_100 },
  78. { "SiS633", PCI_DEVICE_ID_SI_633, ATA_100 },
  79. { "SiS730", PCI_DEVICE_ID_SI_730, ATA_100a },
  80. { "SiS550", PCI_DEVICE_ID_SI_550, ATA_100a },
  81. { "SiS640", PCI_DEVICE_ID_SI_640, ATA_66 },
  82. { "SiS630", PCI_DEVICE_ID_SI_630, ATA_66 },
  83. { "SiS620", PCI_DEVICE_ID_SI_620, ATA_66 },
  84. { "SiS540", PCI_DEVICE_ID_SI_540, ATA_66 },
  85. { "SiS530", PCI_DEVICE_ID_SI_530, ATA_66 },
  86. { "SiS5600", PCI_DEVICE_ID_SI_5600, ATA_33 },
  87. { "SiS5598", PCI_DEVICE_ID_SI_5598, ATA_33 },
  88. { "SiS5597", PCI_DEVICE_ID_SI_5597, ATA_33 },
  89. { "SiS5591/2", PCI_DEVICE_ID_SI_5591, ATA_33 },
  90. { "SiS5582", PCI_DEVICE_ID_SI_5582, ATA_33 },
  91. { "SiS5581", PCI_DEVICE_ID_SI_5581, ATA_33 },
  92. { "SiS5596", PCI_DEVICE_ID_SI_5596, ATA_16 },
  93. { "SiS5571", PCI_DEVICE_ID_SI_5571, ATA_16 },
  94. { "SiS5517", PCI_DEVICE_ID_SI_5517, ATA_16 },
  95. { "SiS551x", PCI_DEVICE_ID_SI_5511, ATA_16 },
  96. };
  97. /* Cycle time bits and values vary across chip dma capabilities
  98. These three arrays hold the register layout and the values to set.
  99. Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
  100. /* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
  101. static u8 cycle_time_offset[] = { 0, 0, 5, 4, 4, 0, 0 };
  102. static u8 cycle_time_range[] = { 0, 0, 2, 3, 3, 4, 4 };
  103. static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
  104. { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
  105. { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
  106. { 3, 2, 1, 0, 0, 0, 0 }, /* ATA_33 */
  107. { 7, 5, 3, 2, 1, 0, 0 }, /* ATA_66 */
  108. { 7, 5, 3, 2, 1, 0, 0 }, /* ATA_100a (730 specific),
  109. different cycle_time range and offset */
  110. { 11, 7, 5, 4, 2, 1, 0 }, /* ATA_100 */
  111. { 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133a (earliest 691 southbridges) */
  112. { 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133 */
  113. };
  114. /* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
  115. See SiS962 data sheet for more detail */
  116. static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
  117. { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
  118. { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
  119. { 2, 1, 1, 0, 0, 0, 0 },
  120. { 4, 3, 2, 1, 0, 0, 0 },
  121. { 4, 3, 2, 1, 0, 0, 0 },
  122. { 6, 4, 3, 1, 1, 1, 0 },
  123. { 9, 6, 4, 2, 2, 2, 2 },
  124. { 9, 6, 4, 2, 2, 2, 2 },
  125. };
  126. /* Initialize time, Active time, Recovery time vary across
  127. IDE clock settings. These 3 arrays hold the register value
  128. for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
  129. static u8 ini_time_value[][8] = {
  130. { 0, 0, 0, 0, 0, 0, 0, 0 },
  131. { 0, 0, 0, 0, 0, 0, 0, 0 },
  132. { 2, 1, 0, 0, 0, 1, 0, 0 },
  133. { 4, 3, 1, 1, 1, 3, 1, 1 },
  134. { 4, 3, 1, 1, 1, 3, 1, 1 },
  135. { 6, 4, 2, 2, 2, 4, 2, 2 },
  136. { 9, 6, 3, 3, 3, 6, 3, 3 },
  137. { 9, 6, 3, 3, 3, 6, 3, 3 },
  138. };
  139. static u8 act_time_value[][8] = {
  140. { 0, 0, 0, 0, 0, 0, 0, 0 },
  141. { 0, 0, 0, 0, 0, 0, 0, 0 },
  142. { 9, 9, 9, 2, 2, 7, 2, 2 },
  143. { 19, 19, 19, 5, 4, 14, 5, 4 },
  144. { 19, 19, 19, 5, 4, 14, 5, 4 },
  145. { 28, 28, 28, 7, 6, 21, 7, 6 },
  146. { 38, 38, 38, 10, 9, 28, 10, 9 },
  147. { 38, 38, 38, 10, 9, 28, 10, 9 },
  148. };
  149. static u8 rco_time_value[][8] = {
  150. { 0, 0, 0, 0, 0, 0, 0, 0 },
  151. { 0, 0, 0, 0, 0, 0, 0, 0 },
  152. { 9, 2, 0, 2, 0, 7, 1, 1 },
  153. { 19, 5, 1, 5, 2, 16, 3, 2 },
  154. { 19, 5, 1, 5, 2, 16, 3, 2 },
  155. { 30, 9, 3, 9, 4, 25, 6, 4 },
  156. { 40, 12, 4, 12, 5, 34, 12, 5 },
  157. { 40, 12, 4, 12, 5, 34, 12, 5 },
  158. };
  159. /*
  160. * Printing configuration
  161. */
  162. /* Used for chipset type printing at boot time */
  163. static char *chipset_capability[] = {
  164. "ATA", "ATA 16",
  165. "ATA 33", "ATA 66",
  166. "ATA 100 (1st gen)", "ATA 100 (2nd gen)",
  167. "ATA 133 (1st gen)", "ATA 133 (2nd gen)"
  168. };
  169. /*
  170. * Configuration functions
  171. */
  172. static u8 sis_ata133_get_base(ide_drive_t *drive)
  173. {
  174. struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  175. u32 reg54 = 0;
  176. pci_read_config_dword(dev, 0x54, &reg54);
  177. return ((reg54 & 0x40000000) ? 0x70 : 0x40) + drive->dn * 4;
  178. }
  179. static void sis_ata16_program_timings(ide_drive_t *drive, const u8 mode)
  180. {
  181. struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  182. u16 t1 = 0;
  183. u8 drive_pci = 0x40 + drive->dn * 2;
  184. const u16 pio_timings[] = { 0x000, 0x607, 0x404, 0x303, 0x301 };
  185. const u16 mwdma_timings[] = { 0x008, 0x302, 0x301 };
  186. pci_read_config_word(dev, drive_pci, &t1);
  187. /* clear active/recovery timings */
  188. t1 &= ~0x070f;
  189. if (mode >= XFER_MW_DMA_0) {
  190. if (chipset_family > ATA_16)
  191. t1 &= ~0x8000; /* disable UDMA */
  192. t1 |= mwdma_timings[mode - XFER_MW_DMA_0];
  193. } else
  194. t1 |= pio_timings[mode - XFER_PIO_0];
  195. pci_write_config_word(dev, drive_pci, t1);
  196. }
  197. static void sis_ata100_program_timings(ide_drive_t *drive, const u8 mode)
  198. {
  199. struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  200. u8 t1, drive_pci = 0x40 + drive->dn * 2;
  201. /* timing bits: 7:4 active 3:0 recovery */
  202. const u8 pio_timings[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
  203. const u8 mwdma_timings[] = { 0x08, 0x32, 0x31 };
  204. if (mode >= XFER_MW_DMA_0) {
  205. u8 t2 = 0;
  206. pci_read_config_byte(dev, drive_pci, &t2);
  207. t2 &= ~0x80; /* disable UDMA */
  208. pci_write_config_byte(dev, drive_pci, t2);
  209. t1 = mwdma_timings[mode - XFER_MW_DMA_0];
  210. } else
  211. t1 = pio_timings[mode - XFER_PIO_0];
  212. pci_write_config_byte(dev, drive_pci + 1, t1);
  213. }
  214. static void sis_ata133_program_timings(ide_drive_t *drive, const u8 mode)
  215. {
  216. struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  217. u32 t1 = 0;
  218. u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
  219. pci_read_config_dword(dev, drive_pci, &t1);
  220. t1 &= 0xc0c00fff;
  221. clk = (t1 & 0x08) ? ATA_133 : ATA_100;
  222. if (mode >= XFER_MW_DMA_0) {
  223. t1 &= ~0x04; /* disable UDMA */
  224. idx = mode - XFER_MW_DMA_0 + 5;
  225. } else
  226. idx = mode - XFER_PIO_0;
  227. t1 |= ini_time_value[clk][idx] << 12;
  228. t1 |= act_time_value[clk][idx] << 16;
  229. t1 |= rco_time_value[clk][idx] << 24;
  230. pci_write_config_dword(dev, drive_pci, t1);
  231. }
  232. static void sis_program_timings(ide_drive_t *drive, const u8 mode)
  233. {
  234. if (chipset_family < ATA_100) /* ATA_16/33/66/100a */
  235. sis_ata16_program_timings(drive, mode);
  236. else if (chipset_family < ATA_133) /* ATA_100/133a */
  237. sis_ata100_program_timings(drive, mode);
  238. else /* ATA_133 */
  239. sis_ata133_program_timings(drive, mode);
  240. }
  241. static void config_drive_art_rwp(ide_drive_t *drive)
  242. {
  243. ide_hwif_t *hwif = drive->hwif;
  244. struct pci_dev *dev = to_pci_dev(hwif->dev);
  245. u8 reg4bh = 0;
  246. u8 rw_prefetch = 0;
  247. pci_read_config_byte(dev, 0x4b, &reg4bh);
  248. rw_prefetch = reg4bh & ~(0x11 << drive->dn);
  249. if (drive->media == ide_disk)
  250. rw_prefetch |= 0x11 << drive->dn;
  251. if (reg4bh != rw_prefetch)
  252. pci_write_config_byte(dev, 0x4b, rw_prefetch);
  253. }
  254. static void sis_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  255. {
  256. config_drive_art_rwp(drive);
  257. sis_program_timings(drive, drive->pio_mode);
  258. }
  259. static void sis_ata133_program_udma_timings(ide_drive_t *drive, const u8 mode)
  260. {
  261. struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  262. u32 regdw = 0;
  263. u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
  264. pci_read_config_dword(dev, drive_pci, &regdw);
  265. regdw |= 0x04;
  266. regdw &= 0xfffff00f;
  267. /* check if ATA133 enable */
  268. clk = (regdw & 0x08) ? ATA_133 : ATA_100;
  269. idx = mode - XFER_UDMA_0;
  270. regdw |= cycle_time_value[clk][idx] << 4;
  271. regdw |= cvs_time_value[clk][idx] << 8;
  272. pci_write_config_dword(dev, drive_pci, regdw);
  273. }
  274. static void sis_ata33_program_udma_timings(ide_drive_t *drive, const u8 mode)
  275. {
  276. struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  277. u8 drive_pci = 0x40 + drive->dn * 2, reg = 0, i = chipset_family;
  278. pci_read_config_byte(dev, drive_pci + 1, &reg);
  279. /* force the UDMA bit on if we want to use UDMA */
  280. reg |= 0x80;
  281. /* clean reg cycle time bits */
  282. reg &= ~((0xff >> (8 - cycle_time_range[i])) << cycle_time_offset[i]);
  283. /* set reg cycle time bits */
  284. reg |= cycle_time_value[i][mode - XFER_UDMA_0] << cycle_time_offset[i];
  285. pci_write_config_byte(dev, drive_pci + 1, reg);
  286. }
  287. static void sis_program_udma_timings(ide_drive_t *drive, const u8 mode)
  288. {
  289. if (chipset_family >= ATA_133) /* ATA_133 */
  290. sis_ata133_program_udma_timings(drive, mode);
  291. else /* ATA_33/66/100a/100/133a */
  292. sis_ata33_program_udma_timings(drive, mode);
  293. }
  294. static void sis_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  295. {
  296. const u8 speed = drive->dma_mode;
  297. if (speed >= XFER_UDMA_0)
  298. sis_program_udma_timings(drive, speed);
  299. else
  300. sis_program_timings(drive, speed);
  301. }
  302. static u8 sis_ata133_udma_filter(ide_drive_t *drive)
  303. {
  304. struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  305. u32 regdw = 0;
  306. u8 drive_pci = sis_ata133_get_base(drive);
  307. pci_read_config_dword(dev, drive_pci, &regdw);
  308. /* if ATA133 disable, we should not set speed above UDMA5 */
  309. return (regdw & 0x08) ? ATA_UDMA6 : ATA_UDMA5;
  310. }
  311. static int sis_find_family(struct pci_dev *dev)
  312. {
  313. struct pci_dev *host;
  314. int i = 0;
  315. chipset_family = 0;
  316. for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {
  317. host = pci_get_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);
  318. if (!host)
  319. continue;
  320. chipset_family = SiSHostChipInfo[i].chipset_family;
  321. /* Special case for SiS630 : 630S/ET is ATA_100a */
  322. if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
  323. if (host->revision >= 0x30)
  324. chipset_family = ATA_100a;
  325. }
  326. pci_dev_put(host);
  327. printk(KERN_INFO DRV_NAME " %s: %s %s controller\n",
  328. pci_name(dev), SiSHostChipInfo[i].name,
  329. chipset_capability[chipset_family]);
  330. }
  331. if (!chipset_family) { /* Belongs to pci-quirks */
  332. u32 idemisc;
  333. u16 trueid;
  334. /* Disable ID masking and register remapping */
  335. pci_read_config_dword(dev, 0x54, &idemisc);
  336. pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
  337. pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
  338. pci_write_config_dword(dev, 0x54, idemisc);
  339. if (trueid == 0x5518) {
  340. printk(KERN_INFO DRV_NAME " %s: SiS 962/963 MuTIOL IDE UDMA133 controller\n",
  341. pci_name(dev));
  342. chipset_family = ATA_133;
  343. /* Check for 5513 compatibility mapping
  344. * We must use this, else the port enabled code will fail,
  345. * as it expects the enablebits at 0x4a.
  346. */
  347. if ((idemisc & 0x40000000) == 0) {
  348. pci_write_config_dword(dev, 0x54, idemisc | 0x40000000);
  349. printk(KERN_INFO DRV_NAME " %s: Switching to 5513 register mapping\n",
  350. pci_name(dev));
  351. }
  352. }
  353. }
  354. if (!chipset_family) { /* Belongs to pci-quirks */
  355. struct pci_dev *lpc_bridge;
  356. u16 trueid;
  357. u8 prefctl;
  358. u8 idecfg;
  359. pci_read_config_byte(dev, 0x4a, &idecfg);
  360. pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
  361. pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
  362. pci_write_config_byte(dev, 0x4a, idecfg);
  363. if (trueid == 0x5517) { /* SiS 961/961B */
  364. lpc_bridge = pci_get_slot(dev->bus, 0x10); /* Bus 0, Dev 2, Fn 0 */
  365. pci_read_config_byte(dev, 0x49, &prefctl);
  366. pci_dev_put(lpc_bridge);
  367. if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
  368. printk(KERN_INFO DRV_NAME " %s: SiS 961B MuTIOL IDE UDMA133 controller\n",
  369. pci_name(dev));
  370. chipset_family = ATA_133a;
  371. } else {
  372. printk(KERN_INFO DRV_NAME " %s: SiS 961 MuTIOL IDE UDMA100 controller\n",
  373. pci_name(dev));
  374. chipset_family = ATA_100;
  375. }
  376. }
  377. }
  378. return chipset_family;
  379. }
  380. static int init_chipset_sis5513(struct pci_dev *dev)
  381. {
  382. /* Make general config ops here
  383. 1/ tell IDE channels to operate in Compatibility mode only
  384. 2/ tell old chips to allow per drive IDE timings */
  385. u8 reg;
  386. u16 regw;
  387. switch (chipset_family) {
  388. case ATA_133:
  389. /* SiS962 operation mode */
  390. pci_read_config_word(dev, 0x50, &regw);
  391. if (regw & 0x08)
  392. pci_write_config_word(dev, 0x50, regw&0xfff7);
  393. pci_read_config_word(dev, 0x52, &regw);
  394. if (regw & 0x08)
  395. pci_write_config_word(dev, 0x52, regw&0xfff7);
  396. break;
  397. case ATA_133a:
  398. case ATA_100:
  399. /* Fixup latency */
  400. pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
  401. /* Set compatibility bit */
  402. pci_read_config_byte(dev, 0x49, &reg);
  403. if (!(reg & 0x01))
  404. pci_write_config_byte(dev, 0x49, reg|0x01);
  405. break;
  406. case ATA_100a:
  407. case ATA_66:
  408. /* Fixup latency */
  409. pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
  410. /* On ATA_66 chips the bit was elsewhere */
  411. pci_read_config_byte(dev, 0x52, &reg);
  412. if (!(reg & 0x04))
  413. pci_write_config_byte(dev, 0x52, reg|0x04);
  414. break;
  415. case ATA_33:
  416. /* On ATA_33 we didn't have a single bit to set */
  417. pci_read_config_byte(dev, 0x09, &reg);
  418. if ((reg & 0x0f) != 0x00)
  419. pci_write_config_byte(dev, 0x09, reg&0xf0);
  420. fallthrough;
  421. case ATA_16:
  422. /* force per drive recovery and active timings
  423. needed on ATA_33 and below chips */
  424. pci_read_config_byte(dev, 0x52, &reg);
  425. if (!(reg & 0x08))
  426. pci_write_config_byte(dev, 0x52, reg|0x08);
  427. break;
  428. }
  429. return 0;
  430. }
  431. struct sis_laptop {
  432. u16 device;
  433. u16 subvendor;
  434. u16 subdevice;
  435. };
  436. static const struct sis_laptop sis_laptop[] = {
  437. /* devid, subvendor, subdev */
  438. { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
  439. { 0x5513, 0x1734, 0x105f }, /* FSC Amilo A1630 */
  440. { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
  441. /* end marker */
  442. { 0, }
  443. };
  444. static u8 sis_cable_detect(ide_hwif_t *hwif)
  445. {
  446. struct pci_dev *pdev = to_pci_dev(hwif->dev);
  447. const struct sis_laptop *lap = &sis_laptop[0];
  448. u8 ata66 = 0;
  449. while (lap->device) {
  450. if (lap->device == pdev->device &&
  451. lap->subvendor == pdev->subsystem_vendor &&
  452. lap->subdevice == pdev->subsystem_device)
  453. return ATA_CBL_PATA40_SHORT;
  454. lap++;
  455. }
  456. if (chipset_family >= ATA_133) {
  457. u16 regw = 0;
  458. u16 reg_addr = hwif->channel ? 0x52: 0x50;
  459. pci_read_config_word(pdev, reg_addr, &regw);
  460. ata66 = (regw & 0x8000) ? 0 : 1;
  461. } else if (chipset_family >= ATA_66) {
  462. u8 reg48h = 0;
  463. u8 mask = hwif->channel ? 0x20 : 0x10;
  464. pci_read_config_byte(pdev, 0x48, &reg48h);
  465. ata66 = (reg48h & mask) ? 0 : 1;
  466. }
  467. return ata66 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
  468. }
  469. static const struct ide_port_ops sis_port_ops = {
  470. .set_pio_mode = sis_set_pio_mode,
  471. .set_dma_mode = sis_set_dma_mode,
  472. .cable_detect = sis_cable_detect,
  473. };
  474. static const struct ide_port_ops sis_ata133_port_ops = {
  475. .set_pio_mode = sis_set_pio_mode,
  476. .set_dma_mode = sis_set_dma_mode,
  477. .udma_filter = sis_ata133_udma_filter,
  478. .cable_detect = sis_cable_detect,
  479. };
  480. static const struct ide_port_info sis5513_chipset = {
  481. .name = DRV_NAME,
  482. .init_chipset = init_chipset_sis5513,
  483. .enablebits = { {0x4a, 0x02, 0x02}, {0x4a, 0x04, 0x04} },
  484. .host_flags = IDE_HFLAG_NO_AUTODMA,
  485. .pio_mask = ATA_PIO4,
  486. .mwdma_mask = ATA_MWDMA2,
  487. };
  488. static int sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  489. {
  490. struct ide_port_info d = sis5513_chipset;
  491. u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f };
  492. int rc;
  493. rc = pci_enable_device(dev);
  494. if (rc)
  495. return rc;
  496. if (sis_find_family(dev) == 0)
  497. return -ENOTSUPP;
  498. if (chipset_family >= ATA_133)
  499. d.port_ops = &sis_ata133_port_ops;
  500. else
  501. d.port_ops = &sis_port_ops;
  502. d.udma_mask = udma_rates[chipset_family];
  503. return ide_pci_init_one(dev, &d, NULL);
  504. }
  505. static void sis5513_remove(struct pci_dev *dev)
  506. {
  507. ide_pci_remove(dev);
  508. pci_disable_device(dev);
  509. }
  510. static const struct pci_device_id sis5513_pci_tbl[] = {
  511. { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5513), 0 },
  512. { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5518), 0 },
  513. { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_1180), 0 },
  514. { 0, },
  515. };
  516. MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
  517. static struct pci_driver sis5513_pci_driver = {
  518. .name = "SIS_IDE",
  519. .id_table = sis5513_pci_tbl,
  520. .probe = sis5513_init_one,
  521. .remove = sis5513_remove,
  522. .suspend = ide_pci_suspend,
  523. .resume = ide_pci_resume,
  524. };
  525. static int __init sis5513_ide_init(void)
  526. {
  527. return ide_pci_register_driver(&sis5513_pci_driver);
  528. }
  529. static void __exit sis5513_ide_exit(void)
  530. {
  531. pci_unregister_driver(&sis5513_pci_driver);
  532. }
  533. module_init(sis5513_ide_init);
  534. module_exit(sis5513_ide_exit);
  535. MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
  536. MODULE_DESCRIPTION("PCI driver module for SIS IDE");
  537. MODULE_LICENSE("GPL");