siimage.c 21 KB

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  1. /*
  2. * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
  3. * Copyright (C) 2003 Red Hat
  4. * Copyright (C) 2007-2008 MontaVista Software, Inc.
  5. * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
  6. *
  7. * May be copied or modified under the terms of the GNU General Public License
  8. *
  9. * Documentation for CMD680:
  10. * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
  11. *
  12. * Documentation for SiI 3112:
  13. * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
  14. *
  15. * Errata and other documentation only available under NDA.
  16. *
  17. *
  18. * FAQ Items:
  19. * If you are using Marvell SATA-IDE adapters with Maxtor drives
  20. * ensure the system is set up for ATA100/UDMA5, not UDMA6.
  21. *
  22. * If you are using WD drives with SATA bridges you must set the
  23. * drive to "Single". "Master" will hang.
  24. *
  25. * If you have strange problems with nVidia chipset systems please
  26. * see the SI support documentation and update your system BIOS
  27. * if necessary
  28. *
  29. * The Dell DRAC4 has some interesting features including effectively hot
  30. * unplugging/replugging the virtual CD interface when the DRAC is reset.
  31. * This often causes drivers/ide/siimage to panic but is ok with the rather
  32. * smarter code in libata.
  33. *
  34. * TODO:
  35. * - VDMA support
  36. */
  37. #include <linux/types.h>
  38. #include <linux/module.h>
  39. #include <linux/pci.h>
  40. #include <linux/ide.h>
  41. #include <linux/init.h>
  42. #include <linux/io.h>
  43. #define DRV_NAME "siimage"
  44. /**
  45. * pdev_is_sata - check if device is SATA
  46. * @pdev: PCI device to check
  47. *
  48. * Returns true if this is a SATA controller
  49. */
  50. static int pdev_is_sata(struct pci_dev *pdev)
  51. {
  52. #ifdef CONFIG_BLK_DEV_IDE_SATA
  53. switch (pdev->device) {
  54. case PCI_DEVICE_ID_SII_3112:
  55. case PCI_DEVICE_ID_SII_1210SA:
  56. return 1;
  57. case PCI_DEVICE_ID_SII_680:
  58. return 0;
  59. }
  60. BUG();
  61. #endif
  62. return 0;
  63. }
  64. /**
  65. * is_sata - check if hwif is SATA
  66. * @hwif: interface to check
  67. *
  68. * Returns true if this is a SATA controller
  69. */
  70. static inline int is_sata(ide_hwif_t *hwif)
  71. {
  72. return pdev_is_sata(to_pci_dev(hwif->dev));
  73. }
  74. /**
  75. * siimage_selreg - return register base
  76. * @hwif: interface
  77. * @r: config offset
  78. *
  79. * Turn a config register offset into the right address in either
  80. * PCI space or MMIO space to access the control register in question
  81. * Thankfully this is a configuration operation, so isn't performance
  82. * critical.
  83. */
  84. static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
  85. {
  86. unsigned long base = (unsigned long)hwif->hwif_data;
  87. base += 0xA0 + r;
  88. if (hwif->host_flags & IDE_HFLAG_MMIO)
  89. base += hwif->channel << 6;
  90. else
  91. base += hwif->channel << 4;
  92. return base;
  93. }
  94. /**
  95. * siimage_seldev - return register base
  96. * @hwif: interface
  97. * @r: config offset
  98. *
  99. * Turn a config register offset into the right address in either
  100. * PCI space or MMIO space to access the control register in question
  101. * including accounting for the unit shift.
  102. */
  103. static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
  104. {
  105. ide_hwif_t *hwif = drive->hwif;
  106. unsigned long base = (unsigned long)hwif->hwif_data;
  107. u8 unit = drive->dn & 1;
  108. base += 0xA0 + r;
  109. if (hwif->host_flags & IDE_HFLAG_MMIO)
  110. base += hwif->channel << 6;
  111. else
  112. base += hwif->channel << 4;
  113. base |= unit << unit;
  114. return base;
  115. }
  116. static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr)
  117. {
  118. struct ide_host *host = pci_get_drvdata(dev);
  119. u8 tmp = 0;
  120. if (host->host_priv)
  121. tmp = readb((void __iomem *)addr);
  122. else
  123. pci_read_config_byte(dev, addr, &tmp);
  124. return tmp;
  125. }
  126. static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr)
  127. {
  128. struct ide_host *host = pci_get_drvdata(dev);
  129. u16 tmp = 0;
  130. if (host->host_priv)
  131. tmp = readw((void __iomem *)addr);
  132. else
  133. pci_read_config_word(dev, addr, &tmp);
  134. return tmp;
  135. }
  136. static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr)
  137. {
  138. struct ide_host *host = pci_get_drvdata(dev);
  139. if (host->host_priv)
  140. writeb(val, (void __iomem *)addr);
  141. else
  142. pci_write_config_byte(dev, addr, val);
  143. }
  144. static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr)
  145. {
  146. struct ide_host *host = pci_get_drvdata(dev);
  147. if (host->host_priv)
  148. writew(val, (void __iomem *)addr);
  149. else
  150. pci_write_config_word(dev, addr, val);
  151. }
  152. static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr)
  153. {
  154. struct ide_host *host = pci_get_drvdata(dev);
  155. if (host->host_priv)
  156. writel(val, (void __iomem *)addr);
  157. else
  158. pci_write_config_dword(dev, addr, val);
  159. }
  160. /**
  161. * sil_udma_filter - compute UDMA mask
  162. * @drive: IDE device
  163. *
  164. * Compute the available UDMA speeds for the device on the interface.
  165. *
  166. * For the CMD680 this depends on the clocking mode (scsc), for the
  167. * SI3112 SATA controller life is a bit simpler.
  168. */
  169. static u8 sil_pata_udma_filter(ide_drive_t *drive)
  170. {
  171. ide_hwif_t *hwif = drive->hwif;
  172. struct pci_dev *dev = to_pci_dev(hwif->dev);
  173. unsigned long base = (unsigned long)hwif->hwif_data;
  174. u8 scsc, mask = 0;
  175. base += (hwif->host_flags & IDE_HFLAG_MMIO) ? 0x4A : 0x8A;
  176. scsc = sil_ioread8(dev, base);
  177. switch (scsc & 0x30) {
  178. case 0x10: /* 133 */
  179. mask = ATA_UDMA6;
  180. break;
  181. case 0x20: /* 2xPCI */
  182. mask = ATA_UDMA6;
  183. break;
  184. case 0x00: /* 100 */
  185. mask = ATA_UDMA5;
  186. break;
  187. default: /* Disabled ? */
  188. BUG();
  189. }
  190. return mask;
  191. }
  192. static u8 sil_sata_udma_filter(ide_drive_t *drive)
  193. {
  194. char *m = (char *)&drive->id[ATA_ID_PROD];
  195. return strstr(m, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6;
  196. }
  197. /**
  198. * sil_set_pio_mode - set host controller for PIO mode
  199. * @hwif: port
  200. * @drive: drive
  201. *
  202. * Load the timing settings for this device mode into the
  203. * controller.
  204. */
  205. static void sil_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  206. {
  207. static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
  208. static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
  209. struct pci_dev *dev = to_pci_dev(hwif->dev);
  210. ide_drive_t *pair = ide_get_pair_dev(drive);
  211. u32 speedt = 0;
  212. u16 speedp = 0;
  213. unsigned long addr = siimage_seldev(drive, 0x04);
  214. unsigned long tfaddr = siimage_selreg(hwif, 0x02);
  215. unsigned long base = (unsigned long)hwif->hwif_data;
  216. const u8 pio = drive->pio_mode - XFER_PIO_0;
  217. u8 tf_pio = pio;
  218. u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
  219. u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
  220. : (mmio ? 0xB4 : 0x80);
  221. u8 mode = 0;
  222. u8 unit = drive->dn & 1;
  223. /* trim *taskfile* PIO to the slowest of the master/slave */
  224. if (pair) {
  225. u8 pair_pio = pair->pio_mode - XFER_PIO_0;
  226. if (pair_pio < tf_pio)
  227. tf_pio = pair_pio;
  228. }
  229. /* cheat for now and use the docs */
  230. speedp = data_speed[pio];
  231. speedt = tf_speed[tf_pio];
  232. sil_iowrite16(dev, speedp, addr);
  233. sil_iowrite16(dev, speedt, tfaddr);
  234. /* now set up IORDY */
  235. speedp = sil_ioread16(dev, tfaddr - 2);
  236. speedp &= ~0x200;
  237. mode = sil_ioread8(dev, base + addr_mask);
  238. mode &= ~(unit ? 0x30 : 0x03);
  239. if (ide_pio_need_iordy(drive, pio)) {
  240. speedp |= 0x200;
  241. mode |= unit ? 0x10 : 0x01;
  242. }
  243. sil_iowrite16(dev, speedp, tfaddr - 2);
  244. sil_iowrite8(dev, mode, base + addr_mask);
  245. }
  246. /**
  247. * sil_set_dma_mode - set host controller for DMA mode
  248. * @hwif: port
  249. * @drive: drive
  250. *
  251. * Tune the SiI chipset for the desired DMA mode.
  252. */
  253. static void sil_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  254. {
  255. static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
  256. static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
  257. static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
  258. struct pci_dev *dev = to_pci_dev(hwif->dev);
  259. unsigned long base = (unsigned long)hwif->hwif_data;
  260. u16 ultra = 0, multi = 0;
  261. u8 mode = 0, unit = drive->dn & 1;
  262. u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
  263. u8 scsc = 0, addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
  264. : (mmio ? 0xB4 : 0x80);
  265. unsigned long ma = siimage_seldev(drive, 0x08);
  266. unsigned long ua = siimage_seldev(drive, 0x0C);
  267. const u8 speed = drive->dma_mode;
  268. scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A));
  269. mode = sil_ioread8 (dev, base + addr_mask);
  270. multi = sil_ioread16(dev, ma);
  271. ultra = sil_ioread16(dev, ua);
  272. mode &= ~(unit ? 0x30 : 0x03);
  273. ultra &= ~0x3F;
  274. scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
  275. scsc = is_sata(hwif) ? 1 : scsc;
  276. if (speed >= XFER_UDMA_0) {
  277. multi = dma[2];
  278. ultra |= scsc ? ultra6[speed - XFER_UDMA_0] :
  279. ultra5[speed - XFER_UDMA_0];
  280. mode |= unit ? 0x30 : 0x03;
  281. } else {
  282. multi = dma[speed - XFER_MW_DMA_0];
  283. mode |= unit ? 0x20 : 0x02;
  284. }
  285. sil_iowrite8 (dev, mode, base + addr_mask);
  286. sil_iowrite16(dev, multi, ma);
  287. sil_iowrite16(dev, ultra, ua);
  288. }
  289. static int sil_test_irq(ide_hwif_t *hwif)
  290. {
  291. struct pci_dev *dev = to_pci_dev(hwif->dev);
  292. unsigned long addr = siimage_selreg(hwif, 1);
  293. u8 val = sil_ioread8(dev, addr);
  294. /* Return 1 if INTRQ asserted */
  295. return (val & 8) ? 1 : 0;
  296. }
  297. /**
  298. * siimage_mmio_dma_test_irq - check we caused an IRQ
  299. * @drive: drive we are testing
  300. *
  301. * Check if we caused an IDE DMA interrupt. We may also have caused
  302. * SATA status interrupts, if so we clean them up and continue.
  303. */
  304. static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
  305. {
  306. ide_hwif_t *hwif = drive->hwif;
  307. void __iomem *sata_error_addr
  308. = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET];
  309. if (sata_error_addr) {
  310. unsigned long base = (unsigned long)hwif->hwif_data;
  311. u32 ext_stat = readl((void __iomem *)(base + 0x10));
  312. u8 watchdog = 0;
  313. if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
  314. u32 sata_error = readl(sata_error_addr);
  315. writel(sata_error, sata_error_addr);
  316. watchdog = (sata_error & 0x00680000) ? 1 : 0;
  317. printk(KERN_WARNING "%s: sata_error = 0x%08x, "
  318. "watchdog = %d, %s\n",
  319. drive->name, sata_error, watchdog, __func__);
  320. } else
  321. watchdog = (ext_stat & 0x8000) ? 1 : 0;
  322. ext_stat >>= 16;
  323. if (!(ext_stat & 0x0404) && !watchdog)
  324. return 0;
  325. }
  326. /* return 1 if INTR asserted */
  327. if (readb((void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)) & 4)
  328. return 1;
  329. return 0;
  330. }
  331. static int siimage_dma_test_irq(ide_drive_t *drive)
  332. {
  333. if (drive->hwif->host_flags & IDE_HFLAG_MMIO)
  334. return siimage_mmio_dma_test_irq(drive);
  335. else
  336. return ide_dma_test_irq(drive);
  337. }
  338. /**
  339. * sil_sata_reset_poll - wait for SATA reset
  340. * @drive: drive we are resetting
  341. *
  342. * Poll the SATA phy and see whether it has come back from the dead
  343. * yet.
  344. */
  345. static blk_status_t sil_sata_reset_poll(ide_drive_t *drive)
  346. {
  347. ide_hwif_t *hwif = drive->hwif;
  348. void __iomem *sata_status_addr
  349. = (void __iomem *)hwif->sata_scr[SATA_STATUS_OFFSET];
  350. if (sata_status_addr) {
  351. /* SATA Status is available only when in MMIO mode */
  352. u32 sata_stat = readl(sata_status_addr);
  353. if ((sata_stat & 0x03) != 0x03) {
  354. printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
  355. hwif->name, sata_stat);
  356. return BLK_STS_IOERR;
  357. }
  358. }
  359. return BLK_STS_OK;
  360. }
  361. /**
  362. * sil_sata_pre_reset - reset hook
  363. * @drive: IDE device being reset
  364. *
  365. * For the SATA devices we need to handle recalibration/geometry
  366. * differently
  367. */
  368. static void sil_sata_pre_reset(ide_drive_t *drive)
  369. {
  370. if (drive->media == ide_disk) {
  371. drive->special_flags &=
  372. ~(IDE_SFLAG_SET_GEOMETRY | IDE_SFLAG_RECALIBRATE);
  373. }
  374. }
  375. /**
  376. * init_chipset_siimage - set up an SI device
  377. * @dev: PCI device
  378. *
  379. * Perform the initial PCI set up for this device. Attempt to switch
  380. * to 133 MHz clocking if the system isn't already set up to do it.
  381. */
  382. static int init_chipset_siimage(struct pci_dev *dev)
  383. {
  384. struct ide_host *host = pci_get_drvdata(dev);
  385. void __iomem *ioaddr = host->host_priv;
  386. unsigned long base, scsc_addr;
  387. u8 rev = dev->revision, tmp;
  388. pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
  389. if (ioaddr)
  390. pci_set_master(dev);
  391. base = (unsigned long)ioaddr;
  392. if (ioaddr && pdev_is_sata(dev)) {
  393. u32 tmp32, irq_mask;
  394. /* make sure IDE0/1 interrupts are not masked */
  395. irq_mask = (1 << 22) | (1 << 23);
  396. tmp32 = readl(ioaddr + 0x48);
  397. if (tmp32 & irq_mask) {
  398. tmp32 &= ~irq_mask;
  399. writel(tmp32, ioaddr + 0x48);
  400. readl(ioaddr + 0x48); /* flush */
  401. }
  402. writel(0, ioaddr + 0x148);
  403. writel(0, ioaddr + 0x1C8);
  404. }
  405. sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);
  406. sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);
  407. scsc_addr = base ? (base + 0x4A) : 0x8A;
  408. tmp = sil_ioread8(dev, scsc_addr);
  409. switch (tmp & 0x30) {
  410. case 0x00:
  411. /* On 100 MHz clocking, try and switch to 133 MHz */
  412. sil_iowrite8(dev, tmp | 0x10, scsc_addr);
  413. break;
  414. case 0x30:
  415. /* Clocking is disabled, attempt to force 133MHz clocking. */
  416. sil_iowrite8(dev, tmp & ~0x20, scsc_addr);
  417. case 0x10:
  418. /* On 133Mhz clocking. */
  419. break;
  420. case 0x20:
  421. /* On PCIx2 clocking. */
  422. break;
  423. }
  424. tmp = sil_ioread8(dev, scsc_addr);
  425. sil_iowrite8 (dev, 0x72, base + 0xA1);
  426. sil_iowrite16(dev, 0x328A, base + 0xA2);
  427. sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
  428. sil_iowrite32(dev, 0x43924392, base + 0xA8);
  429. sil_iowrite32(dev, 0x40094009, base + 0xAC);
  430. sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1);
  431. sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2);
  432. sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
  433. sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
  434. sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);
  435. if (base && pdev_is_sata(dev)) {
  436. writel(0xFFFF0000, ioaddr + 0x108);
  437. writel(0xFFFF0000, ioaddr + 0x188);
  438. writel(0x00680000, ioaddr + 0x148);
  439. writel(0x00680000, ioaddr + 0x1C8);
  440. }
  441. /* report the clocking mode of the controller */
  442. if (!pdev_is_sata(dev)) {
  443. static const char *clk_str[] =
  444. { "== 100", "== 133", "== 2X PCI", "DISABLED!" };
  445. tmp >>= 4;
  446. printk(KERN_INFO DRV_NAME " %s: BASE CLOCK %s\n",
  447. pci_name(dev), clk_str[tmp & 3]);
  448. }
  449. return 0;
  450. }
  451. /**
  452. * init_mmio_iops_siimage - set up the iops for MMIO
  453. * @hwif: interface to set up
  454. *
  455. * The basic setup here is fairly simple, we can use standard MMIO
  456. * operations. However we do have to set the taskfile register offsets
  457. * by hand as there isn't a standard defined layout for them this time.
  458. *
  459. * The hardware supports buffered taskfiles and also some rather nice
  460. * extended PRD tables. For better SI3112 support use the libata driver
  461. */
  462. static void init_mmio_iops_siimage(ide_hwif_t *hwif)
  463. {
  464. struct pci_dev *dev = to_pci_dev(hwif->dev);
  465. struct ide_host *host = pci_get_drvdata(dev);
  466. void *addr = host->host_priv;
  467. u8 ch = hwif->channel;
  468. struct ide_io_ports *io_ports = &hwif->io_ports;
  469. unsigned long base;
  470. /*
  471. * Fill in the basic hwif bits
  472. */
  473. hwif->host_flags |= IDE_HFLAG_MMIO;
  474. hwif->hwif_data = addr;
  475. /*
  476. * Now set up the hw. We have to do this ourselves as the
  477. * MMIO layout isn't the same as the standard port based I/O.
  478. */
  479. memset(io_ports, 0, sizeof(*io_ports));
  480. base = (unsigned long)addr;
  481. if (ch)
  482. base += 0xC0;
  483. else
  484. base += 0x80;
  485. /*
  486. * The buffered task file doesn't have status/control, so we
  487. * can't currently use it sanely since we want to use LBA48 mode.
  488. */
  489. io_ports->data_addr = base;
  490. io_ports->error_addr = base + 1;
  491. io_ports->nsect_addr = base + 2;
  492. io_ports->lbal_addr = base + 3;
  493. io_ports->lbam_addr = base + 4;
  494. io_ports->lbah_addr = base + 5;
  495. io_ports->device_addr = base + 6;
  496. io_ports->status_addr = base + 7;
  497. io_ports->ctl_addr = base + 10;
  498. if (pdev_is_sata(dev)) {
  499. base = (unsigned long)addr;
  500. if (ch)
  501. base += 0x80;
  502. hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
  503. hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
  504. hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
  505. }
  506. hwif->irq = dev->irq;
  507. hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
  508. }
  509. static int is_dev_seagate_sata(ide_drive_t *drive)
  510. {
  511. const char *s = (const char *)&drive->id[ATA_ID_PROD];
  512. unsigned len = strnlen(s, ATA_ID_PROD_LEN);
  513. if ((len > 4) && (!memcmp(s, "ST", 2)))
  514. if ((!memcmp(s + len - 2, "AS", 2)) ||
  515. (!memcmp(s + len - 3, "ASL", 3))) {
  516. printk(KERN_INFO "%s: applying pessimistic Seagate "
  517. "errata fix\n", drive->name);
  518. return 1;
  519. }
  520. return 0;
  521. }
  522. /**
  523. * sil_quirkproc - post probe fixups
  524. * @drive: drive
  525. *
  526. * Called after drive probe we use this to decide whether the
  527. * Seagate fixup must be applied. This used to be in init_iops but
  528. * that can occur before we know what drives are present.
  529. */
  530. static void sil_quirkproc(ide_drive_t *drive)
  531. {
  532. ide_hwif_t *hwif = drive->hwif;
  533. /* Try and rise the rqsize */
  534. if (!is_sata(hwif) || !is_dev_seagate_sata(drive))
  535. hwif->rqsize = 128;
  536. }
  537. /**
  538. * init_iops_siimage - set up iops
  539. * @hwif: interface to set up
  540. *
  541. * Do the basic setup for the SIIMAGE hardware interface
  542. * and then do the MMIO setup if we can. This is the first
  543. * look in we get for setting up the hwif so that we
  544. * can get the iops right before using them.
  545. */
  546. static void init_iops_siimage(ide_hwif_t *hwif)
  547. {
  548. struct ide_host *host = dev_get_drvdata(hwif->dev);
  549. hwif->hwif_data = NULL;
  550. /* Pessimal until we finish probing */
  551. hwif->rqsize = 15;
  552. if (host->host_priv)
  553. init_mmio_iops_siimage(hwif);
  554. }
  555. /**
  556. * sil_cable_detect - cable detection
  557. * @hwif: interface to check
  558. *
  559. * Check for the presence of an ATA66 capable cable on the interface.
  560. */
  561. static u8 sil_cable_detect(ide_hwif_t *hwif)
  562. {
  563. struct pci_dev *dev = to_pci_dev(hwif->dev);
  564. unsigned long addr = siimage_selreg(hwif, 0);
  565. u8 ata66 = sil_ioread8(dev, addr);
  566. return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
  567. }
  568. static const struct ide_port_ops sil_pata_port_ops = {
  569. .set_pio_mode = sil_set_pio_mode,
  570. .set_dma_mode = sil_set_dma_mode,
  571. .quirkproc = sil_quirkproc,
  572. .test_irq = sil_test_irq,
  573. .udma_filter = sil_pata_udma_filter,
  574. .cable_detect = sil_cable_detect,
  575. };
  576. static const struct ide_port_ops sil_sata_port_ops = {
  577. .set_pio_mode = sil_set_pio_mode,
  578. .set_dma_mode = sil_set_dma_mode,
  579. .reset_poll = sil_sata_reset_poll,
  580. .pre_reset = sil_sata_pre_reset,
  581. .quirkproc = sil_quirkproc,
  582. .test_irq = sil_test_irq,
  583. .udma_filter = sil_sata_udma_filter,
  584. .cable_detect = sil_cable_detect,
  585. };
  586. static const struct ide_dma_ops sil_dma_ops = {
  587. .dma_host_set = ide_dma_host_set,
  588. .dma_setup = ide_dma_setup,
  589. .dma_start = ide_dma_start,
  590. .dma_end = ide_dma_end,
  591. .dma_test_irq = siimage_dma_test_irq,
  592. .dma_timer_expiry = ide_dma_sff_timer_expiry,
  593. .dma_lost_irq = ide_dma_lost_irq,
  594. .dma_sff_read_status = ide_dma_sff_read_status,
  595. };
  596. #define DECLARE_SII_DEV(p_ops) \
  597. { \
  598. .name = DRV_NAME, \
  599. .init_chipset = init_chipset_siimage, \
  600. .init_iops = init_iops_siimage, \
  601. .port_ops = p_ops, \
  602. .dma_ops = &sil_dma_ops, \
  603. .pio_mask = ATA_PIO4, \
  604. .mwdma_mask = ATA_MWDMA2, \
  605. .udma_mask = ATA_UDMA6, \
  606. }
  607. static const struct ide_port_info siimage_chipsets[] = {
  608. /* 0: SiI680 */ DECLARE_SII_DEV(&sil_pata_port_ops),
  609. /* 1: SiI3112 */ DECLARE_SII_DEV(&sil_sata_port_ops)
  610. };
  611. /**
  612. * siimage_init_one - PCI layer discovery entry
  613. * @dev: PCI device
  614. * @id: ident table entry
  615. *
  616. * Called by the PCI code when it finds an SiI680 or SiI3112 controller.
  617. * We then use the IDE PCI generic helper to do most of the work.
  618. */
  619. static int siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  620. {
  621. void __iomem *ioaddr = NULL;
  622. resource_size_t bar5 = pci_resource_start(dev, 5);
  623. unsigned long barsize = pci_resource_len(dev, 5);
  624. int rc;
  625. struct ide_port_info d;
  626. u8 idx = id->driver_data;
  627. u8 BA5_EN;
  628. d = siimage_chipsets[idx];
  629. if (idx) {
  630. static int first = 1;
  631. if (first) {
  632. printk(KERN_INFO DRV_NAME ": For full SATA support you "
  633. "should use the libata sata_sil module.\n");
  634. first = 0;
  635. }
  636. d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
  637. }
  638. rc = pci_enable_device(dev);
  639. if (rc)
  640. return rc;
  641. pci_read_config_byte(dev, 0x8A, &BA5_EN);
  642. if ((BA5_EN & 0x01) || bar5) {
  643. /*
  644. * Drop back to PIO if we can't map the MMIO. Some systems
  645. * seem to get terminally confused in the PCI spaces.
  646. */
  647. if (!request_mem_region(bar5, barsize, d.name)) {
  648. printk(KERN_WARNING DRV_NAME " %s: MMIO ports not "
  649. "available\n", pci_name(dev));
  650. } else {
  651. ioaddr = pci_ioremap_bar(dev, 5);
  652. if (ioaddr == NULL)
  653. release_mem_region(bar5, barsize);
  654. }
  655. }
  656. rc = ide_pci_init_one(dev, &d, ioaddr);
  657. if (rc) {
  658. if (ioaddr) {
  659. iounmap(ioaddr);
  660. release_mem_region(bar5, barsize);
  661. }
  662. pci_disable_device(dev);
  663. }
  664. return rc;
  665. }
  666. static void siimage_remove(struct pci_dev *dev)
  667. {
  668. struct ide_host *host = pci_get_drvdata(dev);
  669. void __iomem *ioaddr = host->host_priv;
  670. ide_pci_remove(dev);
  671. if (ioaddr) {
  672. resource_size_t bar5 = pci_resource_start(dev, 5);
  673. unsigned long barsize = pci_resource_len(dev, 5);
  674. iounmap(ioaddr);
  675. release_mem_region(bar5, barsize);
  676. }
  677. pci_disable_device(dev);
  678. }
  679. static const struct pci_device_id siimage_pci_tbl[] = {
  680. { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 },
  681. #ifdef CONFIG_BLK_DEV_IDE_SATA
  682. { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 },
  683. { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 1 },
  684. #endif
  685. { 0, },
  686. };
  687. MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
  688. static struct pci_driver siimage_pci_driver = {
  689. .name = "SiI_IDE",
  690. .id_table = siimage_pci_tbl,
  691. .probe = siimage_init_one,
  692. .remove = siimage_remove,
  693. .suspend = ide_pci_suspend,
  694. .resume = ide_pci_resume,
  695. };
  696. static int __init siimage_ide_init(void)
  697. {
  698. return ide_pci_register_driver(&siimage_pci_driver);
  699. }
  700. static void __exit siimage_ide_exit(void)
  701. {
  702. pci_unregister_driver(&siimage_pci_driver);
  703. }
  704. module_init(siimage_ide_init);
  705. module_exit(siimage_ide_exit);
  706. MODULE_AUTHOR("Andre Hedrick, Alan Cox");
  707. MODULE_DESCRIPTION("PCI driver module for SiI IDE");
  708. MODULE_LICENSE("GPL");