serverworks.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 1998-2000 Michel Aubry
  4. * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
  5. * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
  6. * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
  7. * Portions copyright (c) 2001 Sun Microsystems
  8. *
  9. *
  10. * RCC/ServerWorks IDE driver for Linux
  11. *
  12. * OSB4: `Open South Bridge' IDE Interface (fn 1)
  13. * supports UDMA mode 2 (33 MB/s)
  14. *
  15. * CSB5: `Champion South Bridge' IDE Interface (fn 1)
  16. * all revisions support UDMA mode 4 (66 MB/s)
  17. * revision A2.0 and up support UDMA mode 5 (100 MB/s)
  18. *
  19. * *** The CSB5 does not provide ANY register ***
  20. * *** to detect 80-conductor cable presence. ***
  21. *
  22. * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
  23. *
  24. * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
  25. * controller same as the CSB6. Single channel ATA100 only.
  26. *
  27. * Documentation:
  28. * Available under NDA only. Errata info very hard to get.
  29. *
  30. */
  31. #include <linux/types.h>
  32. #include <linux/module.h>
  33. #include <linux/kernel.h>
  34. #include <linux/pci.h>
  35. #include <linux/ide.h>
  36. #include <linux/init.h>
  37. #include <asm/io.h>
  38. #define DRV_NAME "serverworks"
  39. #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
  40. #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
  41. /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
  42. * can overrun their FIFOs when used with the CSB5 */
  43. static const char *svwks_bad_ata100[] = {
  44. "ST320011A",
  45. "ST340016A",
  46. "ST360021A",
  47. "ST380021A",
  48. NULL
  49. };
  50. static int check_in_drive_lists (ide_drive_t *drive, const char **list)
  51. {
  52. char *m = (char *)&drive->id[ATA_ID_PROD];
  53. while (*list)
  54. if (!strcmp(*list++, m))
  55. return 1;
  56. return 0;
  57. }
  58. static u8 svwks_udma_filter(ide_drive_t *drive)
  59. {
  60. struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  61. if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
  62. return 0x1f;
  63. } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
  64. return 0x07;
  65. } else {
  66. u8 btr = 0, mode, mask;
  67. pci_read_config_byte(dev, 0x5A, &btr);
  68. mode = btr & 0x3;
  69. /* If someone decides to do UDMA133 on CSB5 the same
  70. issue will bite so be inclusive */
  71. if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
  72. mode = 2;
  73. switch(mode) {
  74. case 3: mask = 0x3f; break;
  75. case 2: mask = 0x1f; break;
  76. case 1: mask = 0x07; break;
  77. default: mask = 0x00; break;
  78. }
  79. return mask;
  80. }
  81. }
  82. static u8 svwks_csb_check (struct pci_dev *dev)
  83. {
  84. switch (dev->device) {
  85. case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
  86. case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
  87. case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
  88. case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
  89. return 1;
  90. default:
  91. break;
  92. }
  93. return 0;
  94. }
  95. static void svwks_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  96. {
  97. static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
  98. static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
  99. struct pci_dev *dev = to_pci_dev(hwif->dev);
  100. const u8 pio = drive->pio_mode - XFER_PIO_0;
  101. if (drive->dn >= ARRAY_SIZE(drive_pci))
  102. return;
  103. pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
  104. if (svwks_csb_check(dev)) {
  105. u16 csb_pio = 0;
  106. pci_read_config_word(dev, 0x4a, &csb_pio);
  107. csb_pio &= ~(0x0f << (4 * drive->dn));
  108. csb_pio |= (pio << (4 * drive->dn));
  109. pci_write_config_word(dev, 0x4a, csb_pio);
  110. }
  111. }
  112. static void svwks_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  113. {
  114. static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
  115. static const u8 dma_modes[] = { 0x77, 0x21, 0x20 };
  116. static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
  117. struct pci_dev *dev = to_pci_dev(hwif->dev);
  118. const u8 speed = drive->dma_mode;
  119. u8 unit = drive->dn & 1;
  120. u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0;
  121. if (drive->dn >= ARRAY_SIZE(drive_pci2))
  122. return;
  123. pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
  124. pci_read_config_byte(dev, 0x54, &ultra_enable);
  125. ultra_timing &= ~(0x0F << (4*unit));
  126. ultra_enable &= ~(0x01 << drive->dn);
  127. if (speed >= XFER_UDMA_0) {
  128. dma_timing |= dma_modes[2];
  129. ultra_timing |= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
  130. ultra_enable |= (0x01 << drive->dn);
  131. } else if (speed >= XFER_MW_DMA_0)
  132. dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
  133. pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
  134. pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
  135. pci_write_config_byte(dev, 0x54, ultra_enable);
  136. }
  137. static int init_chipset_svwks(struct pci_dev *dev)
  138. {
  139. unsigned int reg;
  140. u8 btr;
  141. /* force Master Latency Timer value to 64 PCICLKs */
  142. pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
  143. /* OSB4 : South Bridge and IDE */
  144. if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
  145. struct pci_dev *isa_dev =
  146. pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  147. PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
  148. if (isa_dev) {
  149. pci_read_config_dword(isa_dev, 0x64, &reg);
  150. reg &= ~0x00002000; /* disable 600ns interrupt mask */
  151. if(!(reg & 0x00004000))
  152. printk(KERN_DEBUG DRV_NAME " %s: UDMA not BIOS "
  153. "enabled.\n", pci_name(dev));
  154. reg |= 0x00004000; /* enable UDMA/33 support */
  155. pci_write_config_dword(isa_dev, 0x64, reg);
  156. pci_dev_put(isa_dev);
  157. }
  158. }
  159. /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
  160. else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
  161. (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
  162. (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
  163. /* Third Channel Test */
  164. if (!(PCI_FUNC(dev->devfn) & 1)) {
  165. struct pci_dev * findev = NULL;
  166. u32 reg4c = 0;
  167. findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  168. PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
  169. if (findev) {
  170. pci_read_config_dword(findev, 0x4C, &reg4c);
  171. reg4c &= ~0x000007FF;
  172. reg4c |= 0x00000040;
  173. reg4c |= 0x00000020;
  174. pci_write_config_dword(findev, 0x4C, reg4c);
  175. pci_dev_put(findev);
  176. }
  177. outb_p(0x06, 0x0c00);
  178. dev->irq = inb_p(0x0c01);
  179. } else {
  180. struct pci_dev * findev = NULL;
  181. u8 reg41 = 0;
  182. findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  183. PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
  184. if (findev) {
  185. pci_read_config_byte(findev, 0x41, &reg41);
  186. reg41 &= ~0x40;
  187. pci_write_config_byte(findev, 0x41, reg41);
  188. pci_dev_put(findev);
  189. }
  190. /*
  191. * This is a device pin issue on CSB6.
  192. * Since there will be a future raid mode,
  193. * early versions of the chipset require the
  194. * interrupt pin to be set, and it is a compatibility
  195. * mode issue.
  196. */
  197. if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
  198. dev->irq = 0;
  199. }
  200. // pci_read_config_dword(dev, 0x40, &pioreg)
  201. // pci_write_config_dword(dev, 0x40, 0x99999999);
  202. // pci_read_config_dword(dev, 0x44, &dmareg);
  203. // pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
  204. /* setup the UDMA Control register
  205. *
  206. * 1. clear bit 6 to enable DMA
  207. * 2. enable DMA modes with bits 0-1
  208. * 00 : legacy
  209. * 01 : udma2
  210. * 10 : udma2/udma4
  211. * 11 : udma2/udma4/udma5
  212. */
  213. pci_read_config_byte(dev, 0x5A, &btr);
  214. btr &= ~0x40;
  215. if (!(PCI_FUNC(dev->devfn) & 1))
  216. btr |= 0x2;
  217. else
  218. btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
  219. pci_write_config_byte(dev, 0x5A, btr);
  220. }
  221. /* Setup HT1000 SouthBridge Controller - Single Channel Only */
  222. else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
  223. pci_read_config_byte(dev, 0x5A, &btr);
  224. btr &= ~0x40;
  225. btr |= 0x3;
  226. pci_write_config_byte(dev, 0x5A, btr);
  227. }
  228. return 0;
  229. }
  230. static u8 ata66_svwks_svwks(ide_hwif_t *hwif)
  231. {
  232. return ATA_CBL_PATA80;
  233. }
  234. /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
  235. * of the subsystem device ID indicate presence of an 80-pin cable.
  236. * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
  237. * Bit 15 set = secondary IDE channel has 80-pin cable.
  238. * Bit 14 clear = primary IDE channel does not have 80-pin cable.
  239. * Bit 14 set = primary IDE channel has 80-pin cable.
  240. */
  241. static u8 ata66_svwks_dell(ide_hwif_t *hwif)
  242. {
  243. struct pci_dev *dev = to_pci_dev(hwif->dev);
  244. if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
  245. dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
  246. (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
  247. dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
  248. return ((1 << (hwif->channel + 14)) &
  249. dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
  250. return ATA_CBL_PATA40;
  251. }
  252. /* Sun Cobalt Alpine hardware avoids the 80-pin cable
  253. * detect issue by attaching the drives directly to the board.
  254. * This check follows the Dell precedent (how scary is that?!)
  255. *
  256. * WARNING: this only works on Alpine hardware!
  257. */
  258. static u8 ata66_svwks_cobalt(ide_hwif_t *hwif)
  259. {
  260. struct pci_dev *dev = to_pci_dev(hwif->dev);
  261. if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
  262. dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
  263. dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
  264. return ((1 << (hwif->channel + 14)) &
  265. dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
  266. return ATA_CBL_PATA40;
  267. }
  268. static u8 svwks_cable_detect(ide_hwif_t *hwif)
  269. {
  270. struct pci_dev *dev = to_pci_dev(hwif->dev);
  271. /* Server Works */
  272. if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
  273. return ata66_svwks_svwks (hwif);
  274. /* Dell PowerEdge */
  275. if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
  276. return ata66_svwks_dell (hwif);
  277. /* Cobalt Alpine */
  278. if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
  279. return ata66_svwks_cobalt (hwif);
  280. /* Per Specified Design by OEM, and ASIC Architect */
  281. if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
  282. (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
  283. return ATA_CBL_PATA80;
  284. return ATA_CBL_PATA40;
  285. }
  286. static const struct ide_port_ops osb4_port_ops = {
  287. .set_pio_mode = svwks_set_pio_mode,
  288. .set_dma_mode = svwks_set_dma_mode,
  289. };
  290. static const struct ide_port_ops svwks_port_ops = {
  291. .set_pio_mode = svwks_set_pio_mode,
  292. .set_dma_mode = svwks_set_dma_mode,
  293. .udma_filter = svwks_udma_filter,
  294. .cable_detect = svwks_cable_detect,
  295. };
  296. static const struct ide_port_info serverworks_chipsets[] = {
  297. { /* 0: OSB4 */
  298. .name = DRV_NAME,
  299. .init_chipset = init_chipset_svwks,
  300. .port_ops = &osb4_port_ops,
  301. .pio_mask = ATA_PIO4,
  302. .mwdma_mask = ATA_MWDMA2,
  303. .udma_mask = 0x00, /* UDMA is problematic on OSB4 */
  304. },
  305. { /* 1: CSB5 */
  306. .name = DRV_NAME,
  307. .init_chipset = init_chipset_svwks,
  308. .port_ops = &svwks_port_ops,
  309. .pio_mask = ATA_PIO4,
  310. .mwdma_mask = ATA_MWDMA2,
  311. .udma_mask = ATA_UDMA5,
  312. },
  313. { /* 2: CSB6 */
  314. .name = DRV_NAME,
  315. .init_chipset = init_chipset_svwks,
  316. .port_ops = &svwks_port_ops,
  317. .pio_mask = ATA_PIO4,
  318. .mwdma_mask = ATA_MWDMA2,
  319. .udma_mask = ATA_UDMA5,
  320. },
  321. { /* 3: CSB6-2 */
  322. .name = DRV_NAME,
  323. .init_chipset = init_chipset_svwks,
  324. .port_ops = &svwks_port_ops,
  325. .host_flags = IDE_HFLAG_SINGLE,
  326. .pio_mask = ATA_PIO4,
  327. .mwdma_mask = ATA_MWDMA2,
  328. .udma_mask = ATA_UDMA5,
  329. },
  330. { /* 4: HT1000 */
  331. .name = DRV_NAME,
  332. .init_chipset = init_chipset_svwks,
  333. .port_ops = &svwks_port_ops,
  334. .host_flags = IDE_HFLAG_SINGLE,
  335. .pio_mask = ATA_PIO4,
  336. .mwdma_mask = ATA_MWDMA2,
  337. .udma_mask = ATA_UDMA5,
  338. }
  339. };
  340. /**
  341. * svwks_init_one - called when a OSB/CSB is found
  342. * @dev: the svwks device
  343. * @id: the matching pci id
  344. *
  345. * Called when the PCI registration layer (or the IDE initialization)
  346. * finds a device matching our IDE device tables.
  347. */
  348. static int svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  349. {
  350. struct ide_port_info d;
  351. u8 idx = id->driver_data;
  352. d = serverworks_chipsets[idx];
  353. if (idx == 1)
  354. d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
  355. else if (idx == 2 || idx == 3) {
  356. if ((PCI_FUNC(dev->devfn) & 1) == 0) {
  357. if (pci_resource_start(dev, 0) != 0x01f1)
  358. d.host_flags |= IDE_HFLAG_NON_BOOTABLE;
  359. d.host_flags |= IDE_HFLAG_SINGLE;
  360. } else
  361. d.host_flags &= ~IDE_HFLAG_SINGLE;
  362. }
  363. return ide_pci_init_one(dev, &d, NULL);
  364. }
  365. static const struct pci_device_id svwks_pci_tbl[] = {
  366. { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0 },
  367. { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 1 },
  368. { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2 },
  369. { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 3 },
  370. { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
  371. { 0, },
  372. };
  373. MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
  374. static struct pci_driver svwks_pci_driver = {
  375. .name = "Serverworks_IDE",
  376. .id_table = svwks_pci_tbl,
  377. .probe = svwks_init_one,
  378. .remove = ide_pci_remove,
  379. .suspend = ide_pci_suspend,
  380. .resume = ide_pci_resume,
  381. };
  382. static int __init svwks_ide_init(void)
  383. {
  384. return ide_pci_register_driver(&svwks_pci_driver);
  385. }
  386. static void __exit svwks_ide_exit(void)
  387. {
  388. pci_unregister_driver(&svwks_pci_driver);
  389. }
  390. module_init(svwks_ide_init);
  391. module_exit(svwks_ide_exit);
  392. MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick, Bartlomiej Zolnierkiewicz");
  393. MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
  394. MODULE_LICENSE("GPL");