sc1200.c 9.2 KB

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  1. /*
  2. * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
  3. * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
  4. *
  5. * May be copied or modified under the terms of the GNU General Public License
  6. *
  7. * Development of this chipset driver was funded
  8. * by the nice folks at National Semiconductor.
  9. *
  10. * Documentation:
  11. * Available from National Semiconductor
  12. */
  13. #include <linux/module.h>
  14. #include <linux/types.h>
  15. #include <linux/kernel.h>
  16. #include <linux/slab.h>
  17. #include <linux/pci.h>
  18. #include <linux/init.h>
  19. #include <linux/ide.h>
  20. #include <linux/pm.h>
  21. #include <asm/io.h>
  22. #define DRV_NAME "sc1200"
  23. #define SC1200_REV_A 0x00
  24. #define SC1200_REV_B1 0x01
  25. #define SC1200_REV_B3 0x02
  26. #define SC1200_REV_C1 0x03
  27. #define SC1200_REV_D1 0x04
  28. #define PCI_CLK_33 0x00
  29. #define PCI_CLK_48 0x01
  30. #define PCI_CLK_66 0x02
  31. #define PCI_CLK_33A 0x03
  32. static unsigned short sc1200_get_pci_clock (void)
  33. {
  34. unsigned char chip_id, silicon_revision;
  35. unsigned int pci_clock;
  36. /*
  37. * Check the silicon revision, as not all versions of the chip
  38. * have the register with the fast PCI bus timings.
  39. */
  40. chip_id = inb (0x903c);
  41. silicon_revision = inb (0x903d);
  42. // Read the fast pci clock frequency
  43. if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
  44. pci_clock = PCI_CLK_33;
  45. } else {
  46. // check clock generator configuration (cfcc)
  47. // the clock is in bits 8 and 9 of this word
  48. pci_clock = inw (0x901e);
  49. pci_clock >>= 8;
  50. pci_clock &= 0x03;
  51. if (pci_clock == PCI_CLK_33A)
  52. pci_clock = PCI_CLK_33;
  53. }
  54. return pci_clock;
  55. }
  56. /*
  57. * Here are the standard PIO mode 0-4 timings for each "format".
  58. * Format-0 uses fast data reg timings, with slower command reg timings.
  59. * Format-1 uses fast timings for all registers, but won't work with all drives.
  60. */
  61. static const unsigned int sc1200_pio_timings[4][5] =
  62. {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz
  63. {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz
  64. {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz
  65. {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz
  66. /*
  67. * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
  68. */
  69. //#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
  70. static void sc1200_tunepio(ide_drive_t *drive, u8 pio)
  71. {
  72. ide_hwif_t *hwif = drive->hwif;
  73. struct pci_dev *pdev = to_pci_dev(hwif->dev);
  74. unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0;
  75. pci_read_config_dword(pdev, basereg + 4, &format);
  76. format = (format >> 31) & 1;
  77. if (format)
  78. format += sc1200_get_pci_clock();
  79. pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
  80. sc1200_pio_timings[format][pio]);
  81. }
  82. /*
  83. * The SC1200 specifies that two drives sharing a cable cannot mix
  84. * UDMA/MDMA. It has to be one or the other, for the pair, though
  85. * different timings can still be chosen for each drive. We could
  86. * set the appropriate timing bits on the fly, but that might be
  87. * a bit confusing. So, for now we statically handle this requirement
  88. * by looking at our mate drive to see what it is capable of, before
  89. * choosing a mode for our own drive.
  90. */
  91. static u8 sc1200_udma_filter(ide_drive_t *drive)
  92. {
  93. ide_hwif_t *hwif = drive->hwif;
  94. ide_drive_t *mate = ide_get_pair_dev(drive);
  95. u16 *mateid;
  96. u8 mask = hwif->ultra_mask;
  97. if (mate == NULL)
  98. goto out;
  99. mateid = mate->id;
  100. if (ata_id_has_dma(mateid) && __ide_dma_bad_drive(mate) == 0) {
  101. if ((mateid[ATA_ID_FIELD_VALID] & 4) &&
  102. (mateid[ATA_ID_UDMA_MODES] & 7))
  103. goto out;
  104. if (mateid[ATA_ID_MWDMA_MODES] & 7)
  105. mask = 0;
  106. }
  107. out:
  108. return mask;
  109. }
  110. static void sc1200_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  111. {
  112. struct pci_dev *dev = to_pci_dev(hwif->dev);
  113. unsigned int reg, timings;
  114. unsigned short pci_clock;
  115. unsigned int basereg = hwif->channel ? 0x50 : 0x40;
  116. const u8 mode = drive->dma_mode;
  117. static const u32 udma_timing[3][3] = {
  118. { 0x00921250, 0x00911140, 0x00911030 },
  119. { 0x00932470, 0x00922260, 0x00922140 },
  120. { 0x009436a1, 0x00933481, 0x00923261 },
  121. };
  122. static const u32 mwdma_timing[3][3] = {
  123. { 0x00077771, 0x00012121, 0x00002020 },
  124. { 0x000bbbb2, 0x00024241, 0x00013131 },
  125. { 0x000ffff3, 0x00035352, 0x00015151 },
  126. };
  127. pci_clock = sc1200_get_pci_clock();
  128. /*
  129. * Note that each DMA mode has several timings associated with it.
  130. * The correct timing depends on the fast PCI clock freq.
  131. */
  132. if (mode >= XFER_UDMA_0)
  133. timings = udma_timing[pci_clock][mode - XFER_UDMA_0];
  134. else
  135. timings = mwdma_timing[pci_clock][mode - XFER_MW_DMA_0];
  136. if ((drive->dn & 1) == 0) {
  137. pci_read_config_dword(dev, basereg + 4, &reg);
  138. timings |= reg & 0x80000000; /* preserve PIO format bit */
  139. pci_write_config_dword(dev, basereg + 4, timings);
  140. } else
  141. pci_write_config_dword(dev, basereg + 12, timings);
  142. }
  143. /* Replacement for the standard ide_dma_end action in
  144. * dma_proc.
  145. *
  146. * returns 1 on error, 0 otherwise
  147. */
  148. static int sc1200_dma_end(ide_drive_t *drive)
  149. {
  150. ide_hwif_t *hwif = drive->hwif;
  151. unsigned long dma_base = hwif->dma_base;
  152. u8 dma_stat;
  153. dma_stat = inb(dma_base+2); /* get DMA status */
  154. if (!(dma_stat & 4))
  155. printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
  156. dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));
  157. outb(dma_stat|0x1b, dma_base+2); /* clear the INTR & ERROR bits */
  158. outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */
  159. return (dma_stat & 7) != 4; /* verify good DMA status */
  160. }
  161. /*
  162. * sc1200_set_pio_mode() handles setting of PIO modes
  163. * for both the chipset and drive.
  164. *
  165. * All existing BIOSs for this chipset guarantee that all drives
  166. * will have valid default PIO timings set up before we get here.
  167. */
  168. static void sc1200_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  169. {
  170. int mode = -1;
  171. const u8 pio = drive->pio_mode - XFER_PIO_0;
  172. /*
  173. * bad abuse of ->set_pio_mode interface
  174. */
  175. switch (pio) {
  176. case 200: mode = XFER_UDMA_0; break;
  177. case 201: mode = XFER_UDMA_1; break;
  178. case 202: mode = XFER_UDMA_2; break;
  179. case 100: mode = XFER_MW_DMA_0; break;
  180. case 101: mode = XFER_MW_DMA_1; break;
  181. case 102: mode = XFER_MW_DMA_2; break;
  182. }
  183. if (mode != -1) {
  184. printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
  185. ide_dma_off_quietly(drive);
  186. if (ide_set_dma_mode(drive, mode) == 0 &&
  187. (drive->dev_flags & IDE_DFLAG_USING_DMA))
  188. hwif->dma_ops->dma_host_set(drive, 1);
  189. return;
  190. }
  191. sc1200_tunepio(drive, pio);
  192. }
  193. #ifdef CONFIG_PM
  194. struct sc1200_saved_state {
  195. u32 regs[8];
  196. };
  197. static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
  198. {
  199. printk("SC1200: suspend(%u)\n", state.event);
  200. /*
  201. * we only save state when going from full power to less
  202. */
  203. if (state.event == PM_EVENT_ON) {
  204. struct ide_host *host = pci_get_drvdata(dev);
  205. struct sc1200_saved_state *ss = host->host_priv;
  206. unsigned int r;
  207. /*
  208. * save timing registers
  209. * (this may be unnecessary if BIOS also does it)
  210. */
  211. for (r = 0; r < 8; r++)
  212. pci_read_config_dword(dev, 0x40 + r * 4, &ss->regs[r]);
  213. }
  214. pci_disable_device(dev);
  215. pci_set_power_state(dev, pci_choose_state(dev, state));
  216. return 0;
  217. }
  218. static int sc1200_resume (struct pci_dev *dev)
  219. {
  220. struct ide_host *host = pci_get_drvdata(dev);
  221. struct sc1200_saved_state *ss = host->host_priv;
  222. unsigned int r;
  223. int i;
  224. i = pci_enable_device(dev);
  225. if (i)
  226. return i;
  227. /*
  228. * restore timing registers
  229. * (this may be unnecessary if BIOS also does it)
  230. */
  231. for (r = 0; r < 8; r++)
  232. pci_write_config_dword(dev, 0x40 + r * 4, ss->regs[r]);
  233. return 0;
  234. }
  235. #endif
  236. static const struct ide_port_ops sc1200_port_ops = {
  237. .set_pio_mode = sc1200_set_pio_mode,
  238. .set_dma_mode = sc1200_set_dma_mode,
  239. .udma_filter = sc1200_udma_filter,
  240. };
  241. static const struct ide_dma_ops sc1200_dma_ops = {
  242. .dma_host_set = ide_dma_host_set,
  243. .dma_setup = ide_dma_setup,
  244. .dma_start = ide_dma_start,
  245. .dma_end = sc1200_dma_end,
  246. .dma_test_irq = ide_dma_test_irq,
  247. .dma_lost_irq = ide_dma_lost_irq,
  248. .dma_timer_expiry = ide_dma_sff_timer_expiry,
  249. .dma_sff_read_status = ide_dma_sff_read_status,
  250. };
  251. static const struct ide_port_info sc1200_chipset = {
  252. .name = DRV_NAME,
  253. .port_ops = &sc1200_port_ops,
  254. .dma_ops = &sc1200_dma_ops,
  255. .host_flags = IDE_HFLAG_SERIALIZE |
  256. IDE_HFLAG_POST_SET_MODE |
  257. IDE_HFLAG_ABUSE_DMA_MODES,
  258. .pio_mask = ATA_PIO4,
  259. .mwdma_mask = ATA_MWDMA2,
  260. .udma_mask = ATA_UDMA2,
  261. };
  262. static int sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  263. {
  264. struct sc1200_saved_state *ss = NULL;
  265. int rc;
  266. #ifdef CONFIG_PM
  267. ss = kmalloc(sizeof(*ss), GFP_KERNEL);
  268. if (ss == NULL)
  269. return -ENOMEM;
  270. #endif
  271. rc = ide_pci_init_one(dev, &sc1200_chipset, ss);
  272. if (rc)
  273. kfree(ss);
  274. return rc;
  275. }
  276. static const struct pci_device_id sc1200_pci_tbl[] = {
  277. { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
  278. { 0, },
  279. };
  280. MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);
  281. static struct pci_driver sc1200_pci_driver = {
  282. .name = "SC1200_IDE",
  283. .id_table = sc1200_pci_tbl,
  284. .probe = sc1200_init_one,
  285. .remove = ide_pci_remove,
  286. #ifdef CONFIG_PM
  287. .suspend = sc1200_suspend,
  288. .resume = sc1200_resume,
  289. #endif
  290. };
  291. static int __init sc1200_ide_init(void)
  292. {
  293. return ide_pci_register_driver(&sc1200_pci_driver);
  294. }
  295. static void __exit sc1200_ide_exit(void)
  296. {
  297. pci_unregister_driver(&sc1200_pci_driver);
  298. }
  299. module_init(sc1200_ide_init);
  300. module_exit(sc1200_ide_exit);
  301. MODULE_AUTHOR("Mark Lord");
  302. MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
  303. MODULE_LICENSE("GPL");