piix.c 14 KB

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  1. /*
  2. * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
  3. * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
  4. * Copyright (C) 2003 Red Hat
  5. * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
  6. *
  7. * May be copied or modified under the terms of the GNU General Public License
  8. *
  9. * Documentation:
  10. *
  11. * Publicly available from Intel web site. Errata documentation
  12. * is also publicly available. As an aide to anyone hacking on this
  13. * driver the list of errata that are relevant is below.going back to
  14. * PIIX4. Older device documentation is now a bit tricky to find.
  15. *
  16. * Errata of note:
  17. *
  18. * Unfixable
  19. * PIIX4 errata #9 - Only on ultra obscure hw
  20. * ICH3 errata #13 - Not observed to affect real hw
  21. * by Intel
  22. *
  23. * Things we must deal with
  24. * PIIX4 errata #10 - BM IDE hang with non UDMA
  25. * (must stop/start dma to recover)
  26. * 440MX errata #15 - As PIIX4 errata #10
  27. * PIIX4 errata #15 - Must not read control registers
  28. * during a PIO transfer
  29. * 440MX errata #13 - As PIIX4 errata #15
  30. * ICH2 errata #21 - DMA mode 0 doesn't work right
  31. * ICH0/1 errata #55 - As ICH2 errata #21
  32. * ICH2 spec c #9 - Extra operations needed to handle
  33. * drive hotswap [NOT YET SUPPORTED]
  34. * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
  35. * and must be dword aligned
  36. * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
  37. *
  38. * Should have been BIOS fixed:
  39. * 450NX: errata #19 - DMA hangs on old 450NX
  40. * 450NX: errata #20 - DMA hangs on old 450NX
  41. * 450NX: errata #25 - Corruption with DMA on old 450NX
  42. * ICH3 errata #15 - IDE deadlock under high load
  43. * (BIOS must set dev 31 fn 0 bit 23)
  44. * ICH3 errata #18 - Don't use native mode
  45. */
  46. #include <linux/types.h>
  47. #include <linux/module.h>
  48. #include <linux/kernel.h>
  49. #include <linux/pci.h>
  50. #include <linux/ide.h>
  51. #include <linux/init.h>
  52. #include <asm/io.h>
  53. #define DRV_NAME "piix"
  54. static int no_piix_dma;
  55. /**
  56. * piix_set_pio_mode - set host controller for PIO mode
  57. * @port: port
  58. * @drive: drive
  59. *
  60. * Set the interface PIO mode based upon the settings done by AMI BIOS.
  61. */
  62. static void piix_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  63. {
  64. struct pci_dev *dev = to_pci_dev(hwif->dev);
  65. int is_slave = drive->dn & 1;
  66. int master_port = hwif->channel ? 0x42 : 0x40;
  67. int slave_port = 0x44;
  68. unsigned long flags;
  69. u16 master_data;
  70. u8 slave_data;
  71. static DEFINE_SPINLOCK(tune_lock);
  72. int control = 0;
  73. const u8 pio = drive->pio_mode - XFER_PIO_0;
  74. /* ISP RTC */
  75. static const u8 timings[][2]= {
  76. { 0, 0 },
  77. { 0, 0 },
  78. { 1, 0 },
  79. { 2, 1 },
  80. { 2, 3 }, };
  81. /*
  82. * Master vs slave is synchronized above us but the slave register is
  83. * shared by the two hwifs so the corner case of two slave timeouts in
  84. * parallel must be locked.
  85. */
  86. spin_lock_irqsave(&tune_lock, flags);
  87. pci_read_config_word(dev, master_port, &master_data);
  88. if (pio > 1)
  89. control |= 1; /* Programmable timing on */
  90. if (drive->media == ide_disk)
  91. control |= 4; /* Prefetch, post write */
  92. if (ide_pio_need_iordy(drive, pio))
  93. control |= 2; /* IORDY */
  94. if (is_slave) {
  95. master_data |= 0x4000;
  96. master_data &= ~0x0070;
  97. if (pio > 1) {
  98. /* Set PPE, IE and TIME */
  99. master_data |= control << 4;
  100. }
  101. pci_read_config_byte(dev, slave_port, &slave_data);
  102. slave_data &= hwif->channel ? 0x0f : 0xf0;
  103. slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
  104. (hwif->channel ? 4 : 0);
  105. } else {
  106. master_data &= ~0x3307;
  107. if (pio > 1) {
  108. /* enable PPE, IE and TIME */
  109. master_data |= control;
  110. }
  111. master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
  112. }
  113. pci_write_config_word(dev, master_port, master_data);
  114. if (is_slave)
  115. pci_write_config_byte(dev, slave_port, slave_data);
  116. spin_unlock_irqrestore(&tune_lock, flags);
  117. }
  118. /**
  119. * piix_set_dma_mode - set host controller for DMA mode
  120. * @hwif: port
  121. * @drive: drive
  122. *
  123. * Set a PIIX host controller to the desired DMA mode. This involves
  124. * programming the right timing data into the PCI configuration space.
  125. */
  126. static void piix_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  127. {
  128. struct pci_dev *dev = to_pci_dev(hwif->dev);
  129. u8 maslave = hwif->channel ? 0x42 : 0x40;
  130. int a_speed = 3 << (drive->dn * 4);
  131. int u_flag = 1 << drive->dn;
  132. int v_flag = 0x01 << drive->dn;
  133. int w_flag = 0x10 << drive->dn;
  134. int u_speed = 0;
  135. int sitre;
  136. u16 reg4042, reg4a;
  137. u8 reg48, reg54, reg55;
  138. const u8 speed = drive->dma_mode;
  139. pci_read_config_word(dev, maslave, &reg4042);
  140. sitre = (reg4042 & 0x4000) ? 1 : 0;
  141. pci_read_config_byte(dev, 0x48, &reg48);
  142. pci_read_config_word(dev, 0x4a, &reg4a);
  143. pci_read_config_byte(dev, 0x54, &reg54);
  144. pci_read_config_byte(dev, 0x55, &reg55);
  145. if (speed >= XFER_UDMA_0) {
  146. u8 udma = speed - XFER_UDMA_0;
  147. u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
  148. if (!(reg48 & u_flag))
  149. pci_write_config_byte(dev, 0x48, reg48 | u_flag);
  150. if (speed == XFER_UDMA_5) {
  151. pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
  152. } else {
  153. pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
  154. }
  155. if ((reg4a & a_speed) != u_speed)
  156. pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
  157. if (speed > XFER_UDMA_2) {
  158. if (!(reg54 & v_flag))
  159. pci_write_config_byte(dev, 0x54, reg54 | v_flag);
  160. } else
  161. pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
  162. } else {
  163. const u8 mwdma_to_pio[] = { 0, 3, 4 };
  164. if (reg48 & u_flag)
  165. pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
  166. if (reg4a & a_speed)
  167. pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
  168. if (reg54 & v_flag)
  169. pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
  170. if (reg55 & w_flag)
  171. pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
  172. if (speed >= XFER_MW_DMA_0)
  173. drive->pio_mode =
  174. mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
  175. else
  176. drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */
  177. piix_set_pio_mode(hwif, drive);
  178. }
  179. }
  180. /**
  181. * init_chipset_ich - set up the ICH chipset
  182. * @dev: PCI device to set up
  183. *
  184. * Initialize the PCI device as required. For the ICH this turns
  185. * out to be nice and simple.
  186. */
  187. static int init_chipset_ich(struct pci_dev *dev)
  188. {
  189. u32 extra = 0;
  190. pci_read_config_dword(dev, 0x54, &extra);
  191. pci_write_config_dword(dev, 0x54, extra | 0x400);
  192. return 0;
  193. }
  194. /**
  195. * ich_clear_irq - clear BMDMA status
  196. * @drive: IDE drive
  197. *
  198. * ICHx contollers set DMA INTR no matter DMA or PIO.
  199. * BMDMA status might need to be cleared even for
  200. * PIO interrupts to prevent spurious/lost IRQ.
  201. */
  202. static void ich_clear_irq(ide_drive_t *drive)
  203. {
  204. ide_hwif_t *hwif = drive->hwif;
  205. u8 dma_stat;
  206. /*
  207. * ide_dma_end() needs BMDMA status for error checking.
  208. * So, skip clearing BMDMA status here and leave it
  209. * to ide_dma_end() if this is DMA interrupt.
  210. */
  211. if (drive->waiting_for_dma || hwif->dma_base == 0)
  212. return;
  213. /* clear the INTR & ERROR bits */
  214. dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
  215. /* Should we force the bit as well ? */
  216. outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS);
  217. }
  218. struct ich_laptop {
  219. u16 device;
  220. u16 subvendor;
  221. u16 subdevice;
  222. };
  223. /*
  224. * List of laptops that use short cables rather than 80 wire
  225. */
  226. static const struct ich_laptop ich_laptop[] = {
  227. /* devid, subvendor, subdev */
  228. { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
  229. { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
  230. { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
  231. { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
  232. { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
  233. { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
  234. { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */
  235. { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
  236. { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
  237. { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
  238. { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
  239. /* end marker */
  240. { 0, }
  241. };
  242. static u8 piix_cable_detect(ide_hwif_t *hwif)
  243. {
  244. struct pci_dev *pdev = to_pci_dev(hwif->dev);
  245. const struct ich_laptop *lap = &ich_laptop[0];
  246. u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;
  247. /* check for specials */
  248. while (lap->device) {
  249. if (lap->device == pdev->device &&
  250. lap->subvendor == pdev->subsystem_vendor &&
  251. lap->subdevice == pdev->subsystem_device) {
  252. return ATA_CBL_PATA40_SHORT;
  253. }
  254. lap++;
  255. }
  256. pci_read_config_byte(pdev, 0x54, &reg54h);
  257. return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
  258. }
  259. /**
  260. * init_hwif_piix - fill in the hwif for the PIIX
  261. * @hwif: IDE interface
  262. *
  263. * Set up the ide_hwif_t for the PIIX interface according to the
  264. * capabilities of the hardware.
  265. */
  266. static void init_hwif_piix(ide_hwif_t *hwif)
  267. {
  268. if (!hwif->dma_base)
  269. return;
  270. if (no_piix_dma)
  271. hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
  272. }
  273. static const struct ide_port_ops piix_port_ops = {
  274. .set_pio_mode = piix_set_pio_mode,
  275. .set_dma_mode = piix_set_dma_mode,
  276. .cable_detect = piix_cable_detect,
  277. };
  278. static const struct ide_port_ops ich_port_ops = {
  279. .set_pio_mode = piix_set_pio_mode,
  280. .set_dma_mode = piix_set_dma_mode,
  281. .clear_irq = ich_clear_irq,
  282. .cable_detect = piix_cable_detect,
  283. };
  284. #define DECLARE_PIIX_DEV(udma) \
  285. { \
  286. .name = DRV_NAME, \
  287. .init_hwif = init_hwif_piix, \
  288. .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
  289. .port_ops = &piix_port_ops, \
  290. .pio_mask = ATA_PIO4, \
  291. .swdma_mask = ATA_SWDMA2_ONLY, \
  292. .mwdma_mask = ATA_MWDMA12_ONLY, \
  293. .udma_mask = udma, \
  294. }
  295. #define DECLARE_ICH_DEV(mwdma, udma) \
  296. { \
  297. .name = DRV_NAME, \
  298. .init_chipset = init_chipset_ich, \
  299. .init_hwif = init_hwif_piix, \
  300. .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
  301. .port_ops = &ich_port_ops, \
  302. .pio_mask = ATA_PIO4, \
  303. .swdma_mask = ATA_SWDMA2_ONLY, \
  304. .mwdma_mask = mwdma, \
  305. .udma_mask = udma, \
  306. }
  307. static const struct ide_port_info piix_pci_info[] = {
  308. /* 0: MPIIX */
  309. { /*
  310. * MPIIX actually has only a single IDE channel mapped to
  311. * the primary or secondary ports depending on the value
  312. * of the bit 14 of the IDETIM register at offset 0x6c
  313. */
  314. .name = DRV_NAME,
  315. .enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
  316. .host_flags = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA,
  317. .pio_mask = ATA_PIO4,
  318. /* This is a painful system best to let it self tune for now */
  319. },
  320. /* 1: PIIXa/PIIXb/PIIX3 */
  321. DECLARE_PIIX_DEV(0x00), /* no udma */
  322. /* 2: PIIX4 */
  323. DECLARE_PIIX_DEV(ATA_UDMA2),
  324. /* 3: ICH0 */
  325. DECLARE_ICH_DEV(ATA_MWDMA12_ONLY, ATA_UDMA2),
  326. /* 4: ICH */
  327. DECLARE_ICH_DEV(ATA_MWDMA12_ONLY, ATA_UDMA4),
  328. /* 5: PIIX4 */
  329. DECLARE_PIIX_DEV(ATA_UDMA4),
  330. /* 6: ICH[2-6]/ICH[2-3]M/C-ICH/ICH5-SATA/ESB2/ICH8M */
  331. DECLARE_ICH_DEV(ATA_MWDMA12_ONLY, ATA_UDMA5),
  332. /* 7: ICH7/7-R, no MWDMA1 */
  333. DECLARE_ICH_DEV(ATA_MWDMA2_ONLY, ATA_UDMA5),
  334. };
  335. /**
  336. * piix_init_one - called when a PIIX is found
  337. * @dev: the piix device
  338. * @id: the matching pci id
  339. *
  340. * Called when the PCI registration layer (or the IDE initialization)
  341. * finds a device matching our IDE device tables.
  342. */
  343. static int piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  344. {
  345. return ide_pci_init_one(dev, &piix_pci_info[id->driver_data], NULL);
  346. }
  347. /**
  348. * piix_check_450nx - Check for problem 450NX setup
  349. *
  350. * Check for the present of 450NX errata #19 and errata #25. If
  351. * they are found, disable use of DMA IDE
  352. */
  353. static void piix_check_450nx(void)
  354. {
  355. struct pci_dev *pdev = NULL;
  356. u16 cfg;
  357. while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
  358. {
  359. /* Look for 450NX PXB. Check for problem configurations
  360. A PCI quirk checks bit 6 already */
  361. pci_read_config_word(pdev, 0x41, &cfg);
  362. /* Only on the original revision: IDE DMA can hang */
  363. if (pdev->revision == 0x00)
  364. no_piix_dma = 1;
  365. /* On all revisions below 5 PXB bus lock must be disabled for IDE */
  366. else if (cfg & (1<<14) && pdev->revision < 5)
  367. no_piix_dma = 2;
  368. }
  369. if(no_piix_dma)
  370. printk(KERN_WARNING DRV_NAME ": 450NX errata present, disabling IDE DMA.\n");
  371. if(no_piix_dma == 2)
  372. printk(KERN_WARNING DRV_NAME ": A BIOS update may resolve this.\n");
  373. }
  374. static const struct pci_device_id piix_pci_tbl[] = {
  375. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0), 1 },
  376. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1), 1 },
  377. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), 0 },
  378. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1), 1 },
  379. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB), 2 },
  380. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1), 3 },
  381. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1), 2 },
  382. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1), 4 },
  383. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1), 5 },
  384. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX), 2 },
  385. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9), 6 },
  386. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8), 6 },
  387. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 6 },
  388. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 6 },
  389. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 6 },
  390. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 6 },
  391. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11), 6 },
  392. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 6 },
  393. #ifdef CONFIG_BLK_DEV_IDE_SATA
  394. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1), 6 },
  395. #endif
  396. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2), 6 },
  397. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19), 6 },
  398. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21), 7 },
  399. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1), 6 },
  400. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18), 7 },
  401. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6), 6 },
  402. { 0, },
  403. };
  404. MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
  405. static struct pci_driver piix_pci_driver = {
  406. .name = "PIIX_IDE",
  407. .id_table = piix_pci_tbl,
  408. .probe = piix_init_one,
  409. .remove = ide_pci_remove,
  410. .suspend = ide_pci_suspend,
  411. .resume = ide_pci_resume,
  412. };
  413. static int __init piix_ide_init(void)
  414. {
  415. piix_check_450nx();
  416. return ide_pci_register_driver(&piix_pci_driver);
  417. }
  418. static void __exit piix_ide_exit(void)
  419. {
  420. pci_unregister_driver(&piix_pci_driver);
  421. }
  422. module_init(piix_ide_init);
  423. module_exit(piix_ide_exit);
  424. MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
  425. MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
  426. MODULE_LICENSE("GPL");