pdc202xx_new.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Promise TX2/TX4/TX2000/133 IDE driver
  4. *
  5. * Split from:
  6. * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
  7. * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
  8. * Copyright (C) 2005-2007 MontaVista Software, Inc.
  9. * Portions Copyright (C) 1999 Promise Technology, Inc.
  10. * Author: Frank Tiernan (frankt@promise.com)
  11. * Released under terms of General Public License
  12. */
  13. #include <linux/module.h>
  14. #include <linux/types.h>
  15. #include <linux/kernel.h>
  16. #include <linux/delay.h>
  17. #include <linux/pci.h>
  18. #include <linux/init.h>
  19. #include <linux/ide.h>
  20. #include <linux/ktime.h>
  21. #include <asm/io.h>
  22. #ifdef CONFIG_PPC_PMAC
  23. #include <asm/prom.h>
  24. #endif
  25. #define DRV_NAME "pdc202xx_new"
  26. #undef DEBUG
  27. #ifdef DEBUG
  28. #define DBG(fmt, args...) printk("%s: " fmt, __func__, ## args)
  29. #else
  30. #define DBG(fmt, args...)
  31. #endif
  32. static u8 max_dma_rate(struct pci_dev *pdev)
  33. {
  34. u8 mode;
  35. switch(pdev->device) {
  36. case PCI_DEVICE_ID_PROMISE_20277:
  37. case PCI_DEVICE_ID_PROMISE_20276:
  38. case PCI_DEVICE_ID_PROMISE_20275:
  39. case PCI_DEVICE_ID_PROMISE_20271:
  40. case PCI_DEVICE_ID_PROMISE_20269:
  41. mode = 4;
  42. break;
  43. case PCI_DEVICE_ID_PROMISE_20270:
  44. case PCI_DEVICE_ID_PROMISE_20268:
  45. mode = 3;
  46. break;
  47. default:
  48. return 0;
  49. }
  50. return mode;
  51. }
  52. /**
  53. * get_indexed_reg - Get indexed register
  54. * @hwif: for the port address
  55. * @index: index of the indexed register
  56. */
  57. static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
  58. {
  59. u8 value;
  60. outb(index, hwif->dma_base + 1);
  61. value = inb(hwif->dma_base + 3);
  62. DBG("index[%02X] value[%02X]\n", index, value);
  63. return value;
  64. }
  65. /**
  66. * set_indexed_reg - Set indexed register
  67. * @hwif: for the port address
  68. * @index: index of the indexed register
  69. */
  70. static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
  71. {
  72. outb(index, hwif->dma_base + 1);
  73. outb(value, hwif->dma_base + 3);
  74. DBG("index[%02X] value[%02X]\n", index, value);
  75. }
  76. /*
  77. * ATA Timing Tables based on 133 MHz PLL output clock.
  78. *
  79. * If the PLL outputs 100 MHz clock, the ASIC hardware will set
  80. * the timing registers automatically when "set features" command is
  81. * issued to the device. However, if the PLL output clock is 133 MHz,
  82. * the following tables must be used.
  83. */
  84. static struct pio_timing {
  85. u8 reg0c, reg0d, reg13;
  86. } pio_timings [] = {
  87. { 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
  88. { 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
  89. { 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
  90. { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
  91. { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
  92. };
  93. static struct mwdma_timing {
  94. u8 reg0e, reg0f;
  95. } mwdma_timings [] = {
  96. { 0xdf, 0x5f }, /* MWDMA mode 0 */
  97. { 0x6b, 0x27 }, /* MWDMA mode 1 */
  98. { 0x69, 0x25 }, /* MWDMA mode 2 */
  99. };
  100. static struct udma_timing {
  101. u8 reg10, reg11, reg12;
  102. } udma_timings [] = {
  103. { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
  104. { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
  105. { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
  106. { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
  107. { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
  108. { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
  109. { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
  110. };
  111. static void pdcnew_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  112. {
  113. struct pci_dev *dev = to_pci_dev(hwif->dev);
  114. u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
  115. const u8 speed = drive->dma_mode;
  116. /*
  117. * IDE core issues SETFEATURES_XFER to the drive first (thanks to
  118. * IDE_HFLAG_POST_SET_MODE in ->host_flags). PDC202xx hardware will
  119. * automatically set the timing registers based on 100 MHz PLL output.
  120. *
  121. * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
  122. * chips, we must override the default register settings...
  123. */
  124. if (max_dma_rate(dev) == 4) {
  125. u8 mode = speed & 0x07;
  126. if (speed >= XFER_UDMA_0) {
  127. set_indexed_reg(hwif, 0x10 + adj,
  128. udma_timings[mode].reg10);
  129. set_indexed_reg(hwif, 0x11 + adj,
  130. udma_timings[mode].reg11);
  131. set_indexed_reg(hwif, 0x12 + adj,
  132. udma_timings[mode].reg12);
  133. } else {
  134. set_indexed_reg(hwif, 0x0e + adj,
  135. mwdma_timings[mode].reg0e);
  136. set_indexed_reg(hwif, 0x0f + adj,
  137. mwdma_timings[mode].reg0f);
  138. }
  139. } else if (speed == XFER_UDMA_2) {
  140. /* Set tHOLD bit to 0 if using UDMA mode 2 */
  141. u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
  142. set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
  143. }
  144. }
  145. static void pdcnew_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  146. {
  147. struct pci_dev *dev = to_pci_dev(hwif->dev);
  148. u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
  149. const u8 pio = drive->pio_mode - XFER_PIO_0;
  150. if (max_dma_rate(dev) == 4) {
  151. set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c);
  152. set_indexed_reg(hwif, 0x0d + adj, pio_timings[pio].reg0d);
  153. set_indexed_reg(hwif, 0x13 + adj, pio_timings[pio].reg13);
  154. }
  155. }
  156. static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
  157. {
  158. if (get_indexed_reg(hwif, 0x0b) & 0x04)
  159. return ATA_CBL_PATA40;
  160. else
  161. return ATA_CBL_PATA80;
  162. }
  163. static void pdcnew_reset(ide_drive_t *drive)
  164. {
  165. /*
  166. * Deleted this because it is redundant from the caller.
  167. */
  168. printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
  169. drive->hwif->channel ? "Secondary" : "Primary");
  170. }
  171. /**
  172. * read_counter - Read the byte count registers
  173. * @dma_base: for the port address
  174. */
  175. static long read_counter(u32 dma_base)
  176. {
  177. u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
  178. u8 cnt0, cnt1, cnt2, cnt3;
  179. long count = 0, last;
  180. int retry = 3;
  181. do {
  182. last = count;
  183. /* Read the current count */
  184. outb(0x20, pri_dma_base + 0x01);
  185. cnt0 = inb(pri_dma_base + 0x03);
  186. outb(0x21, pri_dma_base + 0x01);
  187. cnt1 = inb(pri_dma_base + 0x03);
  188. outb(0x20, sec_dma_base + 0x01);
  189. cnt2 = inb(sec_dma_base + 0x03);
  190. outb(0x21, sec_dma_base + 0x01);
  191. cnt3 = inb(sec_dma_base + 0x03);
  192. count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;
  193. /*
  194. * The 30-bit decrementing counter is read in 4 pieces.
  195. * Incorrect value may be read when the most significant bytes
  196. * are changing...
  197. */
  198. } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));
  199. DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
  200. cnt0, cnt1, cnt2, cnt3);
  201. return count;
  202. }
  203. /**
  204. * detect_pll_input_clock - Detect the PLL input clock in Hz.
  205. * @dma_base: for the port address
  206. * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
  207. */
  208. static long detect_pll_input_clock(unsigned long dma_base)
  209. {
  210. ktime_t start_time, end_time;
  211. long start_count, end_count;
  212. long pll_input, usec_elapsed;
  213. u8 scr1;
  214. start_count = read_counter(dma_base);
  215. start_time = ktime_get();
  216. /* Start the test mode */
  217. outb(0x01, dma_base + 0x01);
  218. scr1 = inb(dma_base + 0x03);
  219. DBG("scr1[%02X]\n", scr1);
  220. outb(scr1 | 0x40, dma_base + 0x03);
  221. /* Let the counter run for 10 ms. */
  222. mdelay(10);
  223. end_count = read_counter(dma_base);
  224. end_time = ktime_get();
  225. /* Stop the test mode */
  226. outb(0x01, dma_base + 0x01);
  227. scr1 = inb(dma_base + 0x03);
  228. DBG("scr1[%02X]\n", scr1);
  229. outb(scr1 & ~0x40, dma_base + 0x03);
  230. /*
  231. * Calculate the input clock in Hz
  232. * (the clock counter is 30 bit wide and counts down)
  233. */
  234. usec_elapsed = ktime_us_delta(end_time, start_time);
  235. pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
  236. (10000000 / usec_elapsed);
  237. DBG("start[%ld] end[%ld]\n", start_count, end_count);
  238. return pll_input;
  239. }
  240. #ifdef CONFIG_PPC_PMAC
  241. static void apple_kiwi_init(struct pci_dev *pdev)
  242. {
  243. struct device_node *np = pci_device_to_OF_node(pdev);
  244. u8 conf;
  245. if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
  246. return;
  247. if (pdev->revision >= 0x03) {
  248. /* Setup chip magic config stuff (from darwin) */
  249. pci_read_config_byte (pdev, 0x40, &conf);
  250. pci_write_config_byte(pdev, 0x40, (conf | 0x01));
  251. }
  252. }
  253. #endif /* CONFIG_PPC_PMAC */
  254. static int init_chipset_pdcnew(struct pci_dev *dev)
  255. {
  256. const char *name = DRV_NAME;
  257. unsigned long dma_base = pci_resource_start(dev, 4);
  258. unsigned long sec_dma_base = dma_base + 0x08;
  259. long pll_input, pll_output, ratio;
  260. int f, r;
  261. u8 pll_ctl0, pll_ctl1;
  262. if (dma_base == 0)
  263. return -EFAULT;
  264. #ifdef CONFIG_PPC_PMAC
  265. apple_kiwi_init(dev);
  266. #endif
  267. /* Calculate the required PLL output frequency */
  268. switch(max_dma_rate(dev)) {
  269. case 4: /* it's 133 MHz for Ultra133 chips */
  270. pll_output = 133333333;
  271. break;
  272. case 3: /* and 100 MHz for Ultra100 chips */
  273. default:
  274. pll_output = 100000000;
  275. break;
  276. }
  277. /*
  278. * Detect PLL input clock.
  279. * On some systems, where PCI bus is running at non-standard clock rate
  280. * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
  281. * PDC20268 and newer chips employ PLL circuit to help correct timing
  282. * registers setting.
  283. */
  284. pll_input = detect_pll_input_clock(dma_base);
  285. printk(KERN_INFO "%s %s: PLL input clock is %ld kHz\n",
  286. name, pci_name(dev), pll_input / 1000);
  287. /* Sanity check */
  288. if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
  289. printk(KERN_ERR "%s %s: Bad PLL input clock %ld Hz, giving up!"
  290. "\n", name, pci_name(dev), pll_input);
  291. goto out;
  292. }
  293. #ifdef DEBUG
  294. DBG("pll_output is %ld Hz\n", pll_output);
  295. /* Show the current clock value of PLL control register
  296. * (maybe already configured by the BIOS)
  297. */
  298. outb(0x02, sec_dma_base + 0x01);
  299. pll_ctl0 = inb(sec_dma_base + 0x03);
  300. outb(0x03, sec_dma_base + 0x01);
  301. pll_ctl1 = inb(sec_dma_base + 0x03);
  302. DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
  303. #endif
  304. /*
  305. * Calculate the ratio of F, R and NO
  306. * POUT = (F + 2) / (( R + 2) * NO)
  307. */
  308. ratio = pll_output / (pll_input / 1000);
  309. if (ratio < 8600L) { /* 8.6x */
  310. /* Using NO = 0x01, R = 0x0d */
  311. r = 0x0d;
  312. } else if (ratio < 12900L) { /* 12.9x */
  313. /* Using NO = 0x01, R = 0x08 */
  314. r = 0x08;
  315. } else if (ratio < 16100L) { /* 16.1x */
  316. /* Using NO = 0x01, R = 0x06 */
  317. r = 0x06;
  318. } else if (ratio < 64000L) { /* 64x */
  319. r = 0x00;
  320. } else {
  321. /* Invalid ratio */
  322. printk(KERN_ERR "%s %s: Bad ratio %ld, giving up!\n",
  323. name, pci_name(dev), ratio);
  324. goto out;
  325. }
  326. f = (ratio * (r + 2)) / 1000 - 2;
  327. DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
  328. if (unlikely(f < 0 || f > 127)) {
  329. /* Invalid F */
  330. printk(KERN_ERR "%s %s: F[%d] invalid!\n",
  331. name, pci_name(dev), f);
  332. goto out;
  333. }
  334. pll_ctl0 = (u8) f;
  335. pll_ctl1 = (u8) r;
  336. DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
  337. outb(0x02, sec_dma_base + 0x01);
  338. outb(pll_ctl0, sec_dma_base + 0x03);
  339. outb(0x03, sec_dma_base + 0x01);
  340. outb(pll_ctl1, sec_dma_base + 0x03);
  341. /* Wait the PLL circuit to be stable */
  342. mdelay(30);
  343. #ifdef DEBUG
  344. /*
  345. * Show the current clock value of PLL control register
  346. */
  347. outb(0x02, sec_dma_base + 0x01);
  348. pll_ctl0 = inb(sec_dma_base + 0x03);
  349. outb(0x03, sec_dma_base + 0x01);
  350. pll_ctl1 = inb(sec_dma_base + 0x03);
  351. DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
  352. #endif
  353. out:
  354. return 0;
  355. }
  356. static struct pci_dev *pdc20270_get_dev2(struct pci_dev *dev)
  357. {
  358. struct pci_dev *dev2;
  359. dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 1,
  360. PCI_FUNC(dev->devfn)));
  361. if (dev2 &&
  362. dev2->vendor == dev->vendor &&
  363. dev2->device == dev->device) {
  364. if (dev2->irq != dev->irq) {
  365. dev2->irq = dev->irq;
  366. printk(KERN_INFO DRV_NAME " %s: PCI config space "
  367. "interrupt fixed\n", pci_name(dev));
  368. }
  369. return dev2;
  370. }
  371. return NULL;
  372. }
  373. static const struct ide_port_ops pdcnew_port_ops = {
  374. .set_pio_mode = pdcnew_set_pio_mode,
  375. .set_dma_mode = pdcnew_set_dma_mode,
  376. .resetproc = pdcnew_reset,
  377. .cable_detect = pdcnew_cable_detect,
  378. };
  379. #define DECLARE_PDCNEW_DEV(udma) \
  380. { \
  381. .name = DRV_NAME, \
  382. .init_chipset = init_chipset_pdcnew, \
  383. .port_ops = &pdcnew_port_ops, \
  384. .host_flags = IDE_HFLAG_POST_SET_MODE | \
  385. IDE_HFLAG_ERROR_STOPS_FIFO | \
  386. IDE_HFLAG_OFF_BOARD, \
  387. .pio_mask = ATA_PIO4, \
  388. .mwdma_mask = ATA_MWDMA2, \
  389. .udma_mask = udma, \
  390. }
  391. static const struct ide_port_info pdcnew_chipsets[] = {
  392. /* 0: PDC202{68,70} */ DECLARE_PDCNEW_DEV(ATA_UDMA5),
  393. /* 1: PDC202{69,71,75,76,77} */ DECLARE_PDCNEW_DEV(ATA_UDMA6),
  394. };
  395. /**
  396. * pdc202new_init_one - called when a pdc202xx is found
  397. * @dev: the pdc202new device
  398. * @id: the matching pci id
  399. *
  400. * Called when the PCI registration layer (or the IDE initialization)
  401. * finds a device matching our IDE device tables.
  402. */
  403. static int pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  404. {
  405. const struct ide_port_info *d = &pdcnew_chipsets[id->driver_data];
  406. struct pci_dev *bridge = dev->bus->self;
  407. if (dev->device == PCI_DEVICE_ID_PROMISE_20270 && bridge &&
  408. bridge->vendor == PCI_VENDOR_ID_DEC &&
  409. bridge->device == PCI_DEVICE_ID_DEC_21150) {
  410. struct pci_dev *dev2;
  411. if (PCI_SLOT(dev->devfn) & 2)
  412. return -ENODEV;
  413. dev2 = pdc20270_get_dev2(dev);
  414. if (dev2) {
  415. int ret = ide_pci_init_two(dev, dev2, d, NULL);
  416. if (ret < 0)
  417. pci_dev_put(dev2);
  418. return ret;
  419. }
  420. }
  421. if (dev->device == PCI_DEVICE_ID_PROMISE_20276 && bridge &&
  422. bridge->vendor == PCI_VENDOR_ID_INTEL &&
  423. (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
  424. bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
  425. printk(KERN_INFO DRV_NAME " %s: attached to I2O RAID controller,"
  426. " skipping\n", pci_name(dev));
  427. return -ENODEV;
  428. }
  429. return ide_pci_init_one(dev, d, NULL);
  430. }
  431. static void pdc202new_remove(struct pci_dev *dev)
  432. {
  433. struct ide_host *host = pci_get_drvdata(dev);
  434. struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
  435. ide_pci_remove(dev);
  436. pci_dev_put(dev2);
  437. }
  438. static const struct pci_device_id pdc202new_pci_tbl[] = {
  439. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
  440. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
  441. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 0 },
  442. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 1 },
  443. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 1 },
  444. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 1 },
  445. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 1 },
  446. { 0, },
  447. };
  448. MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
  449. static struct pci_driver pdc202new_pci_driver = {
  450. .name = "Promise_IDE",
  451. .id_table = pdc202new_pci_tbl,
  452. .probe = pdc202new_init_one,
  453. .remove = pdc202new_remove,
  454. .suspend = ide_pci_suspend,
  455. .resume = ide_pci_resume,
  456. };
  457. static int __init pdc202new_ide_init(void)
  458. {
  459. return ide_pci_register_driver(&pdc202new_pci_driver);
  460. }
  461. static void __exit pdc202new_ide_exit(void)
  462. {
  463. pci_unregister_driver(&pdc202new_pci_driver);
  464. }
  465. module_init(pdc202new_ide_init);
  466. module_exit(pdc202new_ide_exit);
  467. MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
  468. MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
  469. MODULE_LICENSE("GPL");