ns87415.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 1997-1998 Mark Lord <mlord@pobox.com>
  4. * Copyright (C) 1998 Eddie C. Dost <ecd@skynet.be>
  5. * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
  6. * Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org>
  7. *
  8. * Inspired by an earlier effort from David S. Miller <davem@redhat.com>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/types.h>
  12. #include <linux/kernel.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/pci.h>
  15. #include <linux/delay.h>
  16. #include <linux/ide.h>
  17. #include <linux/init.h>
  18. #include <asm/io.h>
  19. #define DRV_NAME "ns87415"
  20. #ifdef CONFIG_SUPERIO
  21. /* SUPERIO 87560 is a PoS chip that NatSem denies exists.
  22. * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
  23. * which use the integrated NS87514 cell for CD-ROM support.
  24. * i.e we have to support for CD-ROM installs.
  25. * See drivers/parisc/superio.c for more gory details.
  26. */
  27. #include <asm/superio.h>
  28. #define SUPERIO_IDE_MAX_RETRIES 25
  29. /* Because of a defect in Super I/O, all reads of the PCI DMA status
  30. * registers, IDE status register and the IDE select register need to be
  31. * retried
  32. */
  33. static u8 superio_ide_inb (unsigned long port)
  34. {
  35. u8 tmp;
  36. int retries = SUPERIO_IDE_MAX_RETRIES;
  37. /* printk(" [ reading port 0x%x with retry ] ", port); */
  38. do {
  39. tmp = inb(port);
  40. if (tmp == 0)
  41. udelay(50);
  42. } while (tmp == 0 && retries-- > 0);
  43. return tmp;
  44. }
  45. static u8 superio_read_status(ide_hwif_t *hwif)
  46. {
  47. return superio_ide_inb(hwif->io_ports.status_addr);
  48. }
  49. static u8 superio_dma_sff_read_status(ide_hwif_t *hwif)
  50. {
  51. return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
  52. }
  53. static void superio_tf_read(ide_drive_t *drive, struct ide_taskfile *tf,
  54. u8 valid)
  55. {
  56. struct ide_io_ports *io_ports = &drive->hwif->io_ports;
  57. if (valid & IDE_VALID_ERROR)
  58. tf->error = inb(io_ports->feature_addr);
  59. if (valid & IDE_VALID_NSECT)
  60. tf->nsect = inb(io_ports->nsect_addr);
  61. if (valid & IDE_VALID_LBAL)
  62. tf->lbal = inb(io_ports->lbal_addr);
  63. if (valid & IDE_VALID_LBAM)
  64. tf->lbam = inb(io_ports->lbam_addr);
  65. if (valid & IDE_VALID_LBAH)
  66. tf->lbah = inb(io_ports->lbah_addr);
  67. if (valid & IDE_VALID_DEVICE)
  68. tf->device = superio_ide_inb(io_ports->device_addr);
  69. }
  70. static void ns87415_dev_select(ide_drive_t *drive);
  71. static const struct ide_tp_ops superio_tp_ops = {
  72. .exec_command = ide_exec_command,
  73. .read_status = superio_read_status,
  74. .read_altstatus = ide_read_altstatus,
  75. .write_devctl = ide_write_devctl,
  76. .dev_select = ns87415_dev_select,
  77. .tf_load = ide_tf_load,
  78. .tf_read = superio_tf_read,
  79. .input_data = ide_input_data,
  80. .output_data = ide_output_data,
  81. };
  82. static void superio_init_iops(struct hwif_s *hwif)
  83. {
  84. struct pci_dev *pdev = to_pci_dev(hwif->dev);
  85. u32 dma_stat;
  86. u8 port = hwif->channel, tmp;
  87. dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa);
  88. /* Clear error/interrupt, enable dma */
  89. tmp = superio_ide_inb(dma_stat);
  90. outb(tmp | 0x66, dma_stat);
  91. }
  92. #else
  93. #define superio_dma_sff_read_status ide_dma_sff_read_status
  94. #endif
  95. static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
  96. /*
  97. * This routine either enables/disables (according to IDE_DFLAG_PRESENT)
  98. * the IRQ associated with the port,
  99. * and selects either PIO or DMA handshaking for the next I/O operation.
  100. */
  101. static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
  102. {
  103. ide_hwif_t *hwif = drive->hwif;
  104. struct pci_dev *dev = to_pci_dev(hwif->dev);
  105. unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
  106. unsigned long flags;
  107. local_irq_save(flags);
  108. new = *old;
  109. /* Adjust IRQ enable bit */
  110. bit = 1 << (8 + hwif->channel);
  111. if (drive->dev_flags & IDE_DFLAG_PRESENT)
  112. new &= ~bit;
  113. else
  114. new |= bit;
  115. /* Select PIO or DMA, DMA may only be selected for one drive/channel. */
  116. bit = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1));
  117. other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1));
  118. new = use_dma ? ((new & ~other) | bit) : (new & ~bit);
  119. if (new != *old) {
  120. unsigned char stat;
  121. /*
  122. * Don't change DMA engine settings while Write Buffers
  123. * are busy.
  124. */
  125. (void) pci_read_config_byte(dev, 0x43, &stat);
  126. while (stat & 0x03) {
  127. udelay(1);
  128. (void) pci_read_config_byte(dev, 0x43, &stat);
  129. }
  130. *old = new;
  131. (void) pci_write_config_dword(dev, 0x40, new);
  132. /*
  133. * And let things settle...
  134. */
  135. udelay(10);
  136. }
  137. local_irq_restore(flags);
  138. }
  139. static void ns87415_dev_select(ide_drive_t *drive)
  140. {
  141. ns87415_prepare_drive(drive,
  142. !!(drive->dev_flags & IDE_DFLAG_USING_DMA));
  143. outb(drive->select | ATA_DEVICE_OBS, drive->hwif->io_ports.device_addr);
  144. }
  145. static void ns87415_dma_start(ide_drive_t *drive)
  146. {
  147. ns87415_prepare_drive(drive, 1);
  148. ide_dma_start(drive);
  149. }
  150. static int ns87415_dma_end(ide_drive_t *drive)
  151. {
  152. ide_hwif_t *hwif = drive->hwif;
  153. u8 dma_stat = 0, dma_cmd = 0;
  154. dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
  155. /* get DMA command mode */
  156. dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
  157. /* stop DMA */
  158. outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
  159. /* from ERRATA: clear the INTR & ERROR bits */
  160. dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
  161. outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD);
  162. ns87415_prepare_drive(drive, 0);
  163. /* verify good DMA status */
  164. return (dma_stat & 7) != 4;
  165. }
  166. static void init_hwif_ns87415 (ide_hwif_t *hwif)
  167. {
  168. struct pci_dev *dev = to_pci_dev(hwif->dev);
  169. unsigned int ctrl, using_inta;
  170. u8 progif;
  171. #ifdef __sparc_v9__
  172. int timeout;
  173. u8 stat;
  174. #endif
  175. /*
  176. * We cannot probe for IRQ: both ports share common IRQ on INTA.
  177. * Also, leave IRQ masked during drive probing, to prevent infinite
  178. * interrupts from a potentially floating INTA..
  179. *
  180. * IRQs get unmasked in dev_select() when drive is first used.
  181. */
  182. (void) pci_read_config_dword(dev, 0x40, &ctrl);
  183. (void) pci_read_config_byte(dev, 0x09, &progif);
  184. /* is irq in "native" mode? */
  185. using_inta = progif & (1 << (hwif->channel << 1));
  186. if (!using_inta)
  187. using_inta = ctrl & (1 << (4 + hwif->channel));
  188. if (hwif->mate) {
  189. hwif->select_data = hwif->mate->select_data;
  190. } else {
  191. hwif->select_data = (unsigned long)
  192. &ns87415_control[ns87415_count++];
  193. ctrl |= (1 << 8) | (1 << 9); /* mask both IRQs */
  194. if (using_inta)
  195. ctrl &= ~(1 << 6); /* unmask INTA */
  196. *((unsigned int *)hwif->select_data) = ctrl;
  197. (void) pci_write_config_dword(dev, 0x40, ctrl);
  198. /*
  199. * Set prefetch size to 512 bytes for both ports,
  200. * but don't turn on/off prefetching here.
  201. */
  202. pci_write_config_byte(dev, 0x55, 0xee);
  203. #ifdef __sparc_v9__
  204. /*
  205. * XXX: Reset the device, if we don't it will not respond to
  206. * dev_select() properly during first ide_probe_port().
  207. */
  208. timeout = 10000;
  209. outb(12, hwif->io_ports.ctl_addr);
  210. udelay(10);
  211. outb(8, hwif->io_ports.ctl_addr);
  212. do {
  213. udelay(50);
  214. stat = hwif->tp_ops->read_status(hwif);
  215. if (stat == 0xff)
  216. break;
  217. } while ((stat & ATA_BUSY) && --timeout);
  218. #endif
  219. }
  220. if (!using_inta)
  221. hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel);
  222. if (!hwif->dma_base)
  223. return;
  224. outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
  225. }
  226. static const struct ide_tp_ops ns87415_tp_ops = {
  227. .exec_command = ide_exec_command,
  228. .read_status = ide_read_status,
  229. .read_altstatus = ide_read_altstatus,
  230. .write_devctl = ide_write_devctl,
  231. .dev_select = ns87415_dev_select,
  232. .tf_load = ide_tf_load,
  233. .tf_read = ide_tf_read,
  234. .input_data = ide_input_data,
  235. .output_data = ide_output_data,
  236. };
  237. static const struct ide_dma_ops ns87415_dma_ops = {
  238. .dma_host_set = ide_dma_host_set,
  239. .dma_setup = ide_dma_setup,
  240. .dma_start = ns87415_dma_start,
  241. .dma_end = ns87415_dma_end,
  242. .dma_test_irq = ide_dma_test_irq,
  243. .dma_lost_irq = ide_dma_lost_irq,
  244. .dma_timer_expiry = ide_dma_sff_timer_expiry,
  245. .dma_sff_read_status = superio_dma_sff_read_status,
  246. };
  247. static const struct ide_port_info ns87415_chipset = {
  248. .name = DRV_NAME,
  249. .init_hwif = init_hwif_ns87415,
  250. .tp_ops = &ns87415_tp_ops,
  251. .dma_ops = &ns87415_dma_ops,
  252. .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
  253. IDE_HFLAG_NO_ATAPI_DMA,
  254. };
  255. static int ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  256. {
  257. struct ide_port_info d = ns87415_chipset;
  258. #ifdef CONFIG_SUPERIO
  259. if (PCI_SLOT(dev->devfn) == 0xE) {
  260. /* Built-in - assume it's under superio. */
  261. d.init_iops = superio_init_iops;
  262. d.tp_ops = &superio_tp_ops;
  263. }
  264. #endif
  265. return ide_pci_init_one(dev, &d, NULL);
  266. }
  267. static const struct pci_device_id ns87415_pci_tbl[] = {
  268. { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
  269. { 0, },
  270. };
  271. MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
  272. static struct pci_driver ns87415_pci_driver = {
  273. .name = "NS87415_IDE",
  274. .id_table = ns87415_pci_tbl,
  275. .probe = ns87415_init_one,
  276. .remove = ide_pci_remove,
  277. .suspend = ide_pci_suspend,
  278. .resume = ide_pci_resume,
  279. };
  280. static int __init ns87415_ide_init(void)
  281. {
  282. return ide_pci_register_driver(&ns87415_pci_driver);
  283. }
  284. static void __exit ns87415_ide_exit(void)
  285. {
  286. pci_unregister_driver(&ns87415_pci_driver);
  287. }
  288. module_init(ns87415_ide_init);
  289. module_exit(ns87415_ide_exit);
  290. MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
  291. MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
  292. MODULE_LICENSE("GPL");