ide-timings.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) 1999-2001 Vojtech Pavlik
  4. * Copyright (c) 2007-2008 Bartlomiej Zolnierkiewicz
  5. *
  6. * Should you need to contact me, the author, you can do so either by
  7. * e-mail - mail your message to <vojtech@ucw.cz>, or by paper mail:
  8. * Vojtech Pavlik, Simunkova 1594, Prague 8, 182 00 Czech Republic
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/ide.h>
  12. #include <linux/module.h>
  13. /*
  14. * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
  15. * These were taken from ATA/ATAPI-6 standard, rev 0a, except
  16. * for PIO 5, which is a nonstandard extension and UDMA6, which
  17. * is currently supported only by Maxtor drives.
  18. */
  19. static struct ide_timing ide_timing[] = {
  20. { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
  21. { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
  22. { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
  23. { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
  24. { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
  25. { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
  26. { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
  27. { XFER_MW_DMA_4, 25, 0, 0, 0, 55, 20, 80, 0 },
  28. { XFER_MW_DMA_3, 25, 0, 0, 0, 65, 25, 100, 0 },
  29. { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
  30. { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
  31. { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
  32. { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
  33. { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
  34. { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
  35. { XFER_PIO_6, 10, 55, 20, 80, 55, 20, 80, 0 },
  36. { XFER_PIO_5, 15, 65, 25, 100, 65, 25, 100, 0 },
  37. { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
  38. { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
  39. { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
  40. { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
  41. { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
  42. { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 },
  43. { 0xff }
  44. };
  45. struct ide_timing *ide_timing_find_mode(u8 speed)
  46. {
  47. struct ide_timing *t;
  48. for (t = ide_timing; t->mode != speed; t++)
  49. if (t->mode == 0xff)
  50. return NULL;
  51. return t;
  52. }
  53. EXPORT_SYMBOL_GPL(ide_timing_find_mode);
  54. u16 ide_pio_cycle_time(ide_drive_t *drive, u8 pio)
  55. {
  56. u16 *id = drive->id;
  57. struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
  58. u16 cycle = 0;
  59. if (id[ATA_ID_FIELD_VALID] & 2) {
  60. if (ata_id_has_iordy(drive->id))
  61. cycle = id[ATA_ID_EIDE_PIO_IORDY];
  62. else
  63. cycle = id[ATA_ID_EIDE_PIO];
  64. /* conservative "downgrade" for all pre-ATA2 drives */
  65. if (pio < 3 && cycle < t->cycle)
  66. cycle = 0; /* use standard timing */
  67. /* Use the standard timing for the CF specific modes too */
  68. if (pio > 4 && ata_id_is_cfa(id))
  69. cycle = 0;
  70. }
  71. return cycle ? cycle : t->cycle;
  72. }
  73. EXPORT_SYMBOL_GPL(ide_pio_cycle_time);
  74. #define ENOUGH(v, unit) (((v) - 1) / (unit) + 1)
  75. #define EZ(v, unit) ((v) ? ENOUGH((v) * 1000, unit) : 0)
  76. static void ide_timing_quantize(struct ide_timing *t, struct ide_timing *q,
  77. int T, int UT)
  78. {
  79. q->setup = EZ(t->setup, T);
  80. q->act8b = EZ(t->act8b, T);
  81. q->rec8b = EZ(t->rec8b, T);
  82. q->cyc8b = EZ(t->cyc8b, T);
  83. q->active = EZ(t->active, T);
  84. q->recover = EZ(t->recover, T);
  85. q->cycle = EZ(t->cycle, T);
  86. q->udma = EZ(t->udma, UT);
  87. }
  88. void ide_timing_merge(struct ide_timing *a, struct ide_timing *b,
  89. struct ide_timing *m, unsigned int what)
  90. {
  91. if (what & IDE_TIMING_SETUP)
  92. m->setup = max(a->setup, b->setup);
  93. if (what & IDE_TIMING_ACT8B)
  94. m->act8b = max(a->act8b, b->act8b);
  95. if (what & IDE_TIMING_REC8B)
  96. m->rec8b = max(a->rec8b, b->rec8b);
  97. if (what & IDE_TIMING_CYC8B)
  98. m->cyc8b = max(a->cyc8b, b->cyc8b);
  99. if (what & IDE_TIMING_ACTIVE)
  100. m->active = max(a->active, b->active);
  101. if (what & IDE_TIMING_RECOVER)
  102. m->recover = max(a->recover, b->recover);
  103. if (what & IDE_TIMING_CYCLE)
  104. m->cycle = max(a->cycle, b->cycle);
  105. if (what & IDE_TIMING_UDMA)
  106. m->udma = max(a->udma, b->udma);
  107. }
  108. EXPORT_SYMBOL_GPL(ide_timing_merge);
  109. int ide_timing_compute(ide_drive_t *drive, u8 speed,
  110. struct ide_timing *t, int T, int UT)
  111. {
  112. u16 *id = drive->id;
  113. struct ide_timing *s, p;
  114. /*
  115. * Find the mode.
  116. */
  117. s = ide_timing_find_mode(speed);
  118. if (s == NULL)
  119. return -EINVAL;
  120. /*
  121. * Copy the timing from the table.
  122. */
  123. *t = *s;
  124. /*
  125. * If the drive is an EIDE drive, it can tell us it needs extended
  126. * PIO/MWDMA cycle timing.
  127. */
  128. if (id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
  129. memset(&p, 0, sizeof(p));
  130. if (speed >= XFER_PIO_0 && speed < XFER_SW_DMA_0) {
  131. if (speed <= XFER_PIO_2)
  132. p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO];
  133. else if ((speed <= XFER_PIO_4) ||
  134. (speed == XFER_PIO_5 && !ata_id_is_cfa(id)))
  135. p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY];
  136. } else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
  137. p.cycle = id[ATA_ID_EIDE_DMA_MIN];
  138. ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B);
  139. }
  140. /*
  141. * Convert the timing to bus clock counts.
  142. */
  143. ide_timing_quantize(t, t, T, UT);
  144. /*
  145. * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
  146. * S.M.A.R.T and some other commands. We have to ensure that the
  147. * DMA cycle timing is slower/equal than the current PIO timing.
  148. */
  149. if (speed >= XFER_SW_DMA_0) {
  150. ide_timing_compute(drive, drive->pio_mode, &p, T, UT);
  151. ide_timing_merge(&p, t, t, IDE_TIMING_ALL);
  152. }
  153. /*
  154. * Lengthen active & recovery time so that cycle time is correct.
  155. */
  156. if (t->act8b + t->rec8b < t->cyc8b) {
  157. t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
  158. t->rec8b = t->cyc8b - t->act8b;
  159. }
  160. if (t->active + t->recover < t->cycle) {
  161. t->active += (t->cycle - (t->active + t->recover)) / 2;
  162. t->recover = t->cycle - t->active;
  163. }
  164. return 0;
  165. }
  166. EXPORT_SYMBOL_GPL(ide_timing_compute);