cy82c693.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
  4. * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
  5. * Copyright (C) 2007-2011 Bartlomiej Zolnierkiewicz
  6. *
  7. * CYPRESS CY82C693 chipset IDE controller
  8. *
  9. * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/types.h>
  13. #include <linux/pci.h>
  14. #include <linux/ide.h>
  15. #include <linux/init.h>
  16. #include <asm/io.h>
  17. #define DRV_NAME "cy82c693"
  18. /*
  19. * NOTE: the value for busmaster timeout is tricky and I got it by
  20. * trial and error! By using a to low value will cause DMA timeouts
  21. * and drop IDE performance, and by using a to high value will cause
  22. * audio playback to scatter.
  23. * If you know a better value or how to calc it, please let me know.
  24. */
  25. /* twice the value written in cy82c693ub datasheet */
  26. #define BUSMASTER_TIMEOUT 0x50
  27. /*
  28. * the value above was tested on my machine and it seems to work okay
  29. */
  30. /* here are the offset definitions for the registers */
  31. #define CY82_IDE_CMDREG 0x04
  32. #define CY82_IDE_ADDRSETUP 0x48
  33. #define CY82_IDE_MASTER_IOR 0x4C
  34. #define CY82_IDE_MASTER_IOW 0x4D
  35. #define CY82_IDE_SLAVE_IOR 0x4E
  36. #define CY82_IDE_SLAVE_IOW 0x4F
  37. #define CY82_IDE_MASTER_8BIT 0x50
  38. #define CY82_IDE_SLAVE_8BIT 0x51
  39. #define CY82_INDEX_PORT 0x22
  40. #define CY82_DATA_PORT 0x23
  41. #define CY82_INDEX_CHANNEL0 0x30
  42. #define CY82_INDEX_CHANNEL1 0x31
  43. #define CY82_INDEX_TIMEOUT 0x32
  44. /*
  45. * set DMA mode a specific channel for CY82C693
  46. */
  47. static void cy82c693_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  48. {
  49. const u8 mode = drive->dma_mode;
  50. u8 single = (mode & 0x10) >> 4, index = 0, data = 0;
  51. index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;
  52. data = (mode & 3) | (single << 2);
  53. outb(index, CY82_INDEX_PORT);
  54. outb(data, CY82_DATA_PORT);
  55. /*
  56. * note: below we set the value for Bus Master IDE TimeOut Register
  57. * I'm not absolutely sure what this does, but it solved my problem
  58. * with IDE DMA and sound, so I now can play sound and work with
  59. * my IDE driver at the same time :-)
  60. *
  61. * If you know the correct (best) value for this register please
  62. * let me know - ASK
  63. */
  64. data = BUSMASTER_TIMEOUT;
  65. outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
  66. outb(data, CY82_DATA_PORT);
  67. }
  68. static void cy82c693_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  69. {
  70. struct pci_dev *dev = to_pci_dev(hwif->dev);
  71. int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
  72. const unsigned long T = 1000000 / bus_speed;
  73. unsigned int addrCtrl;
  74. struct ide_timing t;
  75. u8 time_16, time_8;
  76. /* select primary or secondary channel */
  77. if (drive->dn > 1) { /* drive is on the secondary channel */
  78. dev = pci_get_slot(dev->bus, dev->devfn+1);
  79. if (!dev) {
  80. printk(KERN_ERR "%s: tune_drive: "
  81. "Cannot find secondary interface!\n",
  82. drive->name);
  83. return;
  84. }
  85. }
  86. ide_timing_compute(drive, drive->pio_mode, &t, T, 1);
  87. time_16 = clamp_val(t.recover - 1, 0, 15) |
  88. (clamp_val(t.active - 1, 0, 15) << 4);
  89. time_8 = clamp_val(t.act8b - 1, 0, 15) |
  90. (clamp_val(t.rec8b - 1, 0, 15) << 4);
  91. /* now let's write the clocks registers */
  92. if ((drive->dn & 1) == 0) {
  93. /*
  94. * set master drive
  95. * address setup control register
  96. * is 32 bit !!!
  97. */
  98. pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
  99. addrCtrl &= (~0xF);
  100. addrCtrl |= clamp_val(t.setup - 1, 0, 15);
  101. pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
  102. /* now let's set the remaining registers */
  103. pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, time_16);
  104. pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, time_16);
  105. pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, time_8);
  106. } else {
  107. /*
  108. * set slave drive
  109. * address setup control register
  110. * is 32 bit !!!
  111. */
  112. pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
  113. addrCtrl &= (~0xF0);
  114. addrCtrl |= (clamp_val(t.setup - 1, 0, 15) << 4);
  115. pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
  116. /* now let's set the remaining registers */
  117. pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, time_16);
  118. pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, time_16);
  119. pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, time_8);
  120. }
  121. if (drive->dn > 1)
  122. pci_dev_put(dev);
  123. }
  124. static void init_iops_cy82c693(ide_hwif_t *hwif)
  125. {
  126. static ide_hwif_t *primary;
  127. struct pci_dev *dev = to_pci_dev(hwif->dev);
  128. if (PCI_FUNC(dev->devfn) == 1)
  129. primary = hwif;
  130. else {
  131. hwif->mate = primary;
  132. hwif->channel = 1;
  133. }
  134. }
  135. static const struct ide_port_ops cy82c693_port_ops = {
  136. .set_pio_mode = cy82c693_set_pio_mode,
  137. .set_dma_mode = cy82c693_set_dma_mode,
  138. };
  139. static const struct ide_port_info cy82c693_chipset = {
  140. .name = DRV_NAME,
  141. .init_iops = init_iops_cy82c693,
  142. .port_ops = &cy82c693_port_ops,
  143. .host_flags = IDE_HFLAG_SINGLE,
  144. .pio_mask = ATA_PIO4,
  145. .swdma_mask = ATA_SWDMA2,
  146. .mwdma_mask = ATA_MWDMA2,
  147. };
  148. static int cy82c693_init_one(struct pci_dev *dev,
  149. const struct pci_device_id *id)
  150. {
  151. struct pci_dev *dev2;
  152. int ret = -ENODEV;
  153. /* CY82C693 is more than only a IDE controller.
  154. Function 1 is primary IDE channel, function 2 - secondary. */
  155. if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
  156. PCI_FUNC(dev->devfn) == 1) {
  157. dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
  158. ret = ide_pci_init_two(dev, dev2, &cy82c693_chipset, NULL);
  159. if (ret)
  160. pci_dev_put(dev2);
  161. }
  162. return ret;
  163. }
  164. static void cy82c693_remove(struct pci_dev *dev)
  165. {
  166. struct ide_host *host = pci_get_drvdata(dev);
  167. struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
  168. ide_pci_remove(dev);
  169. pci_dev_put(dev2);
  170. }
  171. static const struct pci_device_id cy82c693_pci_tbl[] = {
  172. { PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
  173. { 0, },
  174. };
  175. MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
  176. static struct pci_driver cy82c693_pci_driver = {
  177. .name = "Cypress_IDE",
  178. .id_table = cy82c693_pci_tbl,
  179. .probe = cy82c693_init_one,
  180. .remove = cy82c693_remove,
  181. .suspend = ide_pci_suspend,
  182. .resume = ide_pci_resume,
  183. };
  184. static int __init cy82c693_ide_init(void)
  185. {
  186. return ide_pci_register_driver(&cy82c693_pci_driver);
  187. }
  188. static void __exit cy82c693_ide_exit(void)
  189. {
  190. pci_unregister_driver(&cy82c693_pci_driver);
  191. }
  192. module_init(cy82c693_ide_init);
  193. module_exit(cy82c693_ide_exit);
  194. MODULE_AUTHOR("Andreas Krebs, Andre Hedrick, Bartlomiej Zolnierkiewicz");
  195. MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
  196. MODULE_LICENSE("GPL");