cs5530.c 8.1 KB

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  1. /*
  2. * Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
  3. * Copyright (C) 2000 Mark Lord <mlord@pobox.com>
  4. * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
  5. *
  6. * May be copied or modified under the terms of the GNU General Public License
  7. *
  8. * Development of this chipset driver was funded
  9. * by the nice folks at National Semiconductor.
  10. *
  11. * Documentation:
  12. * CS5530 documentation available from National Semiconductor.
  13. */
  14. #include <linux/module.h>
  15. #include <linux/types.h>
  16. #include <linux/kernel.h>
  17. #include <linux/pci.h>
  18. #include <linux/init.h>
  19. #include <linux/ide.h>
  20. #include <asm/io.h>
  21. #define DRV_NAME "cs5530"
  22. /*
  23. * Here are the standard PIO mode 0-4 timings for each "format".
  24. * Format-0 uses fast data reg timings, with slower command reg timings.
  25. * Format-1 uses fast timings for all registers, but won't work with all drives.
  26. */
  27. static unsigned int cs5530_pio_timings[2][5] = {
  28. {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
  29. {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
  30. };
  31. /*
  32. * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
  33. */
  34. #define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
  35. #define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
  36. /**
  37. * cs5530_set_pio_mode - set host controller for PIO mode
  38. * @hwif: port
  39. * @drive: drive
  40. *
  41. * Handles setting of PIO mode for the chipset.
  42. *
  43. * The init_hwif_cs5530() routine guarantees that all drives
  44. * will have valid default PIO timings set up before we get here.
  45. */
  46. static void cs5530_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  47. {
  48. unsigned long basereg = CS5530_BASEREG(hwif);
  49. unsigned int format = (inl(basereg + 4) >> 31) & 1;
  50. const u8 pio = drive->pio_mode - XFER_PIO_0;
  51. outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
  52. }
  53. /**
  54. * cs5530_udma_filter - UDMA filter
  55. * @drive: drive
  56. *
  57. * cs5530_udma_filter() does UDMA mask filtering for the given drive
  58. * taking into the consideration capabilities of the mate device.
  59. *
  60. * The CS5530 specifies that two drives sharing a cable cannot mix
  61. * UDMA/MDMA. It has to be one or the other, for the pair, though
  62. * different timings can still be chosen for each drive. We could
  63. * set the appropriate timing bits on the fly, but that might be
  64. * a bit confusing. So, for now we statically handle this requirement
  65. * by looking at our mate drive to see what it is capable of, before
  66. * choosing a mode for our own drive.
  67. *
  68. * Note: This relies on the fact we never fail from UDMA to MWDMA2
  69. * but instead drop to PIO.
  70. */
  71. static u8 cs5530_udma_filter(ide_drive_t *drive)
  72. {
  73. ide_hwif_t *hwif = drive->hwif;
  74. ide_drive_t *mate = ide_get_pair_dev(drive);
  75. u16 *mateid;
  76. u8 mask = hwif->ultra_mask;
  77. if (mate == NULL)
  78. goto out;
  79. mateid = mate->id;
  80. if (ata_id_has_dma(mateid) && __ide_dma_bad_drive(mate) == 0) {
  81. if ((mateid[ATA_ID_FIELD_VALID] & 4) &&
  82. (mateid[ATA_ID_UDMA_MODES] & 7))
  83. goto out;
  84. if (mateid[ATA_ID_MWDMA_MODES] & 7)
  85. mask = 0;
  86. }
  87. out:
  88. return mask;
  89. }
  90. static void cs5530_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  91. {
  92. unsigned long basereg;
  93. unsigned int reg, timings = 0;
  94. switch (drive->dma_mode) {
  95. case XFER_UDMA_0: timings = 0x00921250; break;
  96. case XFER_UDMA_1: timings = 0x00911140; break;
  97. case XFER_UDMA_2: timings = 0x00911030; break;
  98. case XFER_MW_DMA_0: timings = 0x00077771; break;
  99. case XFER_MW_DMA_1: timings = 0x00012121; break;
  100. case XFER_MW_DMA_2: timings = 0x00002020; break;
  101. }
  102. basereg = CS5530_BASEREG(hwif);
  103. reg = inl(basereg + 4); /* get drive0 config register */
  104. timings |= reg & 0x80000000; /* preserve PIO format bit */
  105. if ((drive-> dn & 1) == 0) { /* are we configuring drive0? */
  106. outl(timings, basereg + 4); /* write drive0 config register */
  107. } else {
  108. if (timings & 0x00100000)
  109. reg |= 0x00100000; /* enable UDMA timings for both drives */
  110. else
  111. reg &= ~0x00100000; /* disable UDMA timings for both drives */
  112. outl(reg, basereg + 4); /* write drive0 config register */
  113. outl(timings, basereg + 12); /* write drive1 config register */
  114. }
  115. }
  116. /**
  117. * init_chipset_5530 - set up 5530 bridge
  118. * @dev: PCI device
  119. *
  120. * Initialize the cs5530 bridge for reliable IDE DMA operation.
  121. */
  122. static int init_chipset_cs5530(struct pci_dev *dev)
  123. {
  124. struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
  125. if (pci_resource_start(dev, 4) == 0)
  126. return -EFAULT;
  127. dev = NULL;
  128. while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
  129. switch (dev->device) {
  130. case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
  131. master_0 = pci_dev_get(dev);
  132. break;
  133. case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
  134. cs5530_0 = pci_dev_get(dev);
  135. break;
  136. }
  137. }
  138. if (!master_0) {
  139. printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
  140. goto out;
  141. }
  142. if (!cs5530_0) {
  143. printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
  144. goto out;
  145. }
  146. /*
  147. * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
  148. * --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
  149. */
  150. pci_set_master(cs5530_0);
  151. pci_try_set_mwi(cs5530_0);
  152. /*
  153. * Set PCI CacheLineSize to 16-bytes:
  154. * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
  155. */
  156. pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
  157. /*
  158. * Disable trapping of UDMA register accesses (Win98 hack):
  159. * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
  160. */
  161. pci_write_config_word(cs5530_0, 0xd0, 0x5006);
  162. /*
  163. * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
  164. * The other settings are what is necessary to get the register
  165. * into a sane state for IDE DMA operation.
  166. */
  167. pci_write_config_byte(master_0, 0x40, 0x1e);
  168. /*
  169. * Set max PCI burst size (16-bytes seems to work best):
  170. * 16bytes: set bit-1 at 0x41 (reg value of 0x16)
  171. * all others: clear bit-1 at 0x41, and do:
  172. * 128bytes: OR 0x00 at 0x41
  173. * 256bytes: OR 0x04 at 0x41
  174. * 512bytes: OR 0x08 at 0x41
  175. * 1024bytes: OR 0x0c at 0x41
  176. */
  177. pci_write_config_byte(master_0, 0x41, 0x14);
  178. /*
  179. * These settings are necessary to get the chip
  180. * into a sane state for IDE DMA operation.
  181. */
  182. pci_write_config_byte(master_0, 0x42, 0x00);
  183. pci_write_config_byte(master_0, 0x43, 0xc1);
  184. out:
  185. pci_dev_put(master_0);
  186. pci_dev_put(cs5530_0);
  187. return 0;
  188. }
  189. /**
  190. * init_hwif_cs5530 - initialise an IDE channel
  191. * @hwif: IDE to initialize
  192. *
  193. * This gets invoked by the IDE driver once for each channel. It
  194. * performs channel-specific pre-initialization before drive probing.
  195. */
  196. static void init_hwif_cs5530 (ide_hwif_t *hwif)
  197. {
  198. unsigned long basereg;
  199. u32 d0_timings;
  200. basereg = CS5530_BASEREG(hwif);
  201. d0_timings = inl(basereg + 0);
  202. if (CS5530_BAD_PIO(d0_timings))
  203. outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
  204. if (CS5530_BAD_PIO(inl(basereg + 8)))
  205. outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
  206. }
  207. static const struct ide_port_ops cs5530_port_ops = {
  208. .set_pio_mode = cs5530_set_pio_mode,
  209. .set_dma_mode = cs5530_set_dma_mode,
  210. .udma_filter = cs5530_udma_filter,
  211. };
  212. static const struct ide_port_info cs5530_chipset = {
  213. .name = DRV_NAME,
  214. .init_chipset = init_chipset_cs5530,
  215. .init_hwif = init_hwif_cs5530,
  216. .port_ops = &cs5530_port_ops,
  217. .host_flags = IDE_HFLAG_SERIALIZE |
  218. IDE_HFLAG_POST_SET_MODE,
  219. .pio_mask = ATA_PIO4,
  220. .mwdma_mask = ATA_MWDMA2,
  221. .udma_mask = ATA_UDMA2,
  222. };
  223. static int cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  224. {
  225. return ide_pci_init_one(dev, &cs5530_chipset, NULL);
  226. }
  227. static const struct pci_device_id cs5530_pci_tbl[] = {
  228. { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), 0 },
  229. { 0, },
  230. };
  231. MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);
  232. static struct pci_driver cs5530_pci_driver = {
  233. .name = "CS5530 IDE",
  234. .id_table = cs5530_pci_tbl,
  235. .probe = cs5530_init_one,
  236. .remove = ide_pci_remove,
  237. .suspend = ide_pci_suspend,
  238. .resume = ide_pci_resume,
  239. };
  240. static int __init cs5530_ide_init(void)
  241. {
  242. return ide_pci_register_driver(&cs5530_pci_driver);
  243. }
  244. static void __exit cs5530_ide_exit(void)
  245. {
  246. pci_unregister_driver(&cs5530_pci_driver);
  247. }
  248. module_init(cs5530_ide_init);
  249. module_exit(cs5530_ide_exit);
  250. MODULE_AUTHOR("Mark Lord");
  251. MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
  252. MODULE_LICENSE("GPL");