cmd64x.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
  4. * Due to massive hardware bugs, UltraDMA is only supported
  5. * on the 646U2 and not on the 646U.
  6. *
  7. * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
  8. * Copyright (C) 1998 David S. Miller (davem@redhat.com)
  9. *
  10. * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
  11. * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
  12. * Copyright (C) 2007,2009 MontaVista Software, Inc. <source@mvista.com>
  13. */
  14. #include <linux/module.h>
  15. #include <linux/types.h>
  16. #include <linux/pci.h>
  17. #include <linux/ide.h>
  18. #include <linux/init.h>
  19. #include <asm/io.h>
  20. #define DRV_NAME "cmd64x"
  21. /*
  22. * CMD64x specific registers definition.
  23. */
  24. #define CFR 0x50
  25. #define CFR_INTR_CH0 0x04
  26. #define CMDTIM 0x52
  27. #define ARTTIM0 0x53
  28. #define DRWTIM0 0x54
  29. #define ARTTIM1 0x55
  30. #define DRWTIM1 0x56
  31. #define ARTTIM23 0x57
  32. #define ARTTIM23_DIS_RA2 0x04
  33. #define ARTTIM23_DIS_RA3 0x08
  34. #define ARTTIM23_INTR_CH1 0x10
  35. #define DRWTIM2 0x58
  36. #define BRST 0x59
  37. #define DRWTIM3 0x5b
  38. #define BMIDECR0 0x70
  39. #define MRDMODE 0x71
  40. #define MRDMODE_INTR_CH0 0x04
  41. #define MRDMODE_INTR_CH1 0x08
  42. #define UDIDETCR0 0x73
  43. #define DTPR0 0x74
  44. #define BMIDECR1 0x78
  45. #define BMIDECSR 0x79
  46. #define UDIDETCR1 0x7B
  47. #define DTPR1 0x7C
  48. static void cmd64x_program_timings(ide_drive_t *drive, u8 mode)
  49. {
  50. ide_hwif_t *hwif = drive->hwif;
  51. struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  52. int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
  53. const unsigned long T = 1000000 / bus_speed;
  54. static const u8 recovery_values[] =
  55. {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
  56. static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
  57. static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
  58. static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
  59. struct ide_timing t;
  60. u8 arttim = 0;
  61. if (drive->dn >= ARRAY_SIZE(drwtim_regs))
  62. return;
  63. ide_timing_compute(drive, mode, &t, T, 0);
  64. /*
  65. * In case we've got too long recovery phase, try to lengthen
  66. * the active phase
  67. */
  68. if (t.recover > 16) {
  69. t.active += t.recover - 16;
  70. t.recover = 16;
  71. }
  72. if (t.active > 16) /* shouldn't actually happen... */
  73. t.active = 16;
  74. /*
  75. * Convert values to internal chipset representation
  76. */
  77. t.recover = recovery_values[t.recover];
  78. t.active &= 0x0f;
  79. /* Program the active/recovery counts into the DRWTIM register */
  80. pci_write_config_byte(dev, drwtim_regs[drive->dn],
  81. (t.active << 4) | t.recover);
  82. /*
  83. * The primary channel has individual address setup timing registers
  84. * for each drive and the hardware selects the slowest timing itself.
  85. * The secondary channel has one common register and we have to select
  86. * the slowest address setup timing ourselves.
  87. */
  88. if (hwif->channel) {
  89. ide_drive_t *pair = ide_get_pair_dev(drive);
  90. if (pair) {
  91. struct ide_timing tp;
  92. ide_timing_compute(pair, pair->pio_mode, &tp, T, 0);
  93. ide_timing_merge(&t, &tp, &t, IDE_TIMING_SETUP);
  94. if (pair->dma_mode) {
  95. ide_timing_compute(pair, pair->dma_mode,
  96. &tp, T, 0);
  97. ide_timing_merge(&tp, &t, &t, IDE_TIMING_SETUP);
  98. }
  99. }
  100. }
  101. if (t.setup > 5) /* shouldn't actually happen... */
  102. t.setup = 5;
  103. /*
  104. * Program the address setup clocks into the ARTTIM registers.
  105. * Avoid clearing the secondary channel's interrupt bit.
  106. */
  107. (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
  108. if (hwif->channel)
  109. arttim &= ~ARTTIM23_INTR_CH1;
  110. arttim &= ~0xc0;
  111. arttim |= setup_values[t.setup];
  112. (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
  113. }
  114. /*
  115. * Attempts to set drive's PIO mode.
  116. * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
  117. */
  118. static void cmd64x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  119. {
  120. const u8 pio = drive->pio_mode - XFER_PIO_0;
  121. /*
  122. * Filter out the prefetch control values
  123. * to prevent PIO5 from being programmed
  124. */
  125. if (pio == 8 || pio == 9)
  126. return;
  127. cmd64x_program_timings(drive, XFER_PIO_0 + pio);
  128. }
  129. static void cmd64x_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  130. {
  131. struct pci_dev *dev = to_pci_dev(hwif->dev);
  132. u8 unit = drive->dn & 0x01;
  133. u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
  134. const u8 speed = drive->dma_mode;
  135. pci_read_config_byte(dev, pciU, &regU);
  136. regU &= ~(unit ? 0xCA : 0x35);
  137. switch(speed) {
  138. case XFER_UDMA_5:
  139. regU |= unit ? 0x0A : 0x05;
  140. break;
  141. case XFER_UDMA_4:
  142. regU |= unit ? 0x4A : 0x15;
  143. break;
  144. case XFER_UDMA_3:
  145. regU |= unit ? 0x8A : 0x25;
  146. break;
  147. case XFER_UDMA_2:
  148. regU |= unit ? 0x42 : 0x11;
  149. break;
  150. case XFER_UDMA_1:
  151. regU |= unit ? 0x82 : 0x21;
  152. break;
  153. case XFER_UDMA_0:
  154. regU |= unit ? 0xC2 : 0x31;
  155. break;
  156. case XFER_MW_DMA_2:
  157. case XFER_MW_DMA_1:
  158. case XFER_MW_DMA_0:
  159. cmd64x_program_timings(drive, speed);
  160. break;
  161. }
  162. pci_write_config_byte(dev, pciU, regU);
  163. }
  164. static void cmd648_clear_irq(ide_drive_t *drive)
  165. {
  166. ide_hwif_t *hwif = drive->hwif;
  167. struct pci_dev *dev = to_pci_dev(hwif->dev);
  168. unsigned long base = pci_resource_start(dev, 4);
  169. u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
  170. MRDMODE_INTR_CH0;
  171. u8 mrdmode = inb(base + 1);
  172. /* clear the interrupt bit */
  173. outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
  174. base + 1);
  175. }
  176. static void cmd64x_clear_irq(ide_drive_t *drive)
  177. {
  178. ide_hwif_t *hwif = drive->hwif;
  179. struct pci_dev *dev = to_pci_dev(hwif->dev);
  180. int irq_reg = hwif->channel ? ARTTIM23 : CFR;
  181. u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
  182. CFR_INTR_CH0;
  183. u8 irq_stat = 0;
  184. (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
  185. /* clear the interrupt bit */
  186. (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
  187. }
  188. static int cmd648_test_irq(ide_hwif_t *hwif)
  189. {
  190. struct pci_dev *dev = to_pci_dev(hwif->dev);
  191. unsigned long base = pci_resource_start(dev, 4);
  192. u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
  193. MRDMODE_INTR_CH0;
  194. u8 mrdmode = inb(base + 1);
  195. pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",
  196. hwif->name, mrdmode, irq_mask);
  197. return (mrdmode & irq_mask) ? 1 : 0;
  198. }
  199. static int cmd64x_test_irq(ide_hwif_t *hwif)
  200. {
  201. struct pci_dev *dev = to_pci_dev(hwif->dev);
  202. int irq_reg = hwif->channel ? ARTTIM23 : CFR;
  203. u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
  204. CFR_INTR_CH0;
  205. u8 irq_stat = 0;
  206. (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
  207. pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n",
  208. hwif->name, irq_stat, irq_mask);
  209. return (irq_stat & irq_mask) ? 1 : 0;
  210. }
  211. /*
  212. * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
  213. * event order for DMA transfers.
  214. */
  215. static int cmd646_1_dma_end(ide_drive_t *drive)
  216. {
  217. ide_hwif_t *hwif = drive->hwif;
  218. u8 dma_stat = 0, dma_cmd = 0;
  219. /* get DMA status */
  220. dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
  221. /* read DMA command state */
  222. dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
  223. /* stop DMA */
  224. outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
  225. /* clear the INTR & ERROR bits */
  226. outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
  227. /* verify good DMA status */
  228. return (dma_stat & 7) != 4;
  229. }
  230. static int init_chipset_cmd64x(struct pci_dev *dev)
  231. {
  232. u8 mrdmode = 0;
  233. /* Set a good latency timer and cache line size value. */
  234. (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
  235. /* FIXME: pci_set_master() to ensure a good latency timer value */
  236. /*
  237. * Enable interrupts, select MEMORY READ LINE for reads.
  238. *
  239. * NOTE: although not mentioned in the PCI0646U specs,
  240. * bits 0-1 are write only and won't be read back as
  241. * set or not -- PCI0646U2 specs clarify this point.
  242. */
  243. (void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
  244. mrdmode &= ~0x30;
  245. (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
  246. return 0;
  247. }
  248. static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
  249. {
  250. struct pci_dev *dev = to_pci_dev(hwif->dev);
  251. u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01;
  252. switch (dev->device) {
  253. case PCI_DEVICE_ID_CMD_648:
  254. case PCI_DEVICE_ID_CMD_649:
  255. pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
  256. return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
  257. default:
  258. return ATA_CBL_PATA40;
  259. }
  260. }
  261. static const struct ide_port_ops cmd64x_port_ops = {
  262. .set_pio_mode = cmd64x_set_pio_mode,
  263. .set_dma_mode = cmd64x_set_dma_mode,
  264. .clear_irq = cmd64x_clear_irq,
  265. .test_irq = cmd64x_test_irq,
  266. .cable_detect = cmd64x_cable_detect,
  267. };
  268. static const struct ide_port_ops cmd648_port_ops = {
  269. .set_pio_mode = cmd64x_set_pio_mode,
  270. .set_dma_mode = cmd64x_set_dma_mode,
  271. .clear_irq = cmd648_clear_irq,
  272. .test_irq = cmd648_test_irq,
  273. .cable_detect = cmd64x_cable_detect,
  274. };
  275. static const struct ide_dma_ops cmd646_rev1_dma_ops = {
  276. .dma_host_set = ide_dma_host_set,
  277. .dma_setup = ide_dma_setup,
  278. .dma_start = ide_dma_start,
  279. .dma_end = cmd646_1_dma_end,
  280. .dma_test_irq = ide_dma_test_irq,
  281. .dma_lost_irq = ide_dma_lost_irq,
  282. .dma_timer_expiry = ide_dma_sff_timer_expiry,
  283. .dma_sff_read_status = ide_dma_sff_read_status,
  284. };
  285. static const struct ide_port_info cmd64x_chipsets[] = {
  286. { /* 0: CMD643 */
  287. .name = DRV_NAME,
  288. .init_chipset = init_chipset_cmd64x,
  289. .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
  290. .port_ops = &cmd64x_port_ops,
  291. .host_flags = IDE_HFLAG_CLEAR_SIMPLEX |
  292. IDE_HFLAG_ABUSE_PREFETCH |
  293. IDE_HFLAG_SERIALIZE,
  294. .pio_mask = ATA_PIO5,
  295. .mwdma_mask = ATA_MWDMA2,
  296. .udma_mask = 0x00, /* no udma */
  297. },
  298. { /* 1: CMD646 */
  299. .name = DRV_NAME,
  300. .init_chipset = init_chipset_cmd64x,
  301. .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
  302. .port_ops = &cmd648_port_ops,
  303. .host_flags = IDE_HFLAG_ABUSE_PREFETCH |
  304. IDE_HFLAG_SERIALIZE,
  305. .pio_mask = ATA_PIO5,
  306. .mwdma_mask = ATA_MWDMA2,
  307. .udma_mask = ATA_UDMA2,
  308. },
  309. { /* 2: CMD648 */
  310. .name = DRV_NAME,
  311. .init_chipset = init_chipset_cmd64x,
  312. .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
  313. .port_ops = &cmd648_port_ops,
  314. .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
  315. .pio_mask = ATA_PIO5,
  316. .mwdma_mask = ATA_MWDMA2,
  317. .udma_mask = ATA_UDMA4,
  318. },
  319. { /* 3: CMD649 */
  320. .name = DRV_NAME,
  321. .init_chipset = init_chipset_cmd64x,
  322. .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
  323. .port_ops = &cmd648_port_ops,
  324. .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
  325. .pio_mask = ATA_PIO5,
  326. .mwdma_mask = ATA_MWDMA2,
  327. .udma_mask = ATA_UDMA5,
  328. }
  329. };
  330. static int cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  331. {
  332. struct ide_port_info d;
  333. u8 idx = id->driver_data;
  334. d = cmd64x_chipsets[idx];
  335. if (idx == 1) {
  336. /*
  337. * UltraDMA only supported on PCI646U and PCI646U2, which
  338. * correspond to revisions 0x03, 0x05 and 0x07 respectively.
  339. * Actually, although the CMD tech support people won't
  340. * tell me the details, the 0x03 revision cannot support
  341. * UDMA correctly without hardware modifications, and even
  342. * then it only works with Quantum disks due to some
  343. * hold time assumptions in the 646U part which are fixed
  344. * in the 646U2.
  345. *
  346. * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
  347. */
  348. if (dev->revision < 5) {
  349. d.udma_mask = 0x00;
  350. /*
  351. * The original PCI0646 didn't have the primary
  352. * channel enable bit, it appeared starting with
  353. * PCI0646U (i.e. revision ID 3).
  354. */
  355. if (dev->revision < 3) {
  356. d.enablebits[0].reg = 0;
  357. d.port_ops = &cmd64x_port_ops;
  358. if (dev->revision == 1)
  359. d.dma_ops = &cmd646_rev1_dma_ops;
  360. }
  361. }
  362. }
  363. return ide_pci_init_one(dev, &d, NULL);
  364. }
  365. static const struct pci_device_id cmd64x_pci_tbl[] = {
  366. { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
  367. { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
  368. { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
  369. { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
  370. { 0, },
  371. };
  372. MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
  373. static struct pci_driver cmd64x_pci_driver = {
  374. .name = "CMD64x_IDE",
  375. .id_table = cmd64x_pci_tbl,
  376. .probe = cmd64x_init_one,
  377. .remove = ide_pci_remove,
  378. .suspend = ide_pci_suspend,
  379. .resume = ide_pci_resume,
  380. };
  381. static int __init cmd64x_ide_init(void)
  382. {
  383. return ide_pci_register_driver(&cmd64x_pci_driver);
  384. }
  385. static void __exit cmd64x_ide_exit(void)
  386. {
  387. pci_unregister_driver(&cmd64x_pci_driver);
  388. }
  389. module_init(cmd64x_ide_init);
  390. module_exit(cmd64x_ide_exit);
  391. MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick, Bartlomiej Zolnierkiewicz");
  392. MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
  393. MODULE_LICENSE("GPL");