mipi.c 15 KB

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  1. /*
  2. * Copyright (C) 2013 NVIDIA Corporation
  3. *
  4. * Permission to use, copy, modify, distribute, and sell this software and its
  5. * documentation for any purpose is hereby granted without fee, provided that
  6. * the above copyright notice appear in all copies and that both that copyright
  7. * notice and this permission notice appear in supporting documentation, and
  8. * that the name of the copyright holders not be used in advertising or
  9. * publicity pertaining to distribution of the software without specific,
  10. * written prior permission. The copyright holders make no representations
  11. * about the suitability of this software for any purpose. It is provided "as
  12. * is" without express or implied warranty.
  13. *
  14. * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  15. * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  16. * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  17. * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
  18. * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  19. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
  20. * OF THIS SOFTWARE.
  21. */
  22. #include <linux/clk.h>
  23. #include <linux/host1x.h>
  24. #include <linux/io.h>
  25. #include <linux/iopoll.h>
  26. #include <linux/of_platform.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/slab.h>
  29. #include "dev.h"
  30. #define MIPI_CAL_CTRL 0x00
  31. #define MIPI_CAL_CTRL_NOISE_FILTER(x) (((x) & 0xf) << 26)
  32. #define MIPI_CAL_CTRL_PRESCALE(x) (((x) & 0x3) << 24)
  33. #define MIPI_CAL_CTRL_CLKEN_OVR (1 << 4)
  34. #define MIPI_CAL_CTRL_START (1 << 0)
  35. #define MIPI_CAL_AUTOCAL_CTRL 0x01
  36. #define MIPI_CAL_STATUS 0x02
  37. #define MIPI_CAL_STATUS_DONE (1 << 16)
  38. #define MIPI_CAL_STATUS_ACTIVE (1 << 0)
  39. #define MIPI_CAL_CONFIG_CSIA 0x05
  40. #define MIPI_CAL_CONFIG_CSIB 0x06
  41. #define MIPI_CAL_CONFIG_CSIC 0x07
  42. #define MIPI_CAL_CONFIG_CSID 0x08
  43. #define MIPI_CAL_CONFIG_CSIE 0x09
  44. #define MIPI_CAL_CONFIG_CSIF 0x0a
  45. #define MIPI_CAL_CONFIG_DSIA 0x0e
  46. #define MIPI_CAL_CONFIG_DSIB 0x0f
  47. #define MIPI_CAL_CONFIG_DSIC 0x10
  48. #define MIPI_CAL_CONFIG_DSID 0x11
  49. #define MIPI_CAL_CONFIG_DSIA_CLK 0x19
  50. #define MIPI_CAL_CONFIG_DSIB_CLK 0x1a
  51. #define MIPI_CAL_CONFIG_CSIAB_CLK 0x1b
  52. #define MIPI_CAL_CONFIG_DSIC_CLK 0x1c
  53. #define MIPI_CAL_CONFIG_CSICD_CLK 0x1c
  54. #define MIPI_CAL_CONFIG_DSID_CLK 0x1d
  55. #define MIPI_CAL_CONFIG_CSIE_CLK 0x1d
  56. /* for data and clock lanes */
  57. #define MIPI_CAL_CONFIG_SELECT (1 << 21)
  58. /* for data lanes */
  59. #define MIPI_CAL_CONFIG_HSPDOS(x) (((x) & 0x1f) << 16)
  60. #define MIPI_CAL_CONFIG_HSPUOS(x) (((x) & 0x1f) << 8)
  61. #define MIPI_CAL_CONFIG_TERMOS(x) (((x) & 0x1f) << 0)
  62. /* for clock lanes */
  63. #define MIPI_CAL_CONFIG_HSCLKPDOSD(x) (((x) & 0x1f) << 8)
  64. #define MIPI_CAL_CONFIG_HSCLKPUOSD(x) (((x) & 0x1f) << 0)
  65. #define MIPI_CAL_BIAS_PAD_CFG0 0x16
  66. #define MIPI_CAL_BIAS_PAD_PDVCLAMP (1 << 1)
  67. #define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF (1 << 0)
  68. #define MIPI_CAL_BIAS_PAD_CFG1 0x17
  69. #define MIPI_CAL_BIAS_PAD_DRV_DN_REF(x) (((x) & 0x7) << 16)
  70. #define MIPI_CAL_BIAS_PAD_DRV_UP_REF(x) (((x) & 0x7) << 8)
  71. #define MIPI_CAL_BIAS_PAD_CFG2 0x18
  72. #define MIPI_CAL_BIAS_PAD_VCLAMP(x) (((x) & 0x7) << 16)
  73. #define MIPI_CAL_BIAS_PAD_VAUXP(x) (((x) & 0x7) << 4)
  74. #define MIPI_CAL_BIAS_PAD_PDVREG (1 << 1)
  75. struct tegra_mipi_pad {
  76. unsigned long data;
  77. unsigned long clk;
  78. };
  79. struct tegra_mipi_soc {
  80. bool has_clk_lane;
  81. const struct tegra_mipi_pad *pads;
  82. unsigned int num_pads;
  83. bool clock_enable_override;
  84. bool needs_vclamp_ref;
  85. /* bias pad configuration settings */
  86. u8 pad_drive_down_ref;
  87. u8 pad_drive_up_ref;
  88. u8 pad_vclamp_level;
  89. u8 pad_vauxp_level;
  90. /* calibration settings for data lanes */
  91. u8 hspdos;
  92. u8 hspuos;
  93. u8 termos;
  94. /* calibration settings for clock lanes */
  95. u8 hsclkpdos;
  96. u8 hsclkpuos;
  97. };
  98. struct tegra_mipi {
  99. const struct tegra_mipi_soc *soc;
  100. struct device *dev;
  101. void __iomem *regs;
  102. struct mutex lock;
  103. struct clk *clk;
  104. unsigned long usage_count;
  105. };
  106. struct tegra_mipi_device {
  107. struct platform_device *pdev;
  108. struct tegra_mipi *mipi;
  109. struct device *device;
  110. unsigned long pads;
  111. };
  112. static inline u32 tegra_mipi_readl(struct tegra_mipi *mipi,
  113. unsigned long offset)
  114. {
  115. return readl(mipi->regs + (offset << 2));
  116. }
  117. static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 value,
  118. unsigned long offset)
  119. {
  120. writel(value, mipi->regs + (offset << 2));
  121. }
  122. static int tegra_mipi_power_up(struct tegra_mipi *mipi)
  123. {
  124. u32 value;
  125. int err;
  126. err = clk_enable(mipi->clk);
  127. if (err < 0)
  128. return err;
  129. value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG0);
  130. value &= ~MIPI_CAL_BIAS_PAD_PDVCLAMP;
  131. if (mipi->soc->needs_vclamp_ref)
  132. value |= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
  133. tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
  134. value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG2);
  135. value &= ~MIPI_CAL_BIAS_PAD_PDVREG;
  136. tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
  137. clk_disable(mipi->clk);
  138. return 0;
  139. }
  140. static int tegra_mipi_power_down(struct tegra_mipi *mipi)
  141. {
  142. u32 value;
  143. int err;
  144. err = clk_enable(mipi->clk);
  145. if (err < 0)
  146. return err;
  147. /*
  148. * The MIPI_CAL_BIAS_PAD_PDVREG controls a voltage regulator that
  149. * supplies the DSI pads. This must be kept enabled until none of the
  150. * DSI lanes are used anymore.
  151. */
  152. value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG2);
  153. value |= MIPI_CAL_BIAS_PAD_PDVREG;
  154. tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
  155. /*
  156. * MIPI_CAL_BIAS_PAD_PDVCLAMP and MIPI_CAL_BIAS_PAD_E_VCLAMP_REF
  157. * control a regulator that supplies current to the pre-driver logic.
  158. * Powering down this regulator causes DSI to fail, so it must remain
  159. * powered on until none of the DSI lanes are used anymore.
  160. */
  161. value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG0);
  162. if (mipi->soc->needs_vclamp_ref)
  163. value &= ~MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
  164. value |= MIPI_CAL_BIAS_PAD_PDVCLAMP;
  165. tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
  166. return 0;
  167. }
  168. struct tegra_mipi_device *tegra_mipi_request(struct device *device,
  169. struct device_node *np)
  170. {
  171. struct tegra_mipi_device *dev;
  172. struct of_phandle_args args;
  173. int err;
  174. err = of_parse_phandle_with_args(np, "nvidia,mipi-calibrate",
  175. "#nvidia,mipi-calibrate-cells", 0,
  176. &args);
  177. if (err < 0)
  178. return ERR_PTR(err);
  179. dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  180. if (!dev) {
  181. err = -ENOMEM;
  182. goto out;
  183. }
  184. dev->pdev = of_find_device_by_node(args.np);
  185. if (!dev->pdev) {
  186. err = -ENODEV;
  187. goto free;
  188. }
  189. dev->mipi = platform_get_drvdata(dev->pdev);
  190. if (!dev->mipi) {
  191. err = -EPROBE_DEFER;
  192. goto put;
  193. }
  194. of_node_put(args.np);
  195. dev->pads = args.args[0];
  196. dev->device = device;
  197. return dev;
  198. put:
  199. platform_device_put(dev->pdev);
  200. free:
  201. kfree(dev);
  202. out:
  203. of_node_put(args.np);
  204. return ERR_PTR(err);
  205. }
  206. EXPORT_SYMBOL(tegra_mipi_request);
  207. void tegra_mipi_free(struct tegra_mipi_device *device)
  208. {
  209. platform_device_put(device->pdev);
  210. kfree(device);
  211. }
  212. EXPORT_SYMBOL(tegra_mipi_free);
  213. int tegra_mipi_enable(struct tegra_mipi_device *dev)
  214. {
  215. int err = 0;
  216. mutex_lock(&dev->mipi->lock);
  217. if (dev->mipi->usage_count++ == 0)
  218. err = tegra_mipi_power_up(dev->mipi);
  219. mutex_unlock(&dev->mipi->lock);
  220. return err;
  221. }
  222. EXPORT_SYMBOL(tegra_mipi_enable);
  223. int tegra_mipi_disable(struct tegra_mipi_device *dev)
  224. {
  225. int err = 0;
  226. mutex_lock(&dev->mipi->lock);
  227. if (--dev->mipi->usage_count == 0)
  228. err = tegra_mipi_power_down(dev->mipi);
  229. mutex_unlock(&dev->mipi->lock);
  230. return err;
  231. }
  232. EXPORT_SYMBOL(tegra_mipi_disable);
  233. int tegra_mipi_finish_calibration(struct tegra_mipi_device *device)
  234. {
  235. struct tegra_mipi *mipi = device->mipi;
  236. void __iomem *status_reg = mipi->regs + (MIPI_CAL_STATUS << 2);
  237. u32 value;
  238. int err;
  239. err = readl_relaxed_poll_timeout(status_reg, value,
  240. !(value & MIPI_CAL_STATUS_ACTIVE) &&
  241. (value & MIPI_CAL_STATUS_DONE), 50,
  242. 250000);
  243. mutex_unlock(&device->mipi->lock);
  244. clk_disable(device->mipi->clk);
  245. return err;
  246. }
  247. EXPORT_SYMBOL(tegra_mipi_finish_calibration);
  248. int tegra_mipi_start_calibration(struct tegra_mipi_device *device)
  249. {
  250. const struct tegra_mipi_soc *soc = device->mipi->soc;
  251. unsigned int i;
  252. u32 value;
  253. int err;
  254. err = clk_enable(device->mipi->clk);
  255. if (err < 0)
  256. return err;
  257. mutex_lock(&device->mipi->lock);
  258. value = MIPI_CAL_BIAS_PAD_DRV_DN_REF(soc->pad_drive_down_ref) |
  259. MIPI_CAL_BIAS_PAD_DRV_UP_REF(soc->pad_drive_up_ref);
  260. tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG1);
  261. value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2);
  262. value &= ~MIPI_CAL_BIAS_PAD_VCLAMP(0x7);
  263. value &= ~MIPI_CAL_BIAS_PAD_VAUXP(0x7);
  264. value |= MIPI_CAL_BIAS_PAD_VCLAMP(soc->pad_vclamp_level);
  265. value |= MIPI_CAL_BIAS_PAD_VAUXP(soc->pad_vauxp_level);
  266. tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
  267. for (i = 0; i < soc->num_pads; i++) {
  268. u32 clk = 0, data = 0;
  269. if (device->pads & BIT(i)) {
  270. data = MIPI_CAL_CONFIG_SELECT |
  271. MIPI_CAL_CONFIG_HSPDOS(soc->hspdos) |
  272. MIPI_CAL_CONFIG_HSPUOS(soc->hspuos) |
  273. MIPI_CAL_CONFIG_TERMOS(soc->termos);
  274. clk = MIPI_CAL_CONFIG_SELECT |
  275. MIPI_CAL_CONFIG_HSCLKPDOSD(soc->hsclkpdos) |
  276. MIPI_CAL_CONFIG_HSCLKPUOSD(soc->hsclkpuos);
  277. }
  278. tegra_mipi_writel(device->mipi, data, soc->pads[i].data);
  279. if (soc->has_clk_lane && soc->pads[i].clk != 0)
  280. tegra_mipi_writel(device->mipi, clk, soc->pads[i].clk);
  281. }
  282. value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
  283. value &= ~MIPI_CAL_CTRL_NOISE_FILTER(0xf);
  284. value &= ~MIPI_CAL_CTRL_PRESCALE(0x3);
  285. value |= MIPI_CAL_CTRL_NOISE_FILTER(0xa);
  286. value |= MIPI_CAL_CTRL_PRESCALE(0x2);
  287. if (!soc->clock_enable_override)
  288. value &= ~MIPI_CAL_CTRL_CLKEN_OVR;
  289. else
  290. value |= MIPI_CAL_CTRL_CLKEN_OVR;
  291. tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
  292. /* clear any pending status bits */
  293. value = tegra_mipi_readl(device->mipi, MIPI_CAL_STATUS);
  294. tegra_mipi_writel(device->mipi, value, MIPI_CAL_STATUS);
  295. value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
  296. value |= MIPI_CAL_CTRL_START;
  297. tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
  298. /*
  299. * Wait for min 72uS to let calibration logic finish calibration
  300. * sequence codes before waiting for pads idle state to apply the
  301. * results.
  302. */
  303. usleep_range(75, 80);
  304. return 0;
  305. }
  306. EXPORT_SYMBOL(tegra_mipi_start_calibration);
  307. static const struct tegra_mipi_pad tegra114_mipi_pads[] = {
  308. { .data = MIPI_CAL_CONFIG_CSIA },
  309. { .data = MIPI_CAL_CONFIG_CSIB },
  310. { .data = MIPI_CAL_CONFIG_CSIC },
  311. { .data = MIPI_CAL_CONFIG_CSID },
  312. { .data = MIPI_CAL_CONFIG_CSIE },
  313. { .data = MIPI_CAL_CONFIG_DSIA },
  314. { .data = MIPI_CAL_CONFIG_DSIB },
  315. { .data = MIPI_CAL_CONFIG_DSIC },
  316. { .data = MIPI_CAL_CONFIG_DSID },
  317. };
  318. static const struct tegra_mipi_soc tegra114_mipi_soc = {
  319. .has_clk_lane = false,
  320. .pads = tegra114_mipi_pads,
  321. .num_pads = ARRAY_SIZE(tegra114_mipi_pads),
  322. .clock_enable_override = true,
  323. .needs_vclamp_ref = true,
  324. .pad_drive_down_ref = 0x2,
  325. .pad_drive_up_ref = 0x0,
  326. .pad_vclamp_level = 0x0,
  327. .pad_vauxp_level = 0x0,
  328. .hspdos = 0x0,
  329. .hspuos = 0x4,
  330. .termos = 0x5,
  331. .hsclkpdos = 0x0,
  332. .hsclkpuos = 0x4,
  333. };
  334. static const struct tegra_mipi_pad tegra124_mipi_pads[] = {
  335. { .data = MIPI_CAL_CONFIG_CSIA, .clk = MIPI_CAL_CONFIG_CSIAB_CLK },
  336. { .data = MIPI_CAL_CONFIG_CSIB, .clk = MIPI_CAL_CONFIG_CSIAB_CLK },
  337. { .data = MIPI_CAL_CONFIG_CSIC, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
  338. { .data = MIPI_CAL_CONFIG_CSID, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
  339. { .data = MIPI_CAL_CONFIG_CSIE, .clk = MIPI_CAL_CONFIG_CSIE_CLK },
  340. { .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIA_CLK },
  341. { .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIB_CLK },
  342. };
  343. static const struct tegra_mipi_soc tegra124_mipi_soc = {
  344. .has_clk_lane = true,
  345. .pads = tegra124_mipi_pads,
  346. .num_pads = ARRAY_SIZE(tegra124_mipi_pads),
  347. .clock_enable_override = true,
  348. .needs_vclamp_ref = true,
  349. .pad_drive_down_ref = 0x2,
  350. .pad_drive_up_ref = 0x0,
  351. .pad_vclamp_level = 0x0,
  352. .pad_vauxp_level = 0x0,
  353. .hspdos = 0x0,
  354. .hspuos = 0x0,
  355. .termos = 0x0,
  356. .hsclkpdos = 0x1,
  357. .hsclkpuos = 0x2,
  358. };
  359. static const struct tegra_mipi_soc tegra132_mipi_soc = {
  360. .has_clk_lane = true,
  361. .pads = tegra124_mipi_pads,
  362. .num_pads = ARRAY_SIZE(tegra124_mipi_pads),
  363. .clock_enable_override = false,
  364. .needs_vclamp_ref = false,
  365. .pad_drive_down_ref = 0x0,
  366. .pad_drive_up_ref = 0x3,
  367. .pad_vclamp_level = 0x0,
  368. .pad_vauxp_level = 0x0,
  369. .hspdos = 0x0,
  370. .hspuos = 0x0,
  371. .termos = 0x0,
  372. .hsclkpdos = 0x3,
  373. .hsclkpuos = 0x2,
  374. };
  375. static const struct tegra_mipi_pad tegra210_mipi_pads[] = {
  376. { .data = MIPI_CAL_CONFIG_CSIA, .clk = 0 },
  377. { .data = MIPI_CAL_CONFIG_CSIB, .clk = 0 },
  378. { .data = MIPI_CAL_CONFIG_CSIC, .clk = 0 },
  379. { .data = MIPI_CAL_CONFIG_CSID, .clk = 0 },
  380. { .data = MIPI_CAL_CONFIG_CSIE, .clk = 0 },
  381. { .data = MIPI_CAL_CONFIG_CSIF, .clk = 0 },
  382. { .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIA_CLK },
  383. { .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIB_CLK },
  384. { .data = MIPI_CAL_CONFIG_DSIC, .clk = MIPI_CAL_CONFIG_DSIC_CLK },
  385. { .data = MIPI_CAL_CONFIG_DSID, .clk = MIPI_CAL_CONFIG_DSID_CLK },
  386. };
  387. static const struct tegra_mipi_soc tegra210_mipi_soc = {
  388. .has_clk_lane = true,
  389. .pads = tegra210_mipi_pads,
  390. .num_pads = ARRAY_SIZE(tegra210_mipi_pads),
  391. .clock_enable_override = true,
  392. .needs_vclamp_ref = false,
  393. .pad_drive_down_ref = 0x0,
  394. .pad_drive_up_ref = 0x3,
  395. .pad_vclamp_level = 0x1,
  396. .pad_vauxp_level = 0x1,
  397. .hspdos = 0x0,
  398. .hspuos = 0x2,
  399. .termos = 0x0,
  400. .hsclkpdos = 0x0,
  401. .hsclkpuos = 0x2,
  402. };
  403. static const struct of_device_id tegra_mipi_of_match[] = {
  404. { .compatible = "nvidia,tegra114-mipi", .data = &tegra114_mipi_soc },
  405. { .compatible = "nvidia,tegra124-mipi", .data = &tegra124_mipi_soc },
  406. { .compatible = "nvidia,tegra132-mipi", .data = &tegra132_mipi_soc },
  407. { .compatible = "nvidia,tegra210-mipi", .data = &tegra210_mipi_soc },
  408. { },
  409. };
  410. static int tegra_mipi_probe(struct platform_device *pdev)
  411. {
  412. const struct of_device_id *match;
  413. struct tegra_mipi *mipi;
  414. struct resource *res;
  415. int err;
  416. match = of_match_node(tegra_mipi_of_match, pdev->dev.of_node);
  417. if (!match)
  418. return -ENODEV;
  419. mipi = devm_kzalloc(&pdev->dev, sizeof(*mipi), GFP_KERNEL);
  420. if (!mipi)
  421. return -ENOMEM;
  422. mipi->soc = match->data;
  423. mipi->dev = &pdev->dev;
  424. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  425. mipi->regs = devm_ioremap_resource(&pdev->dev, res);
  426. if (IS_ERR(mipi->regs))
  427. return PTR_ERR(mipi->regs);
  428. mutex_init(&mipi->lock);
  429. mipi->clk = devm_clk_get(&pdev->dev, NULL);
  430. if (IS_ERR(mipi->clk)) {
  431. dev_err(&pdev->dev, "failed to get clock\n");
  432. return PTR_ERR(mipi->clk);
  433. }
  434. err = clk_prepare(mipi->clk);
  435. if (err < 0)
  436. return err;
  437. platform_set_drvdata(pdev, mipi);
  438. return 0;
  439. }
  440. static int tegra_mipi_remove(struct platform_device *pdev)
  441. {
  442. struct tegra_mipi *mipi = platform_get_drvdata(pdev);
  443. clk_unprepare(mipi->clk);
  444. return 0;
  445. }
  446. struct platform_driver tegra_mipi_driver = {
  447. .driver = {
  448. .name = "tegra-mipi",
  449. .of_match_table = tegra_mipi_of_match,
  450. },
  451. .probe = tegra_mipi_probe,
  452. .remove = tegra_mipi_remove,
  453. };