hw_host1x05_uclass.h 5.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2015 NVIDIA Corporation.
  4. */
  5. /*
  6. * Function naming determines intended use:
  7. *
  8. * <x>_r(void) : Returns the offset for register <x>.
  9. *
  10. * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
  11. *
  12. * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
  13. *
  14. * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
  15. * and masked to place it at field <y> of register <x>. This value
  16. * can be |'d with others to produce a full register value for
  17. * register <x>.
  18. *
  19. * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
  20. * value can be ~'d and then &'d to clear the value of field <y> for
  21. * register <x>.
  22. *
  23. * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
  24. * to place it at field <y> of register <x>. This value can be |'d
  25. * with others to produce a full register value for <x>.
  26. *
  27. * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
  28. * <x> value 'r' after being shifted to place its LSB at bit 0.
  29. * This value is suitable for direct comparison with other unshifted
  30. * values appropriate for use in field <y> of register <x>.
  31. *
  32. * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
  33. * field <y> of register <x>. This value is suitable for direct
  34. * comparison with unshifted values appropriate for use in field <y>
  35. * of register <x>.
  36. */
  37. #ifndef HOST1X_HW_HOST1X05_UCLASS_H
  38. #define HOST1X_HW_HOST1X05_UCLASS_H
  39. static inline u32 host1x_uclass_incr_syncpt_r(void)
  40. {
  41. return 0x0;
  42. }
  43. #define HOST1X_UCLASS_INCR_SYNCPT \
  44. host1x_uclass_incr_syncpt_r()
  45. static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
  46. {
  47. return (v & 0xff) << 8;
  48. }
  49. #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
  50. host1x_uclass_incr_syncpt_cond_f(v)
  51. static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
  52. {
  53. return (v & 0xff) << 0;
  54. }
  55. #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
  56. host1x_uclass_incr_syncpt_indx_f(v)
  57. static inline u32 host1x_uclass_wait_syncpt_r(void)
  58. {
  59. return 0x8;
  60. }
  61. #define HOST1X_UCLASS_WAIT_SYNCPT \
  62. host1x_uclass_wait_syncpt_r()
  63. static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
  64. {
  65. return (v & 0xff) << 24;
  66. }
  67. #define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
  68. host1x_uclass_wait_syncpt_indx_f(v)
  69. static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
  70. {
  71. return (v & 0xffffff) << 0;
  72. }
  73. #define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
  74. host1x_uclass_wait_syncpt_thresh_f(v)
  75. static inline u32 host1x_uclass_wait_syncpt_base_r(void)
  76. {
  77. return 0x9;
  78. }
  79. #define HOST1X_UCLASS_WAIT_SYNCPT_BASE \
  80. host1x_uclass_wait_syncpt_base_r()
  81. static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
  82. {
  83. return (v & 0xff) << 24;
  84. }
  85. #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
  86. host1x_uclass_wait_syncpt_base_indx_f(v)
  87. static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
  88. {
  89. return (v & 0xff) << 16;
  90. }
  91. #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
  92. host1x_uclass_wait_syncpt_base_base_indx_f(v)
  93. static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
  94. {
  95. return (v & 0xffff) << 0;
  96. }
  97. #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
  98. host1x_uclass_wait_syncpt_base_offset_f(v)
  99. static inline u32 host1x_uclass_load_syncpt_base_r(void)
  100. {
  101. return 0xb;
  102. }
  103. #define HOST1X_UCLASS_LOAD_SYNCPT_BASE \
  104. host1x_uclass_load_syncpt_base_r()
  105. static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
  106. {
  107. return (v & 0xff) << 24;
  108. }
  109. #define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
  110. host1x_uclass_load_syncpt_base_base_indx_f(v)
  111. static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
  112. {
  113. return (v & 0xffffff) << 0;
  114. }
  115. #define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
  116. host1x_uclass_load_syncpt_base_value_f(v)
  117. static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
  118. {
  119. return (v & 0xff) << 24;
  120. }
  121. #define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
  122. host1x_uclass_incr_syncpt_base_base_indx_f(v)
  123. static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
  124. {
  125. return (v & 0xffffff) << 0;
  126. }
  127. #define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
  128. host1x_uclass_incr_syncpt_base_offset_f(v)
  129. static inline u32 host1x_uclass_indoff_r(void)
  130. {
  131. return 0x2d;
  132. }
  133. #define HOST1X_UCLASS_INDOFF \
  134. host1x_uclass_indoff_r()
  135. static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
  136. {
  137. return (v & 0xf) << 28;
  138. }
  139. #define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
  140. host1x_uclass_indoff_indbe_f(v)
  141. static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
  142. {
  143. return (v & 0x1) << 27;
  144. }
  145. #define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
  146. host1x_uclass_indoff_autoinc_f(v)
  147. static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
  148. {
  149. return (v & 0xff) << 18;
  150. }
  151. #define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
  152. host1x_uclass_indoff_indmodid_f(v)
  153. static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
  154. {
  155. return (v & 0xffff) << 2;
  156. }
  157. #define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
  158. host1x_uclass_indoff_indroffset_f(v)
  159. static inline u32 host1x_uclass_indoff_rwn_read_v(void)
  160. {
  161. return 1;
  162. }
  163. #define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
  164. host1x_uclass_indoff_indroffset_f(v)
  165. #endif