dev.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Tegra host1x driver
  4. *
  5. * Copyright (c) 2010-2013, NVIDIA Corporation.
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/dma-mapping.h>
  9. #include <linux/io.h>
  10. #include <linux/list.h>
  11. #include <linux/module.h>
  12. #include <linux/of_device.h>
  13. #include <linux/of.h>
  14. #include <linux/slab.h>
  15. #define CREATE_TRACE_POINTS
  16. #include <trace/events/host1x.h>
  17. #undef CREATE_TRACE_POINTS
  18. #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
  19. #include <asm/dma-iommu.h>
  20. #endif
  21. #include "bus.h"
  22. #include "channel.h"
  23. #include "debug.h"
  24. #include "dev.h"
  25. #include "intr.h"
  26. #include "hw/host1x01.h"
  27. #include "hw/host1x02.h"
  28. #include "hw/host1x04.h"
  29. #include "hw/host1x05.h"
  30. #include "hw/host1x06.h"
  31. #include "hw/host1x07.h"
  32. void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
  33. {
  34. writel(v, host1x->hv_regs + r);
  35. }
  36. u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r)
  37. {
  38. return readl(host1x->hv_regs + r);
  39. }
  40. void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
  41. {
  42. void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
  43. writel(v, sync_regs + r);
  44. }
  45. u32 host1x_sync_readl(struct host1x *host1x, u32 r)
  46. {
  47. void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
  48. return readl(sync_regs + r);
  49. }
  50. void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
  51. {
  52. writel(v, ch->regs + r);
  53. }
  54. u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
  55. {
  56. return readl(ch->regs + r);
  57. }
  58. static const struct host1x_info host1x01_info = {
  59. .nb_channels = 8,
  60. .nb_pts = 32,
  61. .nb_mlocks = 16,
  62. .nb_bases = 8,
  63. .init = host1x01_init,
  64. .sync_offset = 0x3000,
  65. .dma_mask = DMA_BIT_MASK(32),
  66. .has_wide_gather = false,
  67. .has_hypervisor = false,
  68. .num_sid_entries = 0,
  69. .sid_table = NULL,
  70. };
  71. static const struct host1x_info host1x02_info = {
  72. .nb_channels = 9,
  73. .nb_pts = 32,
  74. .nb_mlocks = 16,
  75. .nb_bases = 12,
  76. .init = host1x02_init,
  77. .sync_offset = 0x3000,
  78. .dma_mask = DMA_BIT_MASK(32),
  79. .has_wide_gather = false,
  80. .has_hypervisor = false,
  81. .num_sid_entries = 0,
  82. .sid_table = NULL,
  83. };
  84. static const struct host1x_info host1x04_info = {
  85. .nb_channels = 12,
  86. .nb_pts = 192,
  87. .nb_mlocks = 16,
  88. .nb_bases = 64,
  89. .init = host1x04_init,
  90. .sync_offset = 0x2100,
  91. .dma_mask = DMA_BIT_MASK(34),
  92. .has_wide_gather = false,
  93. .has_hypervisor = false,
  94. .num_sid_entries = 0,
  95. .sid_table = NULL,
  96. };
  97. static const struct host1x_info host1x05_info = {
  98. .nb_channels = 14,
  99. .nb_pts = 192,
  100. .nb_mlocks = 16,
  101. .nb_bases = 64,
  102. .init = host1x05_init,
  103. .sync_offset = 0x2100,
  104. .dma_mask = DMA_BIT_MASK(34),
  105. .has_wide_gather = false,
  106. .has_hypervisor = false,
  107. .num_sid_entries = 0,
  108. .sid_table = NULL,
  109. };
  110. static const struct host1x_sid_entry tegra186_sid_table[] = {
  111. {
  112. /* VIC */
  113. .base = 0x1af0,
  114. .offset = 0x30,
  115. .limit = 0x34
  116. },
  117. };
  118. static const struct host1x_info host1x06_info = {
  119. .nb_channels = 63,
  120. .nb_pts = 576,
  121. .nb_mlocks = 24,
  122. .nb_bases = 16,
  123. .init = host1x06_init,
  124. .sync_offset = 0x0,
  125. .dma_mask = DMA_BIT_MASK(40),
  126. .has_wide_gather = true,
  127. .has_hypervisor = true,
  128. .num_sid_entries = ARRAY_SIZE(tegra186_sid_table),
  129. .sid_table = tegra186_sid_table,
  130. };
  131. static const struct host1x_sid_entry tegra194_sid_table[] = {
  132. {
  133. /* VIC */
  134. .base = 0x1af0,
  135. .offset = 0x30,
  136. .limit = 0x34
  137. },
  138. };
  139. static const struct host1x_info host1x07_info = {
  140. .nb_channels = 63,
  141. .nb_pts = 704,
  142. .nb_mlocks = 32,
  143. .nb_bases = 0,
  144. .init = host1x07_init,
  145. .sync_offset = 0x0,
  146. .dma_mask = DMA_BIT_MASK(40),
  147. .has_wide_gather = true,
  148. .has_hypervisor = true,
  149. .num_sid_entries = ARRAY_SIZE(tegra194_sid_table),
  150. .sid_table = tegra194_sid_table,
  151. };
  152. static const struct of_device_id host1x_of_match[] = {
  153. { .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },
  154. { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
  155. { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
  156. { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
  157. { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
  158. { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
  159. { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
  160. { },
  161. };
  162. MODULE_DEVICE_TABLE(of, host1x_of_match);
  163. static void host1x_setup_sid_table(struct host1x *host)
  164. {
  165. const struct host1x_info *info = host->info;
  166. unsigned int i;
  167. for (i = 0; i < info->num_sid_entries; i++) {
  168. const struct host1x_sid_entry *entry = &info->sid_table[i];
  169. host1x_hypervisor_writel(host, entry->offset, entry->base);
  170. host1x_hypervisor_writel(host, entry->limit, entry->base + 4);
  171. }
  172. }
  173. static bool host1x_wants_iommu(struct host1x *host1x)
  174. {
  175. /*
  176. * If we support addressing a maximum of 32 bits of physical memory
  177. * and if the host1x firewall is enabled, there's no need to enable
  178. * IOMMU support. This can happen for example on Tegra20, Tegra30
  179. * and Tegra114.
  180. *
  181. * Tegra124 and later can address up to 34 bits of physical memory and
  182. * many platforms come equipped with more than 2 GiB of system memory,
  183. * which requires crossing the 4 GiB boundary. But there's a catch: on
  184. * SoCs before Tegra186 (i.e. Tegra124 and Tegra210), the host1x can
  185. * only address up to 32 bits of memory in GATHER opcodes, which means
  186. * that command buffers need to either be in the first 2 GiB of system
  187. * memory (which could quickly lead to memory exhaustion), or command
  188. * buffers need to be treated differently from other buffers (which is
  189. * not possible with the current ABI).
  190. *
  191. * A third option is to use the IOMMU in these cases to make sure all
  192. * buffers will be mapped into a 32-bit IOVA space that host1x can
  193. * address. This allows all of the system memory to be used and works
  194. * within the limitations of the host1x on these SoCs.
  195. *
  196. * In summary, default to enable IOMMU on Tegra124 and later. For any
  197. * of the earlier SoCs, only use the IOMMU for additional safety when
  198. * the host1x firewall is disabled.
  199. */
  200. if (host1x->info->dma_mask <= DMA_BIT_MASK(32)) {
  201. if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL))
  202. return false;
  203. }
  204. return true;
  205. }
  206. static struct iommu_domain *host1x_iommu_attach(struct host1x *host)
  207. {
  208. struct iommu_domain *domain = iommu_get_domain_for_dev(host->dev);
  209. int err;
  210. #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
  211. if (host->dev->archdata.mapping) {
  212. struct dma_iommu_mapping *mapping =
  213. to_dma_iommu_mapping(host->dev);
  214. arm_iommu_detach_device(host->dev);
  215. arm_iommu_release_mapping(mapping);
  216. domain = iommu_get_domain_for_dev(host->dev);
  217. }
  218. #endif
  219. /*
  220. * We may not always want to enable IOMMU support (for example if the
  221. * host1x firewall is already enabled and we don't support addressing
  222. * more than 32 bits of physical memory), so check for that first.
  223. *
  224. * Similarly, if host1x is already attached to an IOMMU (via the DMA
  225. * API), don't try to attach again.
  226. */
  227. if (!host1x_wants_iommu(host) || domain)
  228. return domain;
  229. host->group = iommu_group_get(host->dev);
  230. if (host->group) {
  231. struct iommu_domain_geometry *geometry;
  232. dma_addr_t start, end;
  233. unsigned long order;
  234. err = iova_cache_get();
  235. if (err < 0)
  236. goto put_group;
  237. host->domain = iommu_domain_alloc(&platform_bus_type);
  238. if (!host->domain) {
  239. err = -ENOMEM;
  240. goto put_cache;
  241. }
  242. err = iommu_attach_group(host->domain, host->group);
  243. if (err) {
  244. if (err == -ENODEV)
  245. err = 0;
  246. goto free_domain;
  247. }
  248. geometry = &host->domain->geometry;
  249. start = geometry->aperture_start & host->info->dma_mask;
  250. end = geometry->aperture_end & host->info->dma_mask;
  251. order = __ffs(host->domain->pgsize_bitmap);
  252. init_iova_domain(&host->iova, 1UL << order, start >> order);
  253. host->iova_end = end;
  254. domain = host->domain;
  255. }
  256. return domain;
  257. free_domain:
  258. iommu_domain_free(host->domain);
  259. host->domain = NULL;
  260. put_cache:
  261. iova_cache_put();
  262. put_group:
  263. iommu_group_put(host->group);
  264. host->group = NULL;
  265. return ERR_PTR(err);
  266. }
  267. static int host1x_iommu_init(struct host1x *host)
  268. {
  269. u64 mask = host->info->dma_mask;
  270. struct iommu_domain *domain;
  271. int err;
  272. domain = host1x_iommu_attach(host);
  273. if (IS_ERR(domain)) {
  274. err = PTR_ERR(domain);
  275. dev_err(host->dev, "failed to attach to IOMMU: %d\n", err);
  276. return err;
  277. }
  278. /*
  279. * If we're not behind an IOMMU make sure we don't get push buffers
  280. * that are allocated outside of the range addressable by the GATHER
  281. * opcode.
  282. *
  283. * Newer generations of Tegra (Tegra186 and later) support a wide
  284. * variant of the GATHER opcode that allows addressing more bits.
  285. */
  286. if (!domain && !host->info->has_wide_gather)
  287. mask = DMA_BIT_MASK(32);
  288. err = dma_coerce_mask_and_coherent(host->dev, mask);
  289. if (err < 0) {
  290. dev_err(host->dev, "failed to set DMA mask: %d\n", err);
  291. return err;
  292. }
  293. return 0;
  294. }
  295. static void host1x_iommu_exit(struct host1x *host)
  296. {
  297. if (host->domain) {
  298. put_iova_domain(&host->iova);
  299. iommu_detach_group(host->domain, host->group);
  300. iommu_domain_free(host->domain);
  301. host->domain = NULL;
  302. iova_cache_put();
  303. iommu_group_put(host->group);
  304. host->group = NULL;
  305. }
  306. }
  307. static int host1x_probe(struct platform_device *pdev)
  308. {
  309. struct host1x *host;
  310. struct resource *regs, *hv_regs = NULL;
  311. int syncpt_irq;
  312. int err;
  313. host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
  314. if (!host)
  315. return -ENOMEM;
  316. host->info = of_device_get_match_data(&pdev->dev);
  317. if (host->info->has_hypervisor) {
  318. regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm");
  319. if (!regs) {
  320. dev_err(&pdev->dev, "failed to get vm registers\n");
  321. return -ENXIO;
  322. }
  323. hv_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  324. "hypervisor");
  325. if (!hv_regs) {
  326. dev_err(&pdev->dev,
  327. "failed to get hypervisor registers\n");
  328. return -ENXIO;
  329. }
  330. } else {
  331. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  332. if (!regs) {
  333. dev_err(&pdev->dev, "failed to get registers\n");
  334. return -ENXIO;
  335. }
  336. }
  337. syncpt_irq = platform_get_irq(pdev, 0);
  338. if (syncpt_irq < 0)
  339. return syncpt_irq;
  340. mutex_init(&host->devices_lock);
  341. INIT_LIST_HEAD(&host->devices);
  342. INIT_LIST_HEAD(&host->list);
  343. host->dev = &pdev->dev;
  344. /* set common host1x device data */
  345. platform_set_drvdata(pdev, host);
  346. host->regs = devm_ioremap_resource(&pdev->dev, regs);
  347. if (IS_ERR(host->regs))
  348. return PTR_ERR(host->regs);
  349. if (host->info->has_hypervisor) {
  350. host->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs);
  351. if (IS_ERR(host->hv_regs))
  352. return PTR_ERR(host->hv_regs);
  353. }
  354. host->dev->dma_parms = &host->dma_parms;
  355. dma_set_max_seg_size(host->dev, UINT_MAX);
  356. if (host->info->init) {
  357. err = host->info->init(host);
  358. if (err)
  359. return err;
  360. }
  361. host->clk = devm_clk_get(&pdev->dev, NULL);
  362. if (IS_ERR(host->clk)) {
  363. err = PTR_ERR(host->clk);
  364. if (err != -EPROBE_DEFER)
  365. dev_err(&pdev->dev, "failed to get clock: %d\n", err);
  366. return err;
  367. }
  368. host->rst = devm_reset_control_get(&pdev->dev, "host1x");
  369. if (IS_ERR(host->rst)) {
  370. err = PTR_ERR(host->rst);
  371. dev_err(&pdev->dev, "failed to get reset: %d\n", err);
  372. return err;
  373. }
  374. err = host1x_iommu_init(host);
  375. if (err < 0) {
  376. dev_err(&pdev->dev, "failed to setup IOMMU: %d\n", err);
  377. return err;
  378. }
  379. err = host1x_channel_list_init(&host->channel_list,
  380. host->info->nb_channels);
  381. if (err) {
  382. dev_err(&pdev->dev, "failed to initialize channel list\n");
  383. goto iommu_exit;
  384. }
  385. err = clk_prepare_enable(host->clk);
  386. if (err < 0) {
  387. dev_err(&pdev->dev, "failed to enable clock\n");
  388. goto free_channels;
  389. }
  390. err = reset_control_deassert(host->rst);
  391. if (err < 0) {
  392. dev_err(&pdev->dev, "failed to deassert reset: %d\n", err);
  393. goto unprepare_disable;
  394. }
  395. err = host1x_syncpt_init(host);
  396. if (err) {
  397. dev_err(&pdev->dev, "failed to initialize syncpts\n");
  398. goto reset_assert;
  399. }
  400. err = host1x_intr_init(host, syncpt_irq);
  401. if (err) {
  402. dev_err(&pdev->dev, "failed to initialize interrupts\n");
  403. goto deinit_syncpt;
  404. }
  405. host1x_debug_init(host);
  406. if (host->info->has_hypervisor)
  407. host1x_setup_sid_table(host);
  408. err = host1x_register(host);
  409. if (err < 0)
  410. goto deinit_debugfs;
  411. err = devm_of_platform_populate(&pdev->dev);
  412. if (err < 0)
  413. goto unregister;
  414. return 0;
  415. unregister:
  416. host1x_unregister(host);
  417. deinit_debugfs:
  418. host1x_debug_deinit(host);
  419. host1x_intr_deinit(host);
  420. deinit_syncpt:
  421. host1x_syncpt_deinit(host);
  422. reset_assert:
  423. reset_control_assert(host->rst);
  424. unprepare_disable:
  425. clk_disable_unprepare(host->clk);
  426. free_channels:
  427. host1x_channel_list_free(&host->channel_list);
  428. iommu_exit:
  429. host1x_iommu_exit(host);
  430. return err;
  431. }
  432. static int host1x_remove(struct platform_device *pdev)
  433. {
  434. struct host1x *host = platform_get_drvdata(pdev);
  435. host1x_unregister(host);
  436. host1x_debug_deinit(host);
  437. host1x_intr_deinit(host);
  438. host1x_syncpt_deinit(host);
  439. reset_control_assert(host->rst);
  440. clk_disable_unprepare(host->clk);
  441. host1x_channel_list_free(&host->channel_list);
  442. host1x_iommu_exit(host);
  443. return 0;
  444. }
  445. static struct platform_driver tegra_host1x_driver = {
  446. .driver = {
  447. .name = "tegra-host1x",
  448. .of_match_table = host1x_of_match,
  449. },
  450. .probe = host1x_probe,
  451. .remove = host1x_remove,
  452. };
  453. static struct platform_driver * const drivers[] = {
  454. &tegra_host1x_driver,
  455. &tegra_mipi_driver,
  456. };
  457. static int __init tegra_host1x_init(void)
  458. {
  459. int err;
  460. err = bus_register(&host1x_bus_type);
  461. if (err < 0)
  462. return err;
  463. err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
  464. if (err < 0)
  465. bus_unregister(&host1x_bus_type);
  466. return err;
  467. }
  468. module_init(tegra_host1x_init);
  469. static void __exit tegra_host1x_exit(void)
  470. {
  471. platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
  472. bus_unregister(&host1x_bus_type);
  473. }
  474. module_exit(tegra_host1x_exit);
  475. /**
  476. * host1x_get_dma_mask() - query the supported DMA mask for host1x
  477. * @host1x: host1x instance
  478. *
  479. * Note that this returns the supported DMA mask for host1x, which can be
  480. * different from the applicable DMA mask under certain circumstances.
  481. */
  482. u64 host1x_get_dma_mask(struct host1x *host1x)
  483. {
  484. return host1x->info->dma_mask;
  485. }
  486. EXPORT_SYMBOL(host1x_get_dma_mask);
  487. MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
  488. MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
  489. MODULE_DESCRIPTION("Host1x driver for Tegra products");
  490. MODULE_LICENSE("GPL");