vmwgfx_irq.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR MIT
  2. /**************************************************************************
  3. *
  4. * Copyright 2009-2015 VMware, Inc., Palo Alto, CA., USA
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. **************************************************************************/
  27. #include <linux/sched/signal.h>
  28. #include "vmwgfx_drv.h"
  29. #define VMW_FENCE_WRAP (1 << 24)
  30. /**
  31. * vmw_thread_fn - Deferred (process context) irq handler
  32. *
  33. * @irq: irq number
  34. * @arg: Closure argument. Pointer to a struct drm_device cast to void *
  35. *
  36. * This function implements the deferred part of irq processing.
  37. * The function is guaranteed to run at least once after the
  38. * vmw_irq_handler has returned with IRQ_WAKE_THREAD.
  39. *
  40. */
  41. static irqreturn_t vmw_thread_fn(int irq, void *arg)
  42. {
  43. struct drm_device *dev = (struct drm_device *)arg;
  44. struct vmw_private *dev_priv = vmw_priv(dev);
  45. irqreturn_t ret = IRQ_NONE;
  46. if (test_and_clear_bit(VMW_IRQTHREAD_FENCE,
  47. dev_priv->irqthread_pending)) {
  48. vmw_fences_update(dev_priv->fman);
  49. wake_up_all(&dev_priv->fence_queue);
  50. ret = IRQ_HANDLED;
  51. }
  52. if (test_and_clear_bit(VMW_IRQTHREAD_CMDBUF,
  53. dev_priv->irqthread_pending)) {
  54. vmw_cmdbuf_irqthread(dev_priv->cman);
  55. ret = IRQ_HANDLED;
  56. }
  57. return ret;
  58. }
  59. /**
  60. * vmw_irq_handler irq handler
  61. *
  62. * @irq: irq number
  63. * @arg: Closure argument. Pointer to a struct drm_device cast to void *
  64. *
  65. * This function implements the quick part of irq processing.
  66. * The function performs fast actions like clearing the device interrupt
  67. * flags and also reasonably quick actions like waking processes waiting for
  68. * FIFO space. Other IRQ actions are deferred to the IRQ thread.
  69. */
  70. static irqreturn_t vmw_irq_handler(int irq, void *arg)
  71. {
  72. struct drm_device *dev = (struct drm_device *)arg;
  73. struct vmw_private *dev_priv = vmw_priv(dev);
  74. uint32_t status, masked_status;
  75. irqreturn_t ret = IRQ_HANDLED;
  76. status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  77. masked_status = status & READ_ONCE(dev_priv->irq_mask);
  78. if (likely(status))
  79. outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  80. if (!status)
  81. return IRQ_NONE;
  82. if (masked_status & SVGA_IRQFLAG_FIFO_PROGRESS)
  83. wake_up_all(&dev_priv->fifo_queue);
  84. if ((masked_status & (SVGA_IRQFLAG_ANY_FENCE |
  85. SVGA_IRQFLAG_FENCE_GOAL)) &&
  86. !test_and_set_bit(VMW_IRQTHREAD_FENCE, dev_priv->irqthread_pending))
  87. ret = IRQ_WAKE_THREAD;
  88. if ((masked_status & (SVGA_IRQFLAG_COMMAND_BUFFER |
  89. SVGA_IRQFLAG_ERROR)) &&
  90. !test_and_set_bit(VMW_IRQTHREAD_CMDBUF,
  91. dev_priv->irqthread_pending))
  92. ret = IRQ_WAKE_THREAD;
  93. return ret;
  94. }
  95. static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno)
  96. {
  97. return (vmw_read(dev_priv, SVGA_REG_BUSY) == 0);
  98. }
  99. void vmw_update_seqno(struct vmw_private *dev_priv,
  100. struct vmw_fifo_state *fifo_state)
  101. {
  102. u32 *fifo_mem = dev_priv->mmio_virt;
  103. uint32_t seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE);
  104. if (dev_priv->last_read_seqno != seqno) {
  105. dev_priv->last_read_seqno = seqno;
  106. vmw_marker_pull(&fifo_state->marker_queue, seqno);
  107. vmw_fences_update(dev_priv->fman);
  108. }
  109. }
  110. bool vmw_seqno_passed(struct vmw_private *dev_priv,
  111. uint32_t seqno)
  112. {
  113. struct vmw_fifo_state *fifo_state;
  114. bool ret;
  115. if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
  116. return true;
  117. fifo_state = &dev_priv->fifo;
  118. vmw_update_seqno(dev_priv, fifo_state);
  119. if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
  120. return true;
  121. if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE) &&
  122. vmw_fifo_idle(dev_priv, seqno))
  123. return true;
  124. /**
  125. * Then check if the seqno is higher than what we've actually
  126. * emitted. Then the fence is stale and signaled.
  127. */
  128. ret = ((atomic_read(&dev_priv->marker_seq) - seqno)
  129. > VMW_FENCE_WRAP);
  130. return ret;
  131. }
  132. int vmw_fallback_wait(struct vmw_private *dev_priv,
  133. bool lazy,
  134. bool fifo_idle,
  135. uint32_t seqno,
  136. bool interruptible,
  137. unsigned long timeout)
  138. {
  139. struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
  140. uint32_t count = 0;
  141. uint32_t signal_seq;
  142. int ret;
  143. unsigned long end_jiffies = jiffies + timeout;
  144. bool (*wait_condition)(struct vmw_private *, uint32_t);
  145. DEFINE_WAIT(__wait);
  146. wait_condition = (fifo_idle) ? &vmw_fifo_idle :
  147. &vmw_seqno_passed;
  148. /**
  149. * Block command submission while waiting for idle.
  150. */
  151. if (fifo_idle) {
  152. down_read(&fifo_state->rwsem);
  153. if (dev_priv->cman) {
  154. ret = vmw_cmdbuf_idle(dev_priv->cman, interruptible,
  155. 10*HZ);
  156. if (ret)
  157. goto out_err;
  158. }
  159. }
  160. signal_seq = atomic_read(&dev_priv->marker_seq);
  161. ret = 0;
  162. for (;;) {
  163. prepare_to_wait(&dev_priv->fence_queue, &__wait,
  164. (interruptible) ?
  165. TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
  166. if (wait_condition(dev_priv, seqno))
  167. break;
  168. if (time_after_eq(jiffies, end_jiffies)) {
  169. DRM_ERROR("SVGA device lockup.\n");
  170. break;
  171. }
  172. if (lazy)
  173. schedule_timeout(1);
  174. else if ((++count & 0x0F) == 0) {
  175. /**
  176. * FIXME: Use schedule_hr_timeout here for
  177. * newer kernels and lower CPU utilization.
  178. */
  179. __set_current_state(TASK_RUNNING);
  180. schedule();
  181. __set_current_state((interruptible) ?
  182. TASK_INTERRUPTIBLE :
  183. TASK_UNINTERRUPTIBLE);
  184. }
  185. if (interruptible && signal_pending(current)) {
  186. ret = -ERESTARTSYS;
  187. break;
  188. }
  189. }
  190. finish_wait(&dev_priv->fence_queue, &__wait);
  191. if (ret == 0 && fifo_idle) {
  192. u32 *fifo_mem = dev_priv->mmio_virt;
  193. vmw_mmio_write(signal_seq, fifo_mem + SVGA_FIFO_FENCE);
  194. }
  195. wake_up_all(&dev_priv->fence_queue);
  196. out_err:
  197. if (fifo_idle)
  198. up_read(&fifo_state->rwsem);
  199. return ret;
  200. }
  201. void vmw_generic_waiter_add(struct vmw_private *dev_priv,
  202. u32 flag, int *waiter_count)
  203. {
  204. spin_lock_bh(&dev_priv->waiter_lock);
  205. if ((*waiter_count)++ == 0) {
  206. outl(flag, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  207. dev_priv->irq_mask |= flag;
  208. vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
  209. }
  210. spin_unlock_bh(&dev_priv->waiter_lock);
  211. }
  212. void vmw_generic_waiter_remove(struct vmw_private *dev_priv,
  213. u32 flag, int *waiter_count)
  214. {
  215. spin_lock_bh(&dev_priv->waiter_lock);
  216. if (--(*waiter_count) == 0) {
  217. dev_priv->irq_mask &= ~flag;
  218. vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
  219. }
  220. spin_unlock_bh(&dev_priv->waiter_lock);
  221. }
  222. void vmw_seqno_waiter_add(struct vmw_private *dev_priv)
  223. {
  224. vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_ANY_FENCE,
  225. &dev_priv->fence_queue_waiters);
  226. }
  227. void vmw_seqno_waiter_remove(struct vmw_private *dev_priv)
  228. {
  229. vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_ANY_FENCE,
  230. &dev_priv->fence_queue_waiters);
  231. }
  232. void vmw_goal_waiter_add(struct vmw_private *dev_priv)
  233. {
  234. vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FENCE_GOAL,
  235. &dev_priv->goal_queue_waiters);
  236. }
  237. void vmw_goal_waiter_remove(struct vmw_private *dev_priv)
  238. {
  239. vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FENCE_GOAL,
  240. &dev_priv->goal_queue_waiters);
  241. }
  242. int vmw_wait_seqno(struct vmw_private *dev_priv,
  243. bool lazy, uint32_t seqno,
  244. bool interruptible, unsigned long timeout)
  245. {
  246. long ret;
  247. struct vmw_fifo_state *fifo = &dev_priv->fifo;
  248. if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
  249. return 0;
  250. if (likely(vmw_seqno_passed(dev_priv, seqno)))
  251. return 0;
  252. vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
  253. if (!(fifo->capabilities & SVGA_FIFO_CAP_FENCE))
  254. return vmw_fallback_wait(dev_priv, lazy, true, seqno,
  255. interruptible, timeout);
  256. if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
  257. return vmw_fallback_wait(dev_priv, lazy, false, seqno,
  258. interruptible, timeout);
  259. vmw_seqno_waiter_add(dev_priv);
  260. if (interruptible)
  261. ret = wait_event_interruptible_timeout
  262. (dev_priv->fence_queue,
  263. vmw_seqno_passed(dev_priv, seqno),
  264. timeout);
  265. else
  266. ret = wait_event_timeout
  267. (dev_priv->fence_queue,
  268. vmw_seqno_passed(dev_priv, seqno),
  269. timeout);
  270. vmw_seqno_waiter_remove(dev_priv);
  271. if (unlikely(ret == 0))
  272. ret = -EBUSY;
  273. else if (likely(ret > 0))
  274. ret = 0;
  275. return ret;
  276. }
  277. static void vmw_irq_preinstall(struct drm_device *dev)
  278. {
  279. struct vmw_private *dev_priv = vmw_priv(dev);
  280. uint32_t status;
  281. status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  282. outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  283. }
  284. void vmw_irq_uninstall(struct drm_device *dev)
  285. {
  286. struct vmw_private *dev_priv = vmw_priv(dev);
  287. uint32_t status;
  288. if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
  289. return;
  290. if (!dev->irq_enabled)
  291. return;
  292. vmw_write(dev_priv, SVGA_REG_IRQMASK, 0);
  293. status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  294. outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  295. dev->irq_enabled = false;
  296. free_irq(dev->irq, dev);
  297. }
  298. /**
  299. * vmw_irq_install - Install the irq handlers
  300. *
  301. * @dev: Pointer to the drm device.
  302. * @irq: The irq number.
  303. * Return: Zero if successful. Negative number otherwise.
  304. */
  305. int vmw_irq_install(struct drm_device *dev, int irq)
  306. {
  307. int ret;
  308. if (dev->irq_enabled)
  309. return -EBUSY;
  310. vmw_irq_preinstall(dev);
  311. ret = request_threaded_irq(irq, vmw_irq_handler, vmw_thread_fn,
  312. IRQF_SHARED, VMWGFX_DRIVER_NAME, dev);
  313. if (ret < 0)
  314. return ret;
  315. dev->irq_enabled = true;
  316. dev->irq = irq;
  317. return ret;
  318. }