vmwgfx_drv.c 45 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR MIT
  2. /**************************************************************************
  3. *
  4. * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. **************************************************************************/
  27. #include <linux/console.h>
  28. #include <linux/dma-mapping.h>
  29. #include <linux/module.h>
  30. #include <linux/pci.h>
  31. #include <linux/mem_encrypt.h>
  32. #include <drm/drm_drv.h>
  33. #include <drm/drm_ioctl.h>
  34. #include <drm/drm_sysfs.h>
  35. #include <drm/ttm/ttm_bo_driver.h>
  36. #include <drm/ttm/ttm_module.h>
  37. #include <drm/ttm/ttm_placement.h>
  38. #include "ttm_object.h"
  39. #include "vmwgfx_binding.h"
  40. #include "vmwgfx_drv.h"
  41. #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
  42. #define VMWGFX_CHIP_SVGAII 0
  43. #define VMW_FB_RESERVATION 0
  44. #define VMW_MIN_INITIAL_WIDTH 800
  45. #define VMW_MIN_INITIAL_HEIGHT 600
  46. #ifndef VMWGFX_GIT_VERSION
  47. #define VMWGFX_GIT_VERSION "Unknown"
  48. #endif
  49. #define VMWGFX_REPO "In Tree"
  50. #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE)
  51. /**
  52. * Fully encoded drm commands. Might move to vmw_drm.h
  53. */
  54. #define DRM_IOCTL_VMW_GET_PARAM \
  55. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
  56. struct drm_vmw_getparam_arg)
  57. #define DRM_IOCTL_VMW_ALLOC_DMABUF \
  58. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
  59. union drm_vmw_alloc_dmabuf_arg)
  60. #define DRM_IOCTL_VMW_UNREF_DMABUF \
  61. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
  62. struct drm_vmw_unref_dmabuf_arg)
  63. #define DRM_IOCTL_VMW_CURSOR_BYPASS \
  64. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
  65. struct drm_vmw_cursor_bypass_arg)
  66. #define DRM_IOCTL_VMW_CONTROL_STREAM \
  67. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
  68. struct drm_vmw_control_stream_arg)
  69. #define DRM_IOCTL_VMW_CLAIM_STREAM \
  70. DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
  71. struct drm_vmw_stream_arg)
  72. #define DRM_IOCTL_VMW_UNREF_STREAM \
  73. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
  74. struct drm_vmw_stream_arg)
  75. #define DRM_IOCTL_VMW_CREATE_CONTEXT \
  76. DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
  77. struct drm_vmw_context_arg)
  78. #define DRM_IOCTL_VMW_UNREF_CONTEXT \
  79. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
  80. struct drm_vmw_context_arg)
  81. #define DRM_IOCTL_VMW_CREATE_SURFACE \
  82. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
  83. union drm_vmw_surface_create_arg)
  84. #define DRM_IOCTL_VMW_UNREF_SURFACE \
  85. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
  86. struct drm_vmw_surface_arg)
  87. #define DRM_IOCTL_VMW_REF_SURFACE \
  88. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
  89. union drm_vmw_surface_reference_arg)
  90. #define DRM_IOCTL_VMW_EXECBUF \
  91. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
  92. struct drm_vmw_execbuf_arg)
  93. #define DRM_IOCTL_VMW_GET_3D_CAP \
  94. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
  95. struct drm_vmw_get_3d_cap_arg)
  96. #define DRM_IOCTL_VMW_FENCE_WAIT \
  97. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
  98. struct drm_vmw_fence_wait_arg)
  99. #define DRM_IOCTL_VMW_FENCE_SIGNALED \
  100. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
  101. struct drm_vmw_fence_signaled_arg)
  102. #define DRM_IOCTL_VMW_FENCE_UNREF \
  103. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
  104. struct drm_vmw_fence_arg)
  105. #define DRM_IOCTL_VMW_FENCE_EVENT \
  106. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
  107. struct drm_vmw_fence_event_arg)
  108. #define DRM_IOCTL_VMW_PRESENT \
  109. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
  110. struct drm_vmw_present_arg)
  111. #define DRM_IOCTL_VMW_PRESENT_READBACK \
  112. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
  113. struct drm_vmw_present_readback_arg)
  114. #define DRM_IOCTL_VMW_UPDATE_LAYOUT \
  115. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
  116. struct drm_vmw_update_layout_arg)
  117. #define DRM_IOCTL_VMW_CREATE_SHADER \
  118. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
  119. struct drm_vmw_shader_create_arg)
  120. #define DRM_IOCTL_VMW_UNREF_SHADER \
  121. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
  122. struct drm_vmw_shader_arg)
  123. #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
  124. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
  125. union drm_vmw_gb_surface_create_arg)
  126. #define DRM_IOCTL_VMW_GB_SURFACE_REF \
  127. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
  128. union drm_vmw_gb_surface_reference_arg)
  129. #define DRM_IOCTL_VMW_SYNCCPU \
  130. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
  131. struct drm_vmw_synccpu_arg)
  132. #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \
  133. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \
  134. struct drm_vmw_context_arg)
  135. #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \
  136. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \
  137. union drm_vmw_gb_surface_create_ext_arg)
  138. #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \
  139. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \
  140. union drm_vmw_gb_surface_reference_ext_arg)
  141. #define DRM_IOCTL_VMW_MSG \
  142. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \
  143. struct drm_vmw_msg_arg)
  144. /**
  145. * The core DRM version of this macro doesn't account for
  146. * DRM_COMMAND_BASE.
  147. */
  148. #define VMW_IOCTL_DEF(ioctl, func, flags) \
  149. [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
  150. /**
  151. * Ioctl definitions.
  152. */
  153. static const struct drm_ioctl_desc vmw_ioctls[] = {
  154. VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
  155. DRM_RENDER_ALLOW),
  156. VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl,
  157. DRM_RENDER_ALLOW),
  158. VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl,
  159. DRM_RENDER_ALLOW),
  160. VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
  161. vmw_kms_cursor_bypass_ioctl,
  162. DRM_MASTER),
  163. VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
  164. DRM_MASTER),
  165. VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
  166. DRM_MASTER),
  167. VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
  168. DRM_MASTER),
  169. VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
  170. DRM_RENDER_ALLOW),
  171. VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
  172. DRM_RENDER_ALLOW),
  173. VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
  174. DRM_RENDER_ALLOW),
  175. VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
  176. DRM_RENDER_ALLOW),
  177. VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
  178. DRM_RENDER_ALLOW),
  179. VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
  180. DRM_RENDER_ALLOW),
  181. VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
  182. DRM_RENDER_ALLOW),
  183. VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
  184. vmw_fence_obj_signaled_ioctl,
  185. DRM_RENDER_ALLOW),
  186. VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
  187. DRM_RENDER_ALLOW),
  188. VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
  189. DRM_RENDER_ALLOW),
  190. VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
  191. DRM_RENDER_ALLOW),
  192. /* these allow direct access to the framebuffers mark as master only */
  193. VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
  194. DRM_MASTER | DRM_AUTH),
  195. VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
  196. vmw_present_readback_ioctl,
  197. DRM_MASTER | DRM_AUTH),
  198. /*
  199. * The permissions of the below ioctl are overridden in
  200. * vmw_generic_ioctl(). We require either
  201. * DRM_MASTER or capable(CAP_SYS_ADMIN).
  202. */
  203. VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
  204. vmw_kms_update_layout_ioctl,
  205. DRM_RENDER_ALLOW),
  206. VMW_IOCTL_DEF(VMW_CREATE_SHADER,
  207. vmw_shader_define_ioctl,
  208. DRM_RENDER_ALLOW),
  209. VMW_IOCTL_DEF(VMW_UNREF_SHADER,
  210. vmw_shader_destroy_ioctl,
  211. DRM_RENDER_ALLOW),
  212. VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
  213. vmw_gb_surface_define_ioctl,
  214. DRM_RENDER_ALLOW),
  215. VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
  216. vmw_gb_surface_reference_ioctl,
  217. DRM_RENDER_ALLOW),
  218. VMW_IOCTL_DEF(VMW_SYNCCPU,
  219. vmw_user_bo_synccpu_ioctl,
  220. DRM_RENDER_ALLOW),
  221. VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT,
  222. vmw_extended_context_define_ioctl,
  223. DRM_RENDER_ALLOW),
  224. VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT,
  225. vmw_gb_surface_define_ext_ioctl,
  226. DRM_RENDER_ALLOW),
  227. VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT,
  228. vmw_gb_surface_reference_ext_ioctl,
  229. DRM_RENDER_ALLOW),
  230. VMW_IOCTL_DEF(VMW_MSG,
  231. vmw_msg_ioctl,
  232. DRM_RENDER_ALLOW),
  233. };
  234. static const struct pci_device_id vmw_pci_id_list[] = {
  235. {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
  236. {0, 0, 0}
  237. };
  238. MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
  239. static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
  240. static int vmw_force_iommu;
  241. static int vmw_restrict_iommu;
  242. static int vmw_force_coherent;
  243. static int vmw_restrict_dma_mask;
  244. static int vmw_assume_16bpp;
  245. static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
  246. static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
  247. void *ptr);
  248. MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
  249. module_param_named(enable_fbdev, enable_fbdev, int, 0600);
  250. MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
  251. module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
  252. MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
  253. module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
  254. MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
  255. module_param_named(force_coherent, vmw_force_coherent, int, 0600);
  256. MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
  257. module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
  258. MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
  259. module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);
  260. static void vmw_print_capabilities2(uint32_t capabilities2)
  261. {
  262. DRM_INFO("Capabilities2:\n");
  263. if (capabilities2 & SVGA_CAP2_GROW_OTABLE)
  264. DRM_INFO(" Grow oTable.\n");
  265. if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY)
  266. DRM_INFO(" IntraSurface copy.\n");
  267. if (capabilities2 & SVGA_CAP2_DX3)
  268. DRM_INFO(" DX3.\n");
  269. }
  270. static void vmw_print_capabilities(uint32_t capabilities)
  271. {
  272. DRM_INFO("Capabilities:\n");
  273. if (capabilities & SVGA_CAP_RECT_COPY)
  274. DRM_INFO(" Rect copy.\n");
  275. if (capabilities & SVGA_CAP_CURSOR)
  276. DRM_INFO(" Cursor.\n");
  277. if (capabilities & SVGA_CAP_CURSOR_BYPASS)
  278. DRM_INFO(" Cursor bypass.\n");
  279. if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
  280. DRM_INFO(" Cursor bypass 2.\n");
  281. if (capabilities & SVGA_CAP_8BIT_EMULATION)
  282. DRM_INFO(" 8bit emulation.\n");
  283. if (capabilities & SVGA_CAP_ALPHA_CURSOR)
  284. DRM_INFO(" Alpha cursor.\n");
  285. if (capabilities & SVGA_CAP_3D)
  286. DRM_INFO(" 3D.\n");
  287. if (capabilities & SVGA_CAP_EXTENDED_FIFO)
  288. DRM_INFO(" Extended Fifo.\n");
  289. if (capabilities & SVGA_CAP_MULTIMON)
  290. DRM_INFO(" Multimon.\n");
  291. if (capabilities & SVGA_CAP_PITCHLOCK)
  292. DRM_INFO(" Pitchlock.\n");
  293. if (capabilities & SVGA_CAP_IRQMASK)
  294. DRM_INFO(" Irq mask.\n");
  295. if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
  296. DRM_INFO(" Display Topology.\n");
  297. if (capabilities & SVGA_CAP_GMR)
  298. DRM_INFO(" GMR.\n");
  299. if (capabilities & SVGA_CAP_TRACES)
  300. DRM_INFO(" Traces.\n");
  301. if (capabilities & SVGA_CAP_GMR2)
  302. DRM_INFO(" GMR2.\n");
  303. if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
  304. DRM_INFO(" Screen Object 2.\n");
  305. if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
  306. DRM_INFO(" Command Buffers.\n");
  307. if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
  308. DRM_INFO(" Command Buffers 2.\n");
  309. if (capabilities & SVGA_CAP_GBOBJECTS)
  310. DRM_INFO(" Guest Backed Resources.\n");
  311. if (capabilities & SVGA_CAP_DX)
  312. DRM_INFO(" DX Features.\n");
  313. if (capabilities & SVGA_CAP_HP_CMD_QUEUE)
  314. DRM_INFO(" HP Command Queue.\n");
  315. }
  316. /**
  317. * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
  318. *
  319. * @dev_priv: A device private structure.
  320. *
  321. * This function creates a small buffer object that holds the query
  322. * result for dummy queries emitted as query barriers.
  323. * The function will then map the first page and initialize a pending
  324. * occlusion query result structure, Finally it will unmap the buffer.
  325. * No interruptible waits are done within this function.
  326. *
  327. * Returns an error if bo creation or initialization fails.
  328. */
  329. static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
  330. {
  331. int ret;
  332. struct vmw_buffer_object *vbo;
  333. struct ttm_bo_kmap_obj map;
  334. volatile SVGA3dQueryResult *result;
  335. bool dummy;
  336. /*
  337. * Create the vbo as pinned, so that a tryreserve will
  338. * immediately succeed. This is because we're the only
  339. * user of the bo currently.
  340. */
  341. vbo = kzalloc(sizeof(*vbo), GFP_KERNEL);
  342. if (!vbo)
  343. return -ENOMEM;
  344. ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE,
  345. &vmw_sys_ne_placement, false,
  346. &vmw_bo_bo_free);
  347. if (unlikely(ret != 0))
  348. return ret;
  349. ret = ttm_bo_reserve(&vbo->base, false, true, NULL);
  350. BUG_ON(ret != 0);
  351. vmw_bo_pin_reserved(vbo, true);
  352. ret = ttm_bo_kmap(&vbo->base, 0, 1, &map);
  353. if (likely(ret == 0)) {
  354. result = ttm_kmap_obj_virtual(&map, &dummy);
  355. result->totalSize = sizeof(*result);
  356. result->state = SVGA3D_QUERYSTATE_PENDING;
  357. result->result32 = 0xff;
  358. ttm_bo_kunmap(&map);
  359. }
  360. vmw_bo_pin_reserved(vbo, false);
  361. ttm_bo_unreserve(&vbo->base);
  362. if (unlikely(ret != 0)) {
  363. DRM_ERROR("Dummy query buffer map failed.\n");
  364. vmw_bo_unreference(&vbo);
  365. } else
  366. dev_priv->dummy_query_bo = vbo;
  367. return ret;
  368. }
  369. /**
  370. * vmw_request_device_late - Perform late device setup
  371. *
  372. * @dev_priv: Pointer to device private.
  373. *
  374. * This function performs setup of otables and enables large command
  375. * buffer submission. These tasks are split out to a separate function
  376. * because it reverts vmw_release_device_early and is intended to be used
  377. * by an error path in the hibernation code.
  378. */
  379. static int vmw_request_device_late(struct vmw_private *dev_priv)
  380. {
  381. int ret;
  382. if (dev_priv->has_mob) {
  383. ret = vmw_otables_setup(dev_priv);
  384. if (unlikely(ret != 0)) {
  385. DRM_ERROR("Unable to initialize "
  386. "guest Memory OBjects.\n");
  387. return ret;
  388. }
  389. }
  390. if (dev_priv->cman) {
  391. ret = vmw_cmdbuf_set_pool_size(dev_priv->cman,
  392. 256*4096, 2*4096);
  393. if (ret) {
  394. struct vmw_cmdbuf_man *man = dev_priv->cman;
  395. dev_priv->cman = NULL;
  396. vmw_cmdbuf_man_destroy(man);
  397. }
  398. }
  399. return 0;
  400. }
  401. static int vmw_request_device(struct vmw_private *dev_priv)
  402. {
  403. int ret;
  404. ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
  405. if (unlikely(ret != 0)) {
  406. DRM_ERROR("Unable to initialize FIFO.\n");
  407. return ret;
  408. }
  409. vmw_fence_fifo_up(dev_priv->fman);
  410. dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
  411. if (IS_ERR(dev_priv->cman)) {
  412. dev_priv->cman = NULL;
  413. dev_priv->sm_type = VMW_SM_LEGACY;
  414. }
  415. ret = vmw_request_device_late(dev_priv);
  416. if (ret)
  417. goto out_no_mob;
  418. ret = vmw_dummy_query_bo_create(dev_priv);
  419. if (unlikely(ret != 0))
  420. goto out_no_query_bo;
  421. return 0;
  422. out_no_query_bo:
  423. if (dev_priv->cman)
  424. vmw_cmdbuf_remove_pool(dev_priv->cman);
  425. if (dev_priv->has_mob) {
  426. (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
  427. vmw_otables_takedown(dev_priv);
  428. }
  429. if (dev_priv->cman)
  430. vmw_cmdbuf_man_destroy(dev_priv->cman);
  431. out_no_mob:
  432. vmw_fence_fifo_down(dev_priv->fman);
  433. vmw_fifo_release(dev_priv, &dev_priv->fifo);
  434. return ret;
  435. }
  436. /**
  437. * vmw_release_device_early - Early part of fifo takedown.
  438. *
  439. * @dev_priv: Pointer to device private struct.
  440. *
  441. * This is the first part of command submission takedown, to be called before
  442. * buffer management is taken down.
  443. */
  444. static void vmw_release_device_early(struct vmw_private *dev_priv)
  445. {
  446. /*
  447. * Previous destructions should've released
  448. * the pinned bo.
  449. */
  450. BUG_ON(dev_priv->pinned_bo != NULL);
  451. vmw_bo_unreference(&dev_priv->dummy_query_bo);
  452. if (dev_priv->cman)
  453. vmw_cmdbuf_remove_pool(dev_priv->cman);
  454. if (dev_priv->has_mob) {
  455. ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
  456. vmw_otables_takedown(dev_priv);
  457. }
  458. }
  459. /**
  460. * vmw_release_device_late - Late part of fifo takedown.
  461. *
  462. * @dev_priv: Pointer to device private struct.
  463. *
  464. * This is the last part of the command submission takedown, to be called when
  465. * command submission is no longer needed. It may wait on pending fences.
  466. */
  467. static void vmw_release_device_late(struct vmw_private *dev_priv)
  468. {
  469. vmw_fence_fifo_down(dev_priv->fman);
  470. if (dev_priv->cman)
  471. vmw_cmdbuf_man_destroy(dev_priv->cman);
  472. vmw_fifo_release(dev_priv, &dev_priv->fifo);
  473. }
  474. /**
  475. * Sets the initial_[width|height] fields on the given vmw_private.
  476. *
  477. * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
  478. * clamping the value to fb_max_[width|height] fields and the
  479. * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
  480. * If the values appear to be invalid, set them to
  481. * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
  482. */
  483. static void vmw_get_initial_size(struct vmw_private *dev_priv)
  484. {
  485. uint32_t width;
  486. uint32_t height;
  487. width = vmw_read(dev_priv, SVGA_REG_WIDTH);
  488. height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
  489. width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
  490. height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
  491. if (width > dev_priv->fb_max_width ||
  492. height > dev_priv->fb_max_height) {
  493. /*
  494. * This is a host error and shouldn't occur.
  495. */
  496. width = VMW_MIN_INITIAL_WIDTH;
  497. height = VMW_MIN_INITIAL_HEIGHT;
  498. }
  499. dev_priv->initial_width = width;
  500. dev_priv->initial_height = height;
  501. }
  502. /**
  503. * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
  504. * system.
  505. *
  506. * @dev_priv: Pointer to a struct vmw_private
  507. *
  508. * This functions tries to determine what actions need to be taken by the
  509. * driver to make system pages visible to the device.
  510. * If this function decides that DMA is not possible, it returns -EINVAL.
  511. * The driver may then try to disable features of the device that require
  512. * DMA.
  513. */
  514. static int vmw_dma_select_mode(struct vmw_private *dev_priv)
  515. {
  516. static const char *names[vmw_dma_map_max] = {
  517. [vmw_dma_phys] = "Using physical TTM page addresses.",
  518. [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
  519. [vmw_dma_map_populate] = "Caching DMA mappings.",
  520. [vmw_dma_map_bind] = "Giving up DMA mappings early."};
  521. /* TTM currently doesn't fully support SEV encryption. */
  522. if (mem_encrypt_active())
  523. return -EINVAL;
  524. if (vmw_force_coherent)
  525. dev_priv->map_mode = vmw_dma_alloc_coherent;
  526. else if (vmw_restrict_iommu)
  527. dev_priv->map_mode = vmw_dma_map_bind;
  528. else
  529. dev_priv->map_mode = vmw_dma_map_populate;
  530. if (!IS_ENABLED(CONFIG_DRM_TTM_DMA_PAGE_POOL) &&
  531. (dev_priv->map_mode == vmw_dma_alloc_coherent))
  532. return -EINVAL;
  533. DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
  534. return 0;
  535. }
  536. /**
  537. * vmw_dma_masks - set required page- and dma masks
  538. *
  539. * @dev: Pointer to struct drm-device
  540. *
  541. * With 32-bit we can only handle 32 bit PFNs. Optionally set that
  542. * restriction also for 64-bit systems.
  543. */
  544. static int vmw_dma_masks(struct vmw_private *dev_priv)
  545. {
  546. struct drm_device *dev = dev_priv->dev;
  547. int ret = 0;
  548. ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64));
  549. if (dev_priv->map_mode != vmw_dma_phys &&
  550. (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
  551. DRM_INFO("Restricting DMA addresses to 44 bits.\n");
  552. return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44));
  553. }
  554. return ret;
  555. }
  556. static int vmw_vram_manager_init(struct vmw_private *dev_priv)
  557. {
  558. int ret;
  559. #ifdef CONFIG_TRANSPARENT_HUGEPAGE
  560. ret = vmw_thp_init(dev_priv);
  561. #else
  562. ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false,
  563. dev_priv->vram_size >> PAGE_SHIFT);
  564. #endif
  565. ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false);
  566. return ret;
  567. }
  568. static void vmw_vram_manager_fini(struct vmw_private *dev_priv)
  569. {
  570. #ifdef CONFIG_TRANSPARENT_HUGEPAGE
  571. vmw_thp_fini(dev_priv);
  572. #else
  573. ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM);
  574. #endif
  575. }
  576. static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
  577. {
  578. struct vmw_private *dev_priv;
  579. int ret;
  580. uint32_t svga_id;
  581. enum vmw_res_type i;
  582. bool refuse_dma = false;
  583. char host_log[100] = {0};
  584. dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
  585. if (unlikely(!dev_priv)) {
  586. DRM_ERROR("Failed allocating a device private struct.\n");
  587. return -ENOMEM;
  588. }
  589. pci_set_master(dev->pdev);
  590. dev_priv->dev = dev;
  591. dev_priv->vmw_chipset = chipset;
  592. dev_priv->last_read_seqno = (uint32_t) -100;
  593. mutex_init(&dev_priv->cmdbuf_mutex);
  594. mutex_init(&dev_priv->release_mutex);
  595. mutex_init(&dev_priv->binding_mutex);
  596. mutex_init(&dev_priv->global_kms_state_mutex);
  597. ttm_lock_init(&dev_priv->reservation_sem);
  598. spin_lock_init(&dev_priv->resource_lock);
  599. spin_lock_init(&dev_priv->hw_lock);
  600. spin_lock_init(&dev_priv->waiter_lock);
  601. spin_lock_init(&dev_priv->cap_lock);
  602. spin_lock_init(&dev_priv->svga_lock);
  603. spin_lock_init(&dev_priv->cursor_lock);
  604. for (i = vmw_res_context; i < vmw_res_max; ++i) {
  605. idr_init(&dev_priv->res_idr[i]);
  606. INIT_LIST_HEAD(&dev_priv->res_lru[i]);
  607. }
  608. init_waitqueue_head(&dev_priv->fence_queue);
  609. init_waitqueue_head(&dev_priv->fifo_queue);
  610. dev_priv->fence_queue_waiters = 0;
  611. dev_priv->fifo_queue_waiters = 0;
  612. dev_priv->used_memory_size = 0;
  613. dev_priv->io_start = pci_resource_start(dev->pdev, 0);
  614. dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
  615. dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
  616. dev_priv->assume_16bpp = !!vmw_assume_16bpp;
  617. dev_priv->enable_fb = enable_fbdev;
  618. vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
  619. svga_id = vmw_read(dev_priv, SVGA_REG_ID);
  620. if (svga_id != SVGA_ID_2) {
  621. ret = -ENOSYS;
  622. DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
  623. goto out_err0;
  624. }
  625. dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
  626. if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) {
  627. dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2);
  628. }
  629. ret = vmw_dma_select_mode(dev_priv);
  630. if (unlikely(ret != 0)) {
  631. DRM_INFO("Restricting capabilities since DMA not available.\n");
  632. refuse_dma = true;
  633. if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS)
  634. DRM_INFO("Disabling 3D acceleration.\n");
  635. }
  636. dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
  637. dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
  638. dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
  639. dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
  640. vmw_get_initial_size(dev_priv);
  641. if (dev_priv->capabilities & SVGA_CAP_GMR2) {
  642. dev_priv->max_gmr_ids =
  643. vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
  644. dev_priv->max_gmr_pages =
  645. vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
  646. dev_priv->memory_size =
  647. vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
  648. dev_priv->memory_size -= dev_priv->vram_size;
  649. } else {
  650. /*
  651. * An arbitrary limit of 512MiB on surface
  652. * memory. But all HWV8 hardware supports GMR2.
  653. */
  654. dev_priv->memory_size = 512*1024*1024;
  655. }
  656. dev_priv->max_mob_pages = 0;
  657. dev_priv->max_mob_size = 0;
  658. if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
  659. uint64_t mem_size;
  660. if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2)
  661. mem_size = vmw_read(dev_priv,
  662. SVGA_REG_GBOBJECT_MEM_SIZE_KB);
  663. else
  664. mem_size =
  665. vmw_read(dev_priv,
  666. SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
  667. /*
  668. * Workaround for low memory 2D VMs to compensate for the
  669. * allocation taken by fbdev
  670. */
  671. if (!(dev_priv->capabilities & SVGA_CAP_3D))
  672. mem_size *= 3;
  673. dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
  674. dev_priv->prim_bb_mem =
  675. vmw_read(dev_priv,
  676. SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
  677. dev_priv->max_mob_size =
  678. vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
  679. dev_priv->stdu_max_width =
  680. vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
  681. dev_priv->stdu_max_height =
  682. vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
  683. vmw_write(dev_priv, SVGA_REG_DEV_CAP,
  684. SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
  685. dev_priv->texture_max_width = vmw_read(dev_priv,
  686. SVGA_REG_DEV_CAP);
  687. vmw_write(dev_priv, SVGA_REG_DEV_CAP,
  688. SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
  689. dev_priv->texture_max_height = vmw_read(dev_priv,
  690. SVGA_REG_DEV_CAP);
  691. } else {
  692. dev_priv->texture_max_width = 8192;
  693. dev_priv->texture_max_height = 8192;
  694. dev_priv->prim_bb_mem = dev_priv->vram_size;
  695. }
  696. vmw_print_capabilities(dev_priv->capabilities);
  697. if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER)
  698. vmw_print_capabilities2(dev_priv->capabilities2);
  699. ret = vmw_dma_masks(dev_priv);
  700. if (unlikely(ret != 0))
  701. goto out_err0;
  702. dma_set_max_seg_size(dev->dev, min_t(unsigned int, U32_MAX & PAGE_MASK,
  703. SCATTERLIST_MAX_SEGMENT));
  704. if (dev_priv->capabilities & SVGA_CAP_GMR2) {
  705. DRM_INFO("Max GMR ids is %u\n",
  706. (unsigned)dev_priv->max_gmr_ids);
  707. DRM_INFO("Max number of GMR pages is %u\n",
  708. (unsigned)dev_priv->max_gmr_pages);
  709. DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
  710. (unsigned)dev_priv->memory_size / 1024);
  711. }
  712. DRM_INFO("Maximum display memory size is %u kiB\n",
  713. dev_priv->prim_bb_mem / 1024);
  714. DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
  715. dev_priv->vram_start, dev_priv->vram_size / 1024);
  716. DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
  717. dev_priv->mmio_start, dev_priv->mmio_size / 1024);
  718. dev_priv->mmio_virt = memremap(dev_priv->mmio_start,
  719. dev_priv->mmio_size, MEMREMAP_WB);
  720. if (unlikely(dev_priv->mmio_virt == NULL)) {
  721. ret = -ENOMEM;
  722. DRM_ERROR("Failed mapping MMIO.\n");
  723. goto out_err0;
  724. }
  725. /* Need mmio memory to check for fifo pitchlock cap. */
  726. if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
  727. !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
  728. !vmw_fifo_have_pitchlock(dev_priv)) {
  729. ret = -ENOSYS;
  730. DRM_ERROR("Hardware has no pitchlock\n");
  731. goto out_err4;
  732. }
  733. dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12,
  734. &vmw_prime_dmabuf_ops);
  735. if (unlikely(dev_priv->tdev == NULL)) {
  736. DRM_ERROR("Unable to initialize TTM object management.\n");
  737. ret = -ENOMEM;
  738. goto out_err4;
  739. }
  740. dev->dev_private = dev_priv;
  741. ret = pci_request_regions(dev->pdev, "vmwgfx probe");
  742. dev_priv->stealth = (ret != 0);
  743. if (dev_priv->stealth) {
  744. /**
  745. * Request at least the mmio PCI resource.
  746. */
  747. DRM_INFO("It appears like vesafb is loaded. "
  748. "Ignore above error if any.\n");
  749. ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
  750. if (unlikely(ret != 0)) {
  751. DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
  752. goto out_no_device;
  753. }
  754. }
  755. if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
  756. ret = vmw_irq_install(dev, dev->pdev->irq);
  757. if (ret != 0) {
  758. DRM_ERROR("Failed installing irq: %d\n", ret);
  759. goto out_no_irq;
  760. }
  761. }
  762. dev_priv->fman = vmw_fence_manager_init(dev_priv);
  763. if (unlikely(dev_priv->fman == NULL)) {
  764. ret = -ENOMEM;
  765. goto out_no_fman;
  766. }
  767. drm_vma_offset_manager_init(&dev_priv->vma_manager,
  768. DRM_FILE_PAGE_OFFSET_START,
  769. DRM_FILE_PAGE_OFFSET_SIZE);
  770. ret = ttm_bo_device_init(&dev_priv->bdev,
  771. &vmw_bo_driver,
  772. dev->anon_inode->i_mapping,
  773. &dev_priv->vma_manager,
  774. false);
  775. if (unlikely(ret != 0)) {
  776. DRM_ERROR("Failed initializing TTM buffer object driver.\n");
  777. goto out_no_bdev;
  778. }
  779. /*
  780. * Enable VRAM, but initially don't use it until SVGA is enabled and
  781. * unhidden.
  782. */
  783. ret = vmw_vram_manager_init(dev_priv);
  784. if (unlikely(ret != 0)) {
  785. DRM_ERROR("Failed initializing memory manager for VRAM.\n");
  786. goto out_no_vram;
  787. }
  788. /*
  789. * "Guest Memory Regions" is an aperture like feature with
  790. * one slot per bo. There is an upper limit of the number of
  791. * slots as well as the bo size.
  792. */
  793. dev_priv->has_gmr = true;
  794. /* TODO: This is most likely not correct */
  795. if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
  796. refuse_dma ||
  797. vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) {
  798. DRM_INFO("No GMR memory available. "
  799. "Graphics memory resources are very limited.\n");
  800. dev_priv->has_gmr = false;
  801. }
  802. if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) {
  803. dev_priv->has_mob = true;
  804. if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) {
  805. DRM_INFO("No MOB memory available. "
  806. "3D will be disabled.\n");
  807. dev_priv->has_mob = false;
  808. }
  809. }
  810. if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) {
  811. spin_lock(&dev_priv->cap_lock);
  812. vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT);
  813. if (vmw_read(dev_priv, SVGA_REG_DEV_CAP))
  814. dev_priv->sm_type = VMW_SM_4;
  815. spin_unlock(&dev_priv->cap_lock);
  816. }
  817. vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN);
  818. /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */
  819. if (has_sm4_context(dev_priv) &&
  820. (dev_priv->capabilities2 & SVGA_CAP2_DX2)) {
  821. vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM41);
  822. if (vmw_read(dev_priv, SVGA_REG_DEV_CAP))
  823. dev_priv->sm_type = VMW_SM_4_1;
  824. if (has_sm4_1_context(dev_priv) &&
  825. (dev_priv->capabilities2 & SVGA_CAP2_DX3)) {
  826. vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM5);
  827. if (vmw_read(dev_priv, SVGA_REG_DEV_CAP))
  828. dev_priv->sm_type = VMW_SM_5;
  829. }
  830. }
  831. ret = vmw_kms_init(dev_priv);
  832. if (unlikely(ret != 0))
  833. goto out_no_kms;
  834. vmw_overlay_init(dev_priv);
  835. ret = vmw_request_device(dev_priv);
  836. if (ret)
  837. goto out_no_fifo;
  838. DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC)
  839. ? "yes." : "no.");
  840. if (dev_priv->sm_type == VMW_SM_5)
  841. DRM_INFO("SM5 support available.\n");
  842. if (dev_priv->sm_type == VMW_SM_4_1)
  843. DRM_INFO("SM4_1 support available.\n");
  844. if (dev_priv->sm_type == VMW_SM_4)
  845. DRM_INFO("SM4 support available.\n");
  846. snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s",
  847. VMWGFX_REPO, VMWGFX_GIT_VERSION);
  848. vmw_host_log(host_log);
  849. memset(host_log, 0, sizeof(host_log));
  850. snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d",
  851. VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR,
  852. VMWGFX_DRIVER_PATCHLEVEL);
  853. vmw_host_log(host_log);
  854. if (dev_priv->enable_fb) {
  855. vmw_fifo_resource_inc(dev_priv);
  856. vmw_svga_enable(dev_priv);
  857. vmw_fb_init(dev_priv);
  858. }
  859. dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
  860. register_pm_notifier(&dev_priv->pm_nb);
  861. return 0;
  862. out_no_fifo:
  863. vmw_overlay_close(dev_priv);
  864. vmw_kms_close(dev_priv);
  865. out_no_kms:
  866. if (dev_priv->has_mob)
  867. vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB);
  868. if (dev_priv->has_gmr)
  869. vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR);
  870. vmw_vram_manager_fini(dev_priv);
  871. out_no_vram:
  872. (void)ttm_bo_device_release(&dev_priv->bdev);
  873. out_no_bdev:
  874. vmw_fence_manager_takedown(dev_priv->fman);
  875. out_no_fman:
  876. if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
  877. vmw_irq_uninstall(dev_priv->dev);
  878. out_no_irq:
  879. if (dev_priv->stealth)
  880. pci_release_region(dev->pdev, 2);
  881. else
  882. pci_release_regions(dev->pdev);
  883. out_no_device:
  884. ttm_object_device_release(&dev_priv->tdev);
  885. out_err4:
  886. memunmap(dev_priv->mmio_virt);
  887. out_err0:
  888. for (i = vmw_res_context; i < vmw_res_max; ++i)
  889. idr_destroy(&dev_priv->res_idr[i]);
  890. if (dev_priv->ctx.staged_bindings)
  891. vmw_binding_state_free(dev_priv->ctx.staged_bindings);
  892. kfree(dev_priv);
  893. return ret;
  894. }
  895. static void vmw_driver_unload(struct drm_device *dev)
  896. {
  897. struct vmw_private *dev_priv = vmw_priv(dev);
  898. enum vmw_res_type i;
  899. unregister_pm_notifier(&dev_priv->pm_nb);
  900. if (dev_priv->ctx.res_ht_initialized)
  901. drm_ht_remove(&dev_priv->ctx.res_ht);
  902. vfree(dev_priv->ctx.cmd_bounce);
  903. if (dev_priv->enable_fb) {
  904. vmw_fb_off(dev_priv);
  905. vmw_fb_close(dev_priv);
  906. vmw_fifo_resource_dec(dev_priv);
  907. vmw_svga_disable(dev_priv);
  908. }
  909. vmw_kms_close(dev_priv);
  910. vmw_overlay_close(dev_priv);
  911. if (dev_priv->has_gmr)
  912. vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR);
  913. vmw_release_device_early(dev_priv);
  914. if (dev_priv->has_mob)
  915. vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB);
  916. vmw_vram_manager_fini(dev_priv);
  917. (void) ttm_bo_device_release(&dev_priv->bdev);
  918. drm_vma_offset_manager_destroy(&dev_priv->vma_manager);
  919. vmw_release_device_late(dev_priv);
  920. vmw_fence_manager_takedown(dev_priv->fman);
  921. if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
  922. vmw_irq_uninstall(dev_priv->dev);
  923. if (dev_priv->stealth)
  924. pci_release_region(dev->pdev, 2);
  925. else
  926. pci_release_regions(dev->pdev);
  927. ttm_object_device_release(&dev_priv->tdev);
  928. memunmap(dev_priv->mmio_virt);
  929. if (dev_priv->ctx.staged_bindings)
  930. vmw_binding_state_free(dev_priv->ctx.staged_bindings);
  931. for (i = vmw_res_context; i < vmw_res_max; ++i)
  932. idr_destroy(&dev_priv->res_idr[i]);
  933. kfree(dev_priv);
  934. }
  935. static void vmw_postclose(struct drm_device *dev,
  936. struct drm_file *file_priv)
  937. {
  938. struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
  939. ttm_object_file_release(&vmw_fp->tfile);
  940. kfree(vmw_fp);
  941. }
  942. static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
  943. {
  944. struct vmw_private *dev_priv = vmw_priv(dev);
  945. struct vmw_fpriv *vmw_fp;
  946. int ret = -ENOMEM;
  947. vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
  948. if (unlikely(!vmw_fp))
  949. return ret;
  950. vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
  951. if (unlikely(vmw_fp->tfile == NULL))
  952. goto out_no_tfile;
  953. file_priv->driver_priv = vmw_fp;
  954. return 0;
  955. out_no_tfile:
  956. kfree(vmw_fp);
  957. return ret;
  958. }
  959. static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
  960. unsigned long arg,
  961. long (*ioctl_func)(struct file *, unsigned int,
  962. unsigned long))
  963. {
  964. struct drm_file *file_priv = filp->private_data;
  965. struct drm_device *dev = file_priv->minor->dev;
  966. unsigned int nr = DRM_IOCTL_NR(cmd);
  967. unsigned int flags;
  968. /*
  969. * Do extra checking on driver private ioctls.
  970. */
  971. if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
  972. && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
  973. const struct drm_ioctl_desc *ioctl =
  974. &vmw_ioctls[nr - DRM_COMMAND_BASE];
  975. if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
  976. return ioctl_func(filp, cmd, arg);
  977. } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) {
  978. if (!drm_is_current_master(file_priv) &&
  979. !capable(CAP_SYS_ADMIN))
  980. return -EACCES;
  981. }
  982. if (unlikely(ioctl->cmd != cmd))
  983. goto out_io_encoding;
  984. flags = ioctl->flags;
  985. } else if (!drm_ioctl_flags(nr, &flags))
  986. return -EINVAL;
  987. return ioctl_func(filp, cmd, arg);
  988. out_io_encoding:
  989. DRM_ERROR("Invalid command format, ioctl %d\n",
  990. nr - DRM_COMMAND_BASE);
  991. return -EINVAL;
  992. }
  993. static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
  994. unsigned long arg)
  995. {
  996. return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
  997. }
  998. #ifdef CONFIG_COMPAT
  999. static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
  1000. unsigned long arg)
  1001. {
  1002. return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
  1003. }
  1004. #endif
  1005. static void vmw_master_set(struct drm_device *dev,
  1006. struct drm_file *file_priv,
  1007. bool from_open)
  1008. {
  1009. /*
  1010. * Inform a new master that the layout may have changed while
  1011. * it was gone.
  1012. */
  1013. if (!from_open)
  1014. drm_sysfs_hotplug_event(dev);
  1015. }
  1016. static void vmw_master_drop(struct drm_device *dev,
  1017. struct drm_file *file_priv)
  1018. {
  1019. struct vmw_private *dev_priv = vmw_priv(dev);
  1020. vmw_kms_legacy_hotspot_clear(dev_priv);
  1021. if (!dev_priv->enable_fb)
  1022. vmw_svga_disable(dev_priv);
  1023. }
  1024. /**
  1025. * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
  1026. *
  1027. * @dev_priv: Pointer to device private struct.
  1028. * Needs the reservation sem to be held in non-exclusive mode.
  1029. */
  1030. static void __vmw_svga_enable(struct vmw_private *dev_priv)
  1031. {
  1032. struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
  1033. spin_lock(&dev_priv->svga_lock);
  1034. if (!ttm_resource_manager_used(man)) {
  1035. vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE);
  1036. ttm_resource_manager_set_used(man, true);
  1037. }
  1038. spin_unlock(&dev_priv->svga_lock);
  1039. }
  1040. /**
  1041. * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
  1042. *
  1043. * @dev_priv: Pointer to device private struct.
  1044. */
  1045. void vmw_svga_enable(struct vmw_private *dev_priv)
  1046. {
  1047. (void) ttm_read_lock(&dev_priv->reservation_sem, false);
  1048. __vmw_svga_enable(dev_priv);
  1049. ttm_read_unlock(&dev_priv->reservation_sem);
  1050. }
  1051. /**
  1052. * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
  1053. *
  1054. * @dev_priv: Pointer to device private struct.
  1055. * Needs the reservation sem to be held in exclusive mode.
  1056. * Will not empty VRAM. VRAM must be emptied by caller.
  1057. */
  1058. static void __vmw_svga_disable(struct vmw_private *dev_priv)
  1059. {
  1060. struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
  1061. spin_lock(&dev_priv->svga_lock);
  1062. if (ttm_resource_manager_used(man)) {
  1063. ttm_resource_manager_set_used(man, false);
  1064. vmw_write(dev_priv, SVGA_REG_ENABLE,
  1065. SVGA_REG_ENABLE_HIDE |
  1066. SVGA_REG_ENABLE_ENABLE);
  1067. }
  1068. spin_unlock(&dev_priv->svga_lock);
  1069. }
  1070. /**
  1071. * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
  1072. * running.
  1073. *
  1074. * @dev_priv: Pointer to device private struct.
  1075. * Will empty VRAM.
  1076. */
  1077. void vmw_svga_disable(struct vmw_private *dev_priv)
  1078. {
  1079. struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
  1080. /*
  1081. * Disabling SVGA will turn off device modesetting capabilities, so
  1082. * notify KMS about that so that it doesn't cache atomic state that
  1083. * isn't valid anymore, for example crtcs turned on.
  1084. * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex),
  1085. * but vmw_kms_lost_device() takes the reservation sem and thus we'll
  1086. * end up with lock order reversal. Thus, a master may actually perform
  1087. * a new modeset just after we call vmw_kms_lost_device() and race with
  1088. * vmw_svga_disable(), but that should at worst cause atomic KMS state
  1089. * to be inconsistent with the device, causing modesetting problems.
  1090. *
  1091. */
  1092. vmw_kms_lost_device(dev_priv->dev);
  1093. ttm_write_lock(&dev_priv->reservation_sem, false);
  1094. spin_lock(&dev_priv->svga_lock);
  1095. if (ttm_resource_manager_used(man)) {
  1096. ttm_resource_manager_set_used(man, false);
  1097. spin_unlock(&dev_priv->svga_lock);
  1098. if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM))
  1099. DRM_ERROR("Failed evicting VRAM buffers.\n");
  1100. vmw_write(dev_priv, SVGA_REG_ENABLE,
  1101. SVGA_REG_ENABLE_HIDE |
  1102. SVGA_REG_ENABLE_ENABLE);
  1103. } else
  1104. spin_unlock(&dev_priv->svga_lock);
  1105. ttm_write_unlock(&dev_priv->reservation_sem);
  1106. }
  1107. static void vmw_remove(struct pci_dev *pdev)
  1108. {
  1109. struct drm_device *dev = pci_get_drvdata(pdev);
  1110. drm_dev_unregister(dev);
  1111. vmw_driver_unload(dev);
  1112. drm_dev_put(dev);
  1113. pci_disable_device(pdev);
  1114. }
  1115. static unsigned long
  1116. vmw_get_unmapped_area(struct file *file, unsigned long uaddr,
  1117. unsigned long len, unsigned long pgoff,
  1118. unsigned long flags)
  1119. {
  1120. struct drm_file *file_priv = file->private_data;
  1121. struct vmw_private *dev_priv = vmw_priv(file_priv->minor->dev);
  1122. return drm_get_unmapped_area(file, uaddr, len, pgoff, flags,
  1123. &dev_priv->vma_manager);
  1124. }
  1125. static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
  1126. void *ptr)
  1127. {
  1128. struct vmw_private *dev_priv =
  1129. container_of(nb, struct vmw_private, pm_nb);
  1130. switch (val) {
  1131. case PM_HIBERNATION_PREPARE:
  1132. /*
  1133. * Take the reservation sem in write mode, which will make sure
  1134. * there are no other processes holding a buffer object
  1135. * reservation, meaning we should be able to evict all buffer
  1136. * objects if needed.
  1137. * Once user-space processes have been frozen, we can release
  1138. * the lock again.
  1139. */
  1140. ttm_suspend_lock(&dev_priv->reservation_sem);
  1141. dev_priv->suspend_locked = true;
  1142. break;
  1143. case PM_POST_HIBERNATION:
  1144. case PM_POST_RESTORE:
  1145. if (READ_ONCE(dev_priv->suspend_locked)) {
  1146. dev_priv->suspend_locked = false;
  1147. ttm_suspend_unlock(&dev_priv->reservation_sem);
  1148. }
  1149. break;
  1150. default:
  1151. break;
  1152. }
  1153. return 0;
  1154. }
  1155. static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  1156. {
  1157. struct drm_device *dev = pci_get_drvdata(pdev);
  1158. struct vmw_private *dev_priv = vmw_priv(dev);
  1159. if (dev_priv->refuse_hibernation)
  1160. return -EBUSY;
  1161. pci_save_state(pdev);
  1162. pci_disable_device(pdev);
  1163. pci_set_power_state(pdev, PCI_D3hot);
  1164. return 0;
  1165. }
  1166. static int vmw_pci_resume(struct pci_dev *pdev)
  1167. {
  1168. pci_set_power_state(pdev, PCI_D0);
  1169. pci_restore_state(pdev);
  1170. return pci_enable_device(pdev);
  1171. }
  1172. static int vmw_pm_suspend(struct device *kdev)
  1173. {
  1174. struct pci_dev *pdev = to_pci_dev(kdev);
  1175. struct pm_message dummy;
  1176. dummy.event = 0;
  1177. return vmw_pci_suspend(pdev, dummy);
  1178. }
  1179. static int vmw_pm_resume(struct device *kdev)
  1180. {
  1181. struct pci_dev *pdev = to_pci_dev(kdev);
  1182. return vmw_pci_resume(pdev);
  1183. }
  1184. static int vmw_pm_freeze(struct device *kdev)
  1185. {
  1186. struct pci_dev *pdev = to_pci_dev(kdev);
  1187. struct drm_device *dev = pci_get_drvdata(pdev);
  1188. struct vmw_private *dev_priv = vmw_priv(dev);
  1189. int ret;
  1190. /*
  1191. * Unlock for vmw_kms_suspend.
  1192. * No user-space processes should be running now.
  1193. */
  1194. ttm_suspend_unlock(&dev_priv->reservation_sem);
  1195. ret = vmw_kms_suspend(dev_priv->dev);
  1196. if (ret) {
  1197. ttm_suspend_lock(&dev_priv->reservation_sem);
  1198. DRM_ERROR("Failed to freeze modesetting.\n");
  1199. return ret;
  1200. }
  1201. if (dev_priv->enable_fb)
  1202. vmw_fb_off(dev_priv);
  1203. ttm_suspend_lock(&dev_priv->reservation_sem);
  1204. vmw_execbuf_release_pinned_bo(dev_priv);
  1205. vmw_resource_evict_all(dev_priv);
  1206. vmw_release_device_early(dev_priv);
  1207. ttm_bo_swapout_all();
  1208. if (dev_priv->enable_fb)
  1209. vmw_fifo_resource_dec(dev_priv);
  1210. if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
  1211. DRM_ERROR("Can't hibernate while 3D resources are active.\n");
  1212. if (dev_priv->enable_fb)
  1213. vmw_fifo_resource_inc(dev_priv);
  1214. WARN_ON(vmw_request_device_late(dev_priv));
  1215. dev_priv->suspend_locked = false;
  1216. ttm_suspend_unlock(&dev_priv->reservation_sem);
  1217. if (dev_priv->suspend_state)
  1218. vmw_kms_resume(dev);
  1219. if (dev_priv->enable_fb)
  1220. vmw_fb_on(dev_priv);
  1221. return -EBUSY;
  1222. }
  1223. vmw_fence_fifo_down(dev_priv->fman);
  1224. __vmw_svga_disable(dev_priv);
  1225. vmw_release_device_late(dev_priv);
  1226. return 0;
  1227. }
  1228. static int vmw_pm_restore(struct device *kdev)
  1229. {
  1230. struct pci_dev *pdev = to_pci_dev(kdev);
  1231. struct drm_device *dev = pci_get_drvdata(pdev);
  1232. struct vmw_private *dev_priv = vmw_priv(dev);
  1233. int ret;
  1234. vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
  1235. (void) vmw_read(dev_priv, SVGA_REG_ID);
  1236. if (dev_priv->enable_fb)
  1237. vmw_fifo_resource_inc(dev_priv);
  1238. ret = vmw_request_device(dev_priv);
  1239. if (ret)
  1240. return ret;
  1241. if (dev_priv->enable_fb)
  1242. __vmw_svga_enable(dev_priv);
  1243. vmw_fence_fifo_up(dev_priv->fman);
  1244. dev_priv->suspend_locked = false;
  1245. ttm_suspend_unlock(&dev_priv->reservation_sem);
  1246. if (dev_priv->suspend_state)
  1247. vmw_kms_resume(dev_priv->dev);
  1248. if (dev_priv->enable_fb)
  1249. vmw_fb_on(dev_priv);
  1250. return 0;
  1251. }
  1252. static const struct dev_pm_ops vmw_pm_ops = {
  1253. .freeze = vmw_pm_freeze,
  1254. .thaw = vmw_pm_restore,
  1255. .restore = vmw_pm_restore,
  1256. .suspend = vmw_pm_suspend,
  1257. .resume = vmw_pm_resume,
  1258. };
  1259. static const struct file_operations vmwgfx_driver_fops = {
  1260. .owner = THIS_MODULE,
  1261. .open = drm_open,
  1262. .release = drm_release,
  1263. .unlocked_ioctl = vmw_unlocked_ioctl,
  1264. .mmap = vmw_mmap,
  1265. .poll = vmw_fops_poll,
  1266. .read = vmw_fops_read,
  1267. #if defined(CONFIG_COMPAT)
  1268. .compat_ioctl = vmw_compat_ioctl,
  1269. #endif
  1270. .llseek = noop_llseek,
  1271. .get_unmapped_area = vmw_get_unmapped_area,
  1272. };
  1273. static struct drm_driver driver = {
  1274. .driver_features =
  1275. DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC,
  1276. .ioctls = vmw_ioctls,
  1277. .num_ioctls = ARRAY_SIZE(vmw_ioctls),
  1278. .master_set = vmw_master_set,
  1279. .master_drop = vmw_master_drop,
  1280. .open = vmw_driver_open,
  1281. .postclose = vmw_postclose,
  1282. .dumb_create = vmw_dumb_create,
  1283. .dumb_map_offset = vmw_dumb_map_offset,
  1284. .dumb_destroy = vmw_dumb_destroy,
  1285. .prime_fd_to_handle = vmw_prime_fd_to_handle,
  1286. .prime_handle_to_fd = vmw_prime_handle_to_fd,
  1287. .fops = &vmwgfx_driver_fops,
  1288. .name = VMWGFX_DRIVER_NAME,
  1289. .desc = VMWGFX_DRIVER_DESC,
  1290. .date = VMWGFX_DRIVER_DATE,
  1291. .major = VMWGFX_DRIVER_MAJOR,
  1292. .minor = VMWGFX_DRIVER_MINOR,
  1293. .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
  1294. };
  1295. static struct pci_driver vmw_pci_driver = {
  1296. .name = VMWGFX_DRIVER_NAME,
  1297. .id_table = vmw_pci_id_list,
  1298. .probe = vmw_probe,
  1299. .remove = vmw_remove,
  1300. .driver = {
  1301. .pm = &vmw_pm_ops
  1302. }
  1303. };
  1304. static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  1305. {
  1306. struct drm_device *dev;
  1307. int ret;
  1308. ret = pci_enable_device(pdev);
  1309. if (ret)
  1310. return ret;
  1311. dev = drm_dev_alloc(&driver, &pdev->dev);
  1312. if (IS_ERR(dev)) {
  1313. ret = PTR_ERR(dev);
  1314. goto err_pci_disable_device;
  1315. }
  1316. dev->pdev = pdev;
  1317. pci_set_drvdata(pdev, dev);
  1318. ret = vmw_driver_load(dev, ent->driver_data);
  1319. if (ret)
  1320. goto err_drm_dev_put;
  1321. ret = drm_dev_register(dev, ent->driver_data);
  1322. if (ret)
  1323. goto err_vmw_driver_unload;
  1324. return 0;
  1325. err_vmw_driver_unload:
  1326. vmw_driver_unload(dev);
  1327. err_drm_dev_put:
  1328. drm_dev_put(dev);
  1329. err_pci_disable_device:
  1330. pci_disable_device(pdev);
  1331. return ret;
  1332. }
  1333. static int __init vmwgfx_init(void)
  1334. {
  1335. int ret;
  1336. if (vgacon_text_force())
  1337. return -EINVAL;
  1338. ret = pci_register_driver(&vmw_pci_driver);
  1339. if (ret)
  1340. DRM_ERROR("Failed initializing DRM.\n");
  1341. return ret;
  1342. }
  1343. static void __exit vmwgfx_exit(void)
  1344. {
  1345. pci_unregister_driver(&vmw_pci_driver);
  1346. }
  1347. module_init(vmwgfx_init);
  1348. module_exit(vmwgfx_exit);
  1349. MODULE_AUTHOR("VMware Inc. and others");
  1350. MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
  1351. MODULE_LICENSE("GPL and additional rights");
  1352. MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
  1353. __stringify(VMWGFX_DRIVER_MINOR) "."
  1354. __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
  1355. "0");