vs_dc_hw.c 80 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020 VeriSilicon Holdings Co., Ltd.
  4. */
  5. #include <linux/io.h>
  6. #include <linux/bits.h>
  7. #include <linux/delay.h>
  8. #include <linux/media-bus-format.h>
  9. #include <drm/vs_drm.h>
  10. #include "vs_type.h"
  11. #include "vs_dc_hw.h"
  12. #include "vs_dc_dec.h"
  13. static const u32 horKernel[] = {
  14. 0x00000000, 0x20000000, 0x00002000, 0x00000000,
  15. 0x00000000, 0x00000000, 0x23fd1c03, 0x00000000,
  16. 0x00000000, 0x00000000, 0x181f0000, 0x000027e1,
  17. 0x00000000, 0x00000000, 0x00000000, 0x2b981468,
  18. 0x00000000, 0x00000000, 0x00000000, 0x10f00000,
  19. 0x00002f10, 0x00000000, 0x00000000, 0x00000000,
  20. 0x32390dc7, 0x00000000, 0x00000000, 0x00000000,
  21. 0x0af50000, 0x0000350b, 0x00000000, 0x00000000,
  22. 0x00000000, 0x3781087f, 0x00000000, 0x00000000,
  23. 0x00000000, 0x06660000, 0x0000399a, 0x00000000,
  24. 0x00000000, 0x00000000, 0x3b5904a7, 0x00000000,
  25. 0x00000000, 0x00000000, 0x033c0000, 0x00003cc4,
  26. 0x00000000, 0x00000000, 0x00000000, 0x3de1021f,
  27. 0x00000000, 0x00000000, 0x00000000, 0x01470000,
  28. 0x00003eb9, 0x00000000, 0x00000000, 0x00000000,
  29. 0x3f5300ad, 0x00000000, 0x00000000, 0x00000000,
  30. 0x00480000, 0x00003fb8, 0x00000000, 0x00000000,
  31. 0x00000000, 0x3fef0011, 0x00000000, 0x00000000,
  32. 0x00000000, 0x00000000, 0x00004000, 0x00000000,
  33. 0x00000000, 0x00000000, 0x20002000, 0x00000000,
  34. 0x00000000, 0x00000000, 0x1c030000, 0x000023fd,
  35. 0x00000000, 0x00000000, 0x00000000, 0x27e1181f,
  36. 0x00000000, 0x00000000, 0x00000000, 0x14680000,
  37. 0x00002b98, 0x00000000, 0x00000000, 0x00000000,
  38. 0x2f1010f0, 0x00000000, 0x00000000, 0x00000000,
  39. 0x0dc70000, 0x00003239, 0x00000000, 0x00000000,
  40. 0x00000000, 0x350b0af5, 0x00000000, 0x00000000,
  41. 0x00000000, 0x087f0000, 0x00003781, 0x00000000,
  42. 0x00000000, 0x00000000, 0x399a0666, 0x00000000,
  43. 0x00000000, 0x00000000, 0x04a70000, 0x00003b59,
  44. 0x00000000, 0x00000000, 0x00000000, 0x3cc4033c,
  45. 0x00000000, 0x00000000, 0x00000000, 0x021f0000,
  46. };
  47. #define H_COEF_SIZE (sizeof(horKernel) / sizeof(u32))
  48. static const u32 verKernel[] = {
  49. 0x00000000, 0x20000000, 0x00002000, 0x00000000,
  50. 0x00000000, 0x00000000, 0x23fd1c03, 0x00000000,
  51. 0x00000000, 0x00000000, 0x181f0000, 0x000027e1,
  52. 0x00000000, 0x00000000, 0x00000000, 0x2b981468,
  53. 0x00000000, 0x00000000, 0x00000000, 0x10f00000,
  54. 0x00002f10, 0x00000000, 0x00000000, 0x00000000,
  55. 0x32390dc7, 0x00000000, 0x00000000, 0x00000000,
  56. 0x0af50000, 0x0000350b, 0x00000000, 0x00000000,
  57. 0x00000000, 0x3781087f, 0x00000000, 0x00000000,
  58. 0x00000000, 0x06660000, 0x0000399a, 0x00000000,
  59. 0x00000000, 0x00000000, 0x3b5904a7, 0x00000000,
  60. 0x00000000, 0x00000000, 0x033c0000, 0x00003cc4,
  61. 0x00000000, 0x00000000, 0x00000000, 0x3de1021f,
  62. 0x00000000, 0x00000000, 0x00000000, 0x01470000,
  63. 0x00003eb9, 0x00000000, 0x00000000, 0x00000000,
  64. 0x3f5300ad, 0x00000000, 0x00000000, 0x00000000,
  65. 0x00480000, 0x00003fb8, 0x00000000, 0x00000000,
  66. 0x00000000, 0x3fef0011, 0x00000000, 0x00000000,
  67. 0x00000000, 0x00000000, 0x00004000, 0x00000000,
  68. 0xcdcd0000, 0xfdfdfdfd, 0xabababab, 0xabababab,
  69. 0x00000000, 0x00000000, 0x5ff5f456, 0x000f5f58,
  70. 0x02cc6c78, 0x02cc0c28, 0xfeeefeee, 0xfeeefeee,
  71. 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
  72. 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
  73. 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
  74. 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
  75. 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
  76. 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
  77. 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
  78. 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
  79. 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
  80. 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
  81. };
  82. #define V_COEF_SIZE (sizeof(verKernel) / sizeof(u32))
  83. /*
  84. * RGB 709->2020 conversion parameters
  85. */
  86. static u16 RGB2RGB[RGB_TO_RGB_TABLE_SIZE] = {
  87. 10279, 5395, 709,
  88. 1132, 15065, 187,
  89. 269, 1442, 14674
  90. };
  91. /*
  92. * YUV601 to RGB conversion parameters
  93. * YUV2RGB[0] - [8] : C0 - C8;
  94. * YUV2RGB[9] - [11]: D0 - D2;
  95. * YUV2RGB[12] - [13]: Y clamp min & max calue;
  96. * YUV2RGB[14] - [15]: UV clamp min & max calue;
  97. */
  98. static s32 YUV601_2RGB[YUV_TO_RGB_TABLE_SIZE] = {
  99. 1196, 0, 1640, 1196,
  100. -404, -836, 1196, 2076,
  101. 0, -916224, 558336, -1202944,
  102. 64, 940, 64, 960
  103. };
  104. /*
  105. * YUV709 to RGB conversion parameters
  106. * YUV2RGB[0] - [8] : C0 - C8;
  107. * YUV2RGB[9] - [11]: D0 - D2;
  108. * YUV2RGB[12] - [13]: Y clamp min & max calue;
  109. * YUV2RGB[14] - [15]: UV clamp min & max calue;
  110. */
  111. static s32 YUV709_2RGB[YUV_TO_RGB_TABLE_SIZE] = {
  112. 1196, 0, 1844, 1196,
  113. -220, -548, 1196, 2172,
  114. 0, -1020672, 316672, -1188608,
  115. 64, 940, 64, 960
  116. };
  117. /*
  118. * YUV2020 to RGB conversion parameters
  119. * YUV2RGB[0] - [8] : C0 - C8;
  120. * YUV2RGB[9] - [11]: D0 - D2;
  121. * YUV2RGB[12] - [13]: Y clamp min & max calue;
  122. * YUV2RGB[14] - [15]: UV clamp min & max calue;
  123. */
  124. static s32 YUV2020_2RGB[YUV_TO_RGB_TABLE_SIZE] = {
  125. 1196, 0, 1724, 1196,
  126. -192, -668, 1196, 2200,
  127. 0, -959232, 363776, -1202944,
  128. 64, 940, 64, 960
  129. };
  130. /*
  131. * RGB to YUV2020 conversion parameters
  132. * RGB2YUV[0] - [8] : C0 - C8;
  133. * RGB2YUV[9] - [11]: D0 - D2;
  134. */
  135. static s16 RGB2YUV[RGB_TO_YUV_TABLE_SIZE] = {
  136. 230, 594, 52,
  137. -125, -323, 448,
  138. 448, -412, -36,
  139. 64, 512, 512
  140. };
  141. /*
  142. * Degamma table for 709 color space data.
  143. */
  144. static u16 DEGAMMA_709[DEGAMMA_SIZE] = {
  145. 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0002, 0x0004, 0x0005,
  146. 0x0007, 0x000a, 0x000d, 0x0011, 0x0015, 0x0019, 0x001e, 0x0024,
  147. 0x002a, 0x0030, 0x0038, 0x003f, 0x0048, 0x0051, 0x005a, 0x0064,
  148. 0x006f, 0x007b, 0x0087, 0x0094, 0x00a1, 0x00af, 0x00be, 0x00ce,
  149. 0x00de, 0x00ef, 0x0101, 0x0114, 0x0127, 0x013b, 0x0150, 0x0166,
  150. 0x017c, 0x0193, 0x01ac, 0x01c4, 0x01de, 0x01f9, 0x0214, 0x0230,
  151. 0x024d, 0x026b, 0x028a, 0x02aa, 0x02ca, 0x02ec, 0x030e, 0x0331,
  152. 0x0355, 0x037a, 0x03a0, 0x03c7, 0x03ef, 0x0418, 0x0441, 0x046c,
  153. 0x0498, 0x04c4, 0x04f2, 0x0520, 0x0550, 0x0581, 0x05b2, 0x05e5,
  154. 0x0618, 0x064d, 0x0682, 0x06b9, 0x06f0, 0x0729, 0x0763, 0x079d,
  155. 0x07d9, 0x0816, 0x0854, 0x0893, 0x08d3, 0x0914, 0x0956, 0x0999,
  156. 0x09dd, 0x0a23, 0x0a69, 0x0ab1, 0x0afa, 0x0b44, 0x0b8f, 0x0bdb,
  157. 0x0c28, 0x0c76, 0x0cc6, 0x0d17, 0x0d69, 0x0dbb, 0x0e10, 0x0e65,
  158. 0x0ebb, 0x0f13, 0x0f6c, 0x0fc6, 0x1021, 0x107d, 0x10db, 0x113a,
  159. 0x119a, 0x11fb, 0x125d, 0x12c1, 0x1325, 0x138c, 0x13f3, 0x145b,
  160. 0x14c5, 0x1530, 0x159c, 0x160a, 0x1678, 0x16e8, 0x175a, 0x17cc,
  161. 0x1840, 0x18b5, 0x192b, 0x19a3, 0x1a1c, 0x1a96, 0x1b11, 0x1b8e,
  162. 0x1c0c, 0x1c8c, 0x1d0c, 0x1d8e, 0x1e12, 0x1e96, 0x1f1c, 0x1fa3,
  163. 0x202c, 0x20b6, 0x2141, 0x21ce, 0x225c, 0x22eb, 0x237c, 0x240e,
  164. 0x24a1, 0x2536, 0x25cc, 0x2664, 0x26fc, 0x2797, 0x2832, 0x28cf,
  165. 0x296e, 0x2a0e, 0x2aaf, 0x2b51, 0x2bf5, 0x2c9b, 0x2d41, 0x2dea,
  166. 0x2e93, 0x2f3e, 0x2feb, 0x3099, 0x3148, 0x31f9, 0x32ab, 0x335f,
  167. 0x3414, 0x34ca, 0x3582, 0x363c, 0x36f7, 0x37b3, 0x3871, 0x3930,
  168. 0x39f1, 0x3ab3, 0x3b77, 0x3c3c, 0x3d02, 0x3dcb, 0x3e94, 0x3f5f,
  169. 0x402c, 0x40fa, 0x41ca, 0x429b, 0x436d, 0x4442, 0x4517, 0x45ee,
  170. 0x46c7, 0x47a1, 0x487d, 0x495a, 0x4a39, 0x4b19, 0x4bfb, 0x4cde,
  171. 0x4dc3, 0x4eaa, 0x4f92, 0x507c, 0x5167, 0x5253, 0x5342, 0x5431,
  172. 0x5523, 0x5616, 0x570a, 0x5800, 0x58f8, 0x59f1, 0x5aec, 0x5be9,
  173. 0x5ce7, 0x5de6, 0x5ee7, 0x5fea, 0x60ef, 0x61f5, 0x62fc, 0x6406,
  174. 0x6510, 0x661d, 0x672b, 0x683b, 0x694c, 0x6a5f, 0x6b73, 0x6c8a,
  175. 0x6da2, 0x6ebb, 0x6fd6, 0x70f3, 0x7211, 0x7331, 0x7453, 0x7576,
  176. 0x769b, 0x77c2, 0x78ea, 0x7a14, 0x7b40, 0x7c6d, 0x7d9c, 0x7ecd,
  177. 0x3f65, 0x3f8c, 0x3fb2, 0x3fd8
  178. };
  179. /*
  180. * Degamma table for 2020 color space data.
  181. */
  182. static u16 DEGAMMA_2020[DEGAMMA_SIZE] = {
  183. 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
  184. 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
  185. 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
  186. 0x0000, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001,
  187. 0x0001, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0003, 0x0003,
  188. 0x0003, 0x0003, 0x0004, 0x0004, 0x0004, 0x0005, 0x0005, 0x0006,
  189. 0x0006, 0x0006, 0x0007, 0x0007, 0x0008, 0x0008, 0x0009, 0x000a,
  190. 0x000a, 0x000b, 0x000c, 0x000c, 0x000d, 0x000e, 0x000f, 0x000f,
  191. 0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0016, 0x0017, 0x0018,
  192. 0x0019, 0x001b, 0x001c, 0x001e, 0x001f, 0x0021, 0x0022, 0x0024,
  193. 0x0026, 0x0028, 0x002a, 0x002c, 0x002e, 0x0030, 0x0033, 0x0035,
  194. 0x0038, 0x003a, 0x003d, 0x0040, 0x0043, 0x0046, 0x0049, 0x004d,
  195. 0x0050, 0x0054, 0x0057, 0x005b, 0x005f, 0x0064, 0x0068, 0x006d,
  196. 0x0071, 0x0076, 0x007c, 0x0081, 0x0086, 0x008c, 0x0092, 0x0098,
  197. 0x009f, 0x00a5, 0x00ac, 0x00b4, 0x00bb, 0x00c3, 0x00cb, 0x00d3,
  198. 0x00dc, 0x00e5, 0x00ee, 0x00f8, 0x0102, 0x010c, 0x0117, 0x0123,
  199. 0x012e, 0x013a, 0x0147, 0x0154, 0x0161, 0x016f, 0x017e, 0x018d,
  200. 0x019c, 0x01ac, 0x01bd, 0x01ce, 0x01e0, 0x01f3, 0x0206, 0x021a,
  201. 0x022f, 0x0244, 0x025a, 0x0272, 0x0289, 0x02a2, 0x02bc, 0x02d6,
  202. 0x02f2, 0x030f, 0x032c, 0x034b, 0x036b, 0x038b, 0x03ae, 0x03d1,
  203. 0x03f5, 0x041b, 0x0443, 0x046b, 0x0495, 0x04c1, 0x04ee, 0x051d,
  204. 0x054e, 0x0580, 0x05b4, 0x05ea, 0x0622, 0x065c, 0x0698, 0x06d6,
  205. 0x0717, 0x075a, 0x079f, 0x07e7, 0x0831, 0x087e, 0x08cd, 0x0920,
  206. 0x0976, 0x09ce, 0x0a2a, 0x0a89, 0x0aec, 0x0b52, 0x0bbc, 0x0c2a,
  207. 0x0c9b, 0x0d11, 0x0d8b, 0x0e0a, 0x0e8d, 0x0f15, 0x0fa1, 0x1033,
  208. 0x10ca, 0x1167, 0x120a, 0x12b2, 0x1360, 0x1415, 0x14d1, 0x1593,
  209. 0x165d, 0x172e, 0x1806, 0x18e7, 0x19d0, 0x1ac1, 0x1bbb, 0x1cbf,
  210. 0x1dcc, 0x1ee3, 0x2005, 0x2131, 0x2268, 0x23ab, 0x24fa, 0x2656,
  211. 0x27be, 0x2934, 0x2ab8, 0x2c4a, 0x2dec, 0x2f9d, 0x315f, 0x3332,
  212. 0x3516, 0x370d, 0x3916, 0x3b34, 0x3d66, 0x3fad, 0x420b, 0x4480,
  213. 0x470d, 0x49b3, 0x4c73, 0x4f4e, 0x5246, 0x555a, 0x588e, 0x5be1,
  214. 0x5f55, 0x62eb, 0x66a6, 0x6a86, 0x6e8c, 0x72bb, 0x7714, 0x7b99,
  215. 0x3dcb, 0x3e60, 0x3ef5, 0x3f8c
  216. };
  217. /* one is for primary plane and the other is for all overlay planes */
  218. static const struct dc_hw_plane_reg dc_plane_reg[] = {
  219. {
  220. .y_address = DC_FRAMEBUFFER_ADDRESS,
  221. .u_address = DC_FRAMEBUFFER_U_ADDRESS,
  222. .v_address = DC_FRAMEBUFFER_V_ADDRESS,
  223. .y_stride = DC_FRAMEBUFFER_STRIDE,
  224. .u_stride = DC_FRAMEBUFFER_U_STRIDE,
  225. .v_stride = DC_FRAMEBUFFER_V_STRIDE,
  226. .size = DC_FRAMEBUFFER_SIZE,
  227. .top_left = DC_FRAMEBUFFER_TOP_LEFT,
  228. .bottom_right = DC_FRAMEBUFFER_BOTTOM_RIGHT,
  229. .scale_factor_x = DC_FRAMEBUFFER_SCALE_FACTOR_X,
  230. .scale_factor_y = DC_FRAMEBUFFER_SCALE_FACTOR_Y,
  231. .h_filter_coef_index = DC_FRAMEBUFFER_H_FILTER_COEF_INDEX,
  232. .h_filter_coef_data = DC_FRAMEBUFFER_H_FILTER_COEF_DATA,
  233. .v_filter_coef_index = DC_FRAMEBUFFER_V_FILTER_COEF_INDEX,
  234. .v_filter_coef_data = DC_FRAMEBUFFER_V_FILTER_COEF_DATA,
  235. .init_offset = DC_FRAMEBUFFER_INIT_OFFSET,
  236. .color_key = DC_FRAMEBUFFER_COLOR_KEY,
  237. .color_key_high = DC_FRAMEBUFFER_COLOR_KEY_HIGH,
  238. .clear_value = DC_FRAMEBUFFER_CLEAR_VALUE,
  239. .color_table_index = DC_FRAMEBUFFER_COLOR_TABLE_INDEX,
  240. .color_table_data = DC_FRAMEBUFFER_COLOR_TABLE_DATA,
  241. .scale_config = DC_FRAMEBUFFER_SCALE_CONFIG,
  242. .water_mark = DC_FRAMEBUFFER_WATER_MARK,
  243. .degamma_index = DC_FRAMEBUFFER_DEGAMMA_INDEX,
  244. .degamma_data = DC_FRAMEBUFFER_DEGAMMA_DATA,
  245. .degamma_ex_data = DC_FRAMEBUFFER_DEGAMMA_EX_DATA,
  246. .src_global_color = DC_FRAMEBUFFER_SRC_GLOBAL_COLOR,
  247. .dst_global_color = DC_FRAMEBUFFER_DST_GLOBAL_COLOR,
  248. .blend_config = DC_FRAMEBUFFER_BLEND_CONFIG,
  249. .roi_origin = DC_FRAMEBUFFER_ROI_ORIGIN,
  250. .roi_size = DC_FRAMEBUFFER_ROI_SIZE,
  251. .YUVToRGBCoef0 = DC_FRAMEBUFFER_YUVTORGB_COEF0,
  252. .YUVToRGBCoef1 = DC_FRAMEBUFFER_YUVTORGB_COEF1,
  253. .YUVToRGBCoef2 = DC_FRAMEBUFFER_YUVTORGB_COEF2,
  254. .YUVToRGBCoef3 = DC_FRAMEBUFFER_YUVTORGB_COEF3,
  255. .YUVToRGBCoef4 = DC_FRAMEBUFFER_YUVTORGB_COEF4,
  256. .YUVToRGBCoefD0 = DC_FRAMEBUFFER_YUVTORGB_COEFD0,
  257. .YUVToRGBCoefD1 = DC_FRAMEBUFFER_YUVTORGB_COEFD1,
  258. .YUVToRGBCoefD2 = DC_FRAMEBUFFER_YUVTORGB_COEFD2,
  259. .YClampBound = DC_FRAMEBUFFER_Y_CLAMP_BOUND,
  260. .UVClampBound = DC_FRAMEBUFFER_UV_CLAMP_BOUND,
  261. .RGBToRGBCoef0 = DC_FRAMEBUFFER_RGBTORGB_COEF0,
  262. .RGBToRGBCoef1 = DC_FRAMEBUFFER_RGBTORGB_COEF1,
  263. .RGBToRGBCoef2 = DC_FRAMEBUFFER_RGBTORGB_COEF2,
  264. .RGBToRGBCoef3 = DC_FRAMEBUFFER_RGBTORGB_COEF3,
  265. .RGBToRGBCoef4 = DC_FRAMEBUFFER_RGBTORGB_COEF4,
  266. },
  267. {
  268. .y_address = DC_OVERLAY_ADDRESS,
  269. .u_address = DC_OVERLAY_U_ADDRESS,
  270. .v_address = DC_OVERLAY_V_ADDRESS,
  271. .y_stride = DC_OVERLAY_STRIDE,
  272. .u_stride = DC_OVERLAY_U_STRIDE,
  273. .v_stride = DC_OVERLAY_V_STRIDE,
  274. .size = DC_OVERLAY_SIZE,
  275. .top_left = DC_OVERLAY_TOP_LEFT,
  276. .bottom_right = DC_OVERLAY_BOTTOM_RIGHT,
  277. .scale_factor_x = DC_OVERLAY_SCALE_FACTOR_X,
  278. .scale_factor_y = DC_OVERLAY_SCALE_FACTOR_Y,
  279. .h_filter_coef_index = DC_OVERLAY_H_FILTER_COEF_INDEX,
  280. .h_filter_coef_data = DC_OVERLAY_H_FILTER_COEF_DATA,
  281. .v_filter_coef_index = DC_OVERLAY_V_FILTER_COEF_INDEX,
  282. .v_filter_coef_data = DC_OVERLAY_V_FILTER_COEF_DATA,
  283. .init_offset = DC_OVERLAY_INIT_OFFSET,
  284. .color_key = DC_OVERLAY_COLOR_KEY,
  285. .color_key_high = DC_OVERLAY_COLOR_KEY_HIGH,
  286. .clear_value = DC_OVERLAY_CLEAR_VALUE,
  287. .color_table_index = DC_OVERLAY_COLOR_TABLE_INDEX,
  288. .color_table_data = DC_OVERLAY_COLOR_TABLE_DATA,
  289. .scale_config = DC_OVERLAY_SCALE_CONFIG,
  290. .water_mark = DC_OVERLAY_WATER_MARK,
  291. .degamma_index = DC_OVERLAY_DEGAMMA_INDEX,
  292. .degamma_data = DC_OVERLAY_DEGAMMA_DATA,
  293. .degamma_ex_data = DC_OVERLAY_DEGAMMA_EX_DATA,
  294. .src_global_color = DC_OVERLAY_SRC_GLOBAL_COLOR,
  295. .dst_global_color = DC_OVERLAY_DST_GLOBAL_COLOR,
  296. .blend_config = DC_OVERLAY_BLEND_CONFIG,
  297. .roi_origin = DC_OVERLAY_ROI_ORIGIN,
  298. .roi_size = DC_OVERLAY_ROI_SIZE,
  299. .YUVToRGBCoef0 = DC_OVERLAY_YUVTORGB_COEF0,
  300. .YUVToRGBCoef1 = DC_OVERLAY_YUVTORGB_COEF1,
  301. .YUVToRGBCoef2 = DC_OVERLAY_YUVTORGB_COEF2,
  302. .YUVToRGBCoef3 = DC_OVERLAY_YUVTORGB_COEF3,
  303. .YUVToRGBCoef4 = DC_OVERLAY_YUVTORGB_COEF4,
  304. .YUVToRGBCoefD0 = DC_OVERLAY_YUVTORGB_COEFD0,
  305. .YUVToRGBCoefD1 = DC_OVERLAY_YUVTORGB_COEFD1,
  306. .YUVToRGBCoefD2 = DC_OVERLAY_YUVTORGB_COEFD2,
  307. .YClampBound = DC_OVERLAY_Y_CLAMP_BOUND,
  308. .UVClampBound = DC_OVERLAY_UV_CLAMP_BOUND,
  309. .RGBToRGBCoef0 = DC_OVERLAY_RGBTORGB_COEF0,
  310. .RGBToRGBCoef1 = DC_OVERLAY_RGBTORGB_COEF1,
  311. .RGBToRGBCoef2 = DC_OVERLAY_RGBTORGB_COEF2,
  312. .RGBToRGBCoef3 = DC_OVERLAY_RGBTORGB_COEF3,
  313. .RGBToRGBCoef4 = DC_OVERLAY_RGBTORGB_COEF4,
  314. },
  315. };
  316. #ifdef CONFIG_VERISILICON_MMU
  317. static const u32 mmu_reg_base = SE_MMU_REG_BASE;
  318. static const struct dc_hw_mmu_reg dc_mmu_reg = {
  319. .mmu_config = SE_MMU_REG_CONFIG,
  320. .mmu_control = SE_MMU_REG_CONTROL,
  321. .table_array_size = SE_MMU_REG_TABLE_ARRAY_SIZE,
  322. .safe_non_secure = SE_MMU_REG_SAFE_NON_SECUR,
  323. .safe_secure = SE_MMU_REG_SAFE_SECURE,
  324. .safe_ex = SE_MMU_REG_SAFE_EXT_ADDRESS,
  325. .context_pd_entry = SE_MMU_REG_CONTEXT_PD,
  326. };
  327. #endif
  328. static const u32 primary_overlay_format0[] = {
  329. DRM_FORMAT_XRGB4444,
  330. DRM_FORMAT_XBGR4444,
  331. DRM_FORMAT_RGBX4444,
  332. DRM_FORMAT_BGRX4444,
  333. DRM_FORMAT_ARGB4444,
  334. DRM_FORMAT_ABGR4444,
  335. DRM_FORMAT_RGBA4444,
  336. DRM_FORMAT_BGRA4444,
  337. DRM_FORMAT_XRGB1555,
  338. DRM_FORMAT_XBGR1555,
  339. DRM_FORMAT_RGBX5551,
  340. DRM_FORMAT_BGRX5551,
  341. DRM_FORMAT_ARGB1555,
  342. DRM_FORMAT_ABGR1555,
  343. DRM_FORMAT_RGBA5551,
  344. DRM_FORMAT_BGRA5551,
  345. DRM_FORMAT_RGB565,
  346. DRM_FORMAT_BGR565,
  347. DRM_FORMAT_XRGB8888,
  348. DRM_FORMAT_XBGR8888,
  349. DRM_FORMAT_RGBX8888,
  350. DRM_FORMAT_BGRX8888,
  351. DRM_FORMAT_ARGB8888,
  352. DRM_FORMAT_ABGR8888,
  353. DRM_FORMAT_RGBA8888,
  354. DRM_FORMAT_BGRA8888,
  355. DRM_FORMAT_ARGB2101010,
  356. DRM_FORMAT_ABGR2101010,
  357. DRM_FORMAT_RGBA1010102,
  358. DRM_FORMAT_BGRA1010102,
  359. DRM_FORMAT_YUYV,
  360. DRM_FORMAT_YVYU,
  361. DRM_FORMAT_UYVY,
  362. DRM_FORMAT_VYUY,
  363. DRM_FORMAT_YVU420,
  364. DRM_FORMAT_YUV420,
  365. DRM_FORMAT_NV12,
  366. DRM_FORMAT_NV21,
  367. DRM_FORMAT_NV16,
  368. DRM_FORMAT_NV61,
  369. DRM_FORMAT_P010,
  370. };
  371. static const u32 primary_overlay_format1[] = {
  372. DRM_FORMAT_XRGB4444,
  373. DRM_FORMAT_XBGR4444,
  374. DRM_FORMAT_RGBX4444,
  375. DRM_FORMAT_BGRX4444,
  376. DRM_FORMAT_ARGB4444,
  377. DRM_FORMAT_ABGR4444,
  378. DRM_FORMAT_RGBA4444,
  379. DRM_FORMAT_BGRA4444,
  380. DRM_FORMAT_XRGB1555,
  381. DRM_FORMAT_XBGR1555,
  382. DRM_FORMAT_RGBX5551,
  383. DRM_FORMAT_BGRX5551,
  384. DRM_FORMAT_ARGB1555,
  385. DRM_FORMAT_ABGR1555,
  386. DRM_FORMAT_RGBA5551,
  387. DRM_FORMAT_BGRA5551,
  388. DRM_FORMAT_RGB565,
  389. DRM_FORMAT_BGR565,
  390. DRM_FORMAT_XRGB8888,
  391. DRM_FORMAT_XBGR8888,
  392. DRM_FORMAT_RGBX8888,
  393. DRM_FORMAT_BGRX8888,
  394. DRM_FORMAT_ARGB8888,
  395. DRM_FORMAT_ABGR8888,
  396. DRM_FORMAT_RGBA8888,
  397. DRM_FORMAT_BGRA8888,
  398. DRM_FORMAT_ARGB2101010,
  399. DRM_FORMAT_ABGR2101010,
  400. DRM_FORMAT_RGBA1010102,
  401. DRM_FORMAT_BGRA1010102,
  402. DRM_FORMAT_YUYV,
  403. DRM_FORMAT_YVYU,
  404. DRM_FORMAT_UYVY,
  405. DRM_FORMAT_VYUY,
  406. DRM_FORMAT_YVU420,
  407. DRM_FORMAT_YUV420,
  408. DRM_FORMAT_NV12,
  409. DRM_FORMAT_NV21,
  410. DRM_FORMAT_NV16,
  411. DRM_FORMAT_NV61,
  412. DRM_FORMAT_P010,
  413. DRM_FORMAT_YUV444,
  414. };
  415. static const u32 cursor_formats[] = {
  416. DRM_FORMAT_ARGB8888
  417. };
  418. static const u64 format_modifier0[] = {
  419. DRM_FORMAT_MOD_LINEAR,
  420. fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_LINEAR),
  421. fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_SUPER_TILED_XMAJOR),
  422. fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_SUPER_TILED_YMAJOR),
  423. fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_TILE_8X8),
  424. fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_TILE_8X4),
  425. fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_SUPER_TILED_XMAJOR_8X4),
  426. fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_SUPER_TILED_YMAJOR_4X8),
  427. #ifdef CONFIG_VERISILICON_DEC
  428. fourcc_mod_vs_dec_code(DRM_FORMAT_MOD_VS_DEC_TILE_8X8_XMAJOR,
  429. DRM_FORMAT_MOD_VS_DEC_ALIGN_32),
  430. fourcc_mod_vs_dec_code(DRM_FORMAT_MOD_VS_DEC_TILE_8X4,
  431. DRM_FORMAT_MOD_VS_DEC_ALIGN_32),
  432. fourcc_mod_vs_dec_code(DRM_FORMAT_MOD_VS_DEC_TILE_4X8,
  433. DRM_FORMAT_MOD_VS_DEC_ALIGN_32),
  434. fourcc_mod_vs_dec_code(DRM_FORMAT_MOD_VS_DEC_RASTER_256X1,
  435. DRM_FORMAT_MOD_VS_DEC_ALIGN_32),
  436. fourcc_mod_vs_dec_code(DRM_FORMAT_MOD_VS_DEC_RASTER_128X1,
  437. DRM_FORMAT_MOD_VS_DEC_ALIGN_32),
  438. fourcc_mod_vs_dec_code(DRM_FORMAT_MOD_VS_DEC_RASTER_64X1,
  439. DRM_FORMAT_MOD_VS_DEC_ALIGN_32),
  440. fourcc_mod_vs_dec_code(DRM_FORMAT_MOD_VS_DEC_TILE_16X8,
  441. DRM_FORMAT_MOD_VS_DEC_ALIGN_32),
  442. fourcc_mod_vs_dec_code(DRM_FORMAT_MOD_VS_DEC_RASTER_32X1,
  443. DRM_FORMAT_MOD_VS_DEC_ALIGN_32),
  444. fourcc_mod_vs_dec_code(DRM_FORMAT_MOD_VS_DEC_TILE_32X8,
  445. DRM_FORMAT_MOD_VS_DEC_ALIGN_32),
  446. #endif
  447. DRM_FORMAT_MOD_INVALID
  448. };
  449. static const u64 format_modifier1[] = {
  450. DRM_FORMAT_MOD_LINEAR,
  451. fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_LINEAR),
  452. fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_SUPER_TILED_XMAJOR),
  453. fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_SUPER_TILED_YMAJOR),
  454. fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_TILE_8X8),
  455. fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_TILE_8X4),
  456. fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_SUPER_TILED_XMAJOR_8X4),
  457. fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_SUPER_TILED_YMAJOR_4X8),
  458. fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_TILE_MODE4X4),
  459. fourcc_mod_vs_custom_code(DRM_FORMAT_MOD_VS_TILE_MODE4X4),
  460. DRM_FORMAT_MOD_INVALID
  461. };
  462. static const u64 secondary_format_modifiers[] = {
  463. DRM_FORMAT_MOD_LINEAR,
  464. #ifdef CONFIG_VERISILICON_DEC
  465. fourcc_mod_vs_dec_code(DRM_FORMAT_MOD_VS_DEC_RASTER_256X1,
  466. DRM_FORMAT_MOD_VS_DEC_ALIGN_32),
  467. fourcc_mod_vs_dec_code(DRM_FORMAT_MOD_VS_DEC_RASTER_128X1,
  468. DRM_FORMAT_MOD_VS_DEC_ALIGN_32),
  469. fourcc_mod_vs_dec_code(DRM_FORMAT_MOD_VS_DEC_RASTER_64X1,
  470. DRM_FORMAT_MOD_VS_DEC_ALIGN_32),
  471. fourcc_mod_vs_dec_code(DRM_FORMAT_MOD_VS_DEC_RASTER_32X1,
  472. DRM_FORMAT_MOD_VS_DEC_ALIGN_32),
  473. #endif
  474. DRM_FORMAT_MOD_INVALID
  475. };
  476. #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
  477. static const struct vs_plane_info dc_hw_planes[][PLANE_NUM] = {
  478. {
  479. /* DC_REV_0 */
  480. {
  481. .name = "Primary",
  482. .id = PRIMARY_PLANE_0,
  483. .type = DRM_PLANE_TYPE_PRIMARY,
  484. .num_formats = ARRAY_SIZE(primary_overlay_format0),
  485. .formats = primary_overlay_format0,
  486. .num_modifiers = ARRAY_SIZE(format_modifier0),
  487. .modifiers = format_modifier0,
  488. .min_width = 0,
  489. .min_height = 0,
  490. .max_width = 4096,
  491. .max_height = 4096,
  492. .rotation = DRM_MODE_ROTATE_0 |
  493. DRM_MODE_ROTATE_90 |
  494. DRM_MODE_ROTATE_180 |
  495. DRM_MODE_ROTATE_270 |
  496. DRM_MODE_REFLECT_X |
  497. DRM_MODE_REFLECT_Y,
  498. .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
  499. BIT(DRM_MODE_BLEND_PREMULTI) |
  500. BIT(DRM_MODE_BLEND_COVERAGE),
  501. .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) |
  502. BIT(DRM_COLOR_YCBCR_BT2020),
  503. .degamma_size = DEGAMMA_SIZE,
  504. .min_scale = FRAC_16_16(1, 3),
  505. .max_scale = FRAC_16_16(10, 1),
  506. .zpos = 0,
  507. .watermark = true,
  508. .color_mgmt = true,
  509. .roi = true,
  510. },
  511. {
  512. .name = "Overlay",
  513. .id = OVERLAY_PLANE_0,
  514. .type = DRM_PLANE_TYPE_OVERLAY,
  515. .num_formats = ARRAY_SIZE(primary_overlay_format0),
  516. .formats = primary_overlay_format0,
  517. .num_modifiers = ARRAY_SIZE(format_modifier0),
  518. .modifiers = format_modifier0,
  519. .min_width = 0,
  520. .min_height = 0,
  521. .max_width = 4096,
  522. .max_height = 4096,
  523. .rotation = DRM_MODE_ROTATE_0 |
  524. DRM_MODE_ROTATE_90 |
  525. DRM_MODE_ROTATE_180 |
  526. DRM_MODE_ROTATE_270 |
  527. DRM_MODE_REFLECT_X |
  528. DRM_MODE_REFLECT_Y,
  529. .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
  530. BIT(DRM_MODE_BLEND_PREMULTI) |
  531. BIT(DRM_MODE_BLEND_COVERAGE),
  532. .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) |
  533. BIT(DRM_COLOR_YCBCR_BT2020),
  534. .degamma_size = DEGAMMA_SIZE,
  535. .min_scale = FRAC_16_16(1, 3),
  536. .max_scale = FRAC_16_16(10, 1),
  537. .zpos = 1,
  538. .watermark = true,
  539. .color_mgmt = true,
  540. .roi = true,
  541. },
  542. {
  543. .name = "Overlay_1",
  544. .id = OVERLAY_PLANE_1,
  545. .type = DRM_PLANE_TYPE_OVERLAY,
  546. .num_formats = ARRAY_SIZE(primary_overlay_format0),
  547. .formats = primary_overlay_format0,
  548. .num_modifiers = ARRAY_SIZE(secondary_format_modifiers),
  549. .modifiers = secondary_format_modifiers,
  550. .min_width = 0,
  551. .min_height = 0,
  552. .max_width = 4096,
  553. .max_height = 4096,
  554. .rotation = 0,
  555. .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
  556. BIT(DRM_MODE_BLEND_PREMULTI) |
  557. BIT(DRM_MODE_BLEND_COVERAGE),
  558. .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) |
  559. BIT(DRM_COLOR_YCBCR_BT2020),
  560. .degamma_size = DEGAMMA_SIZE,
  561. .min_scale = DRM_PLANE_HELPER_NO_SCALING,
  562. .max_scale = DRM_PLANE_HELPER_NO_SCALING,
  563. .zpos = 2,
  564. .watermark = true,
  565. .color_mgmt = true,
  566. .roi = true,
  567. },
  568. {
  569. .name = "Primary_1",
  570. .id = PRIMARY_PLANE_1,
  571. .type = DRM_PLANE_TYPE_PRIMARY,
  572. .num_formats = ARRAY_SIZE(primary_overlay_format0),
  573. .formats = primary_overlay_format0,
  574. .num_modifiers = ARRAY_SIZE(format_modifier0),
  575. .modifiers = format_modifier0,
  576. .min_width = 0,
  577. .min_height = 0,
  578. .max_width = 4096,
  579. .max_height = 4096,
  580. .rotation = DRM_MODE_ROTATE_0 |
  581. DRM_MODE_ROTATE_90 |
  582. DRM_MODE_ROTATE_180 |
  583. DRM_MODE_ROTATE_270 |
  584. DRM_MODE_REFLECT_X |
  585. DRM_MODE_REFLECT_Y,
  586. .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
  587. BIT(DRM_MODE_BLEND_PREMULTI) |
  588. BIT(DRM_MODE_BLEND_COVERAGE),
  589. .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) |
  590. BIT(DRM_COLOR_YCBCR_BT2020),
  591. .degamma_size = DEGAMMA_SIZE,
  592. .min_scale = FRAC_16_16(1, 3),
  593. .max_scale = FRAC_16_16(10, 1),
  594. .zpos = 3,
  595. .watermark = true,
  596. .color_mgmt = true,
  597. .roi = true,
  598. },
  599. {
  600. .name = "Overlay_2",
  601. .id = OVERLAY_PLANE_2,
  602. .type = DRM_PLANE_TYPE_OVERLAY,
  603. .num_formats = ARRAY_SIZE(primary_overlay_format0),
  604. .formats = primary_overlay_format0,
  605. .num_modifiers = ARRAY_SIZE(format_modifier0),
  606. .modifiers = format_modifier0,
  607. .min_width = 0,
  608. .min_height = 0,
  609. .max_width = 4096,
  610. .max_height = 4096,
  611. .rotation = DRM_MODE_ROTATE_0 |
  612. DRM_MODE_ROTATE_90 |
  613. DRM_MODE_ROTATE_180 |
  614. DRM_MODE_ROTATE_270 |
  615. DRM_MODE_REFLECT_X |
  616. DRM_MODE_REFLECT_Y,
  617. .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
  618. BIT(DRM_MODE_BLEND_PREMULTI) |
  619. BIT(DRM_MODE_BLEND_COVERAGE),
  620. .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) |
  621. BIT(DRM_COLOR_YCBCR_BT2020),
  622. .degamma_size = DEGAMMA_SIZE,
  623. .min_scale = FRAC_16_16(1, 3),
  624. .max_scale = FRAC_16_16(10, 1),
  625. .zpos = 4,
  626. .watermark = true,
  627. .color_mgmt = true,
  628. .roi = true,
  629. },
  630. {
  631. .name = "Overlay_3",
  632. .id = OVERLAY_PLANE_3,
  633. .type = DRM_PLANE_TYPE_OVERLAY,
  634. .num_formats = ARRAY_SIZE(primary_overlay_format0),
  635. .formats = primary_overlay_format0,
  636. .num_modifiers = ARRAY_SIZE(secondary_format_modifiers),
  637. .modifiers = secondary_format_modifiers,
  638. .min_width = 0,
  639. .min_height = 0,
  640. .max_width = 4096,
  641. .max_height = 4096,
  642. .rotation = 0,
  643. .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
  644. BIT(DRM_MODE_BLEND_PREMULTI) |
  645. BIT(DRM_MODE_BLEND_COVERAGE),
  646. .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) |
  647. BIT(DRM_COLOR_YCBCR_BT2020),
  648. .degamma_size = DEGAMMA_SIZE,
  649. .min_scale = DRM_PLANE_HELPER_NO_SCALING,
  650. .max_scale = DRM_PLANE_HELPER_NO_SCALING,
  651. .zpos = 5,
  652. .watermark = true,
  653. .color_mgmt = true,
  654. .roi = true,
  655. },
  656. {
  657. .name = "Cursor",
  658. .id = CURSOR_PLANE_0,
  659. .type = DRM_PLANE_TYPE_CURSOR,
  660. .num_formats = ARRAY_SIZE(cursor_formats),
  661. .formats = cursor_formats,
  662. .num_modifiers = 0,
  663. .modifiers = NULL,
  664. .min_width = 32,
  665. .min_height = 32,
  666. .max_width = 64,
  667. .max_height = 64,
  668. .rotation = 0,
  669. .degamma_size = 0,
  670. .min_scale = DRM_PLANE_HELPER_NO_SCALING,
  671. .max_scale = DRM_PLANE_HELPER_NO_SCALING,
  672. .zpos = 255,
  673. .watermark = false,
  674. .color_mgmt = false,
  675. .roi = false,
  676. },
  677. {
  678. .name = "Cursor_1",
  679. .id = CURSOR_PLANE_1,
  680. .type = DRM_PLANE_TYPE_CURSOR,
  681. .num_formats = ARRAY_SIZE(cursor_formats),
  682. .formats = cursor_formats,
  683. .num_modifiers = 0,
  684. .modifiers = NULL,
  685. .min_width = 32,
  686. .min_height = 32,
  687. .max_width = 64,
  688. .max_height = 64,
  689. .rotation = 0,
  690. .degamma_size = 0,
  691. .min_scale = DRM_PLANE_HELPER_NO_SCALING,
  692. .max_scale = DRM_PLANE_HELPER_NO_SCALING,
  693. .zpos = 255,
  694. .watermark = false,
  695. .color_mgmt = false,
  696. .roi = false,
  697. },
  698. },
  699. {
  700. /* DC_REV_1 */
  701. {
  702. .name = "Primary",
  703. .id = PRIMARY_PLANE_0,
  704. .type = DRM_PLANE_TYPE_PRIMARY,
  705. .num_formats = ARRAY_SIZE(primary_overlay_format0),
  706. .formats = primary_overlay_format0,
  707. .num_modifiers = ARRAY_SIZE(format_modifier0),
  708. .modifiers = format_modifier0,
  709. .min_width = 0,
  710. .min_height = 0,
  711. .max_width = 4096,
  712. .max_height = 4096,
  713. .rotation = DRM_MODE_ROTATE_0 |
  714. DRM_MODE_ROTATE_90 |
  715. DRM_MODE_ROTATE_180 |
  716. DRM_MODE_ROTATE_270 |
  717. DRM_MODE_REFLECT_X |
  718. DRM_MODE_REFLECT_Y,
  719. .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
  720. BIT(DRM_MODE_BLEND_PREMULTI) |
  721. BIT(DRM_MODE_BLEND_COVERAGE),
  722. .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) |
  723. BIT(DRM_COLOR_YCBCR_BT2020),
  724. .degamma_size = DEGAMMA_SIZE,
  725. .min_scale = FRAC_16_16(1, 3),
  726. .max_scale = FRAC_16_16(10, 1),
  727. .zpos = 0,
  728. .watermark = true,
  729. .color_mgmt = true,
  730. .roi = true,
  731. },
  732. {
  733. .name = "Overlay",
  734. .id = OVERLAY_PLANE_0,
  735. .type = DRM_PLANE_TYPE_OVERLAY,
  736. .num_formats = ARRAY_SIZE(primary_overlay_format0),
  737. .formats = primary_overlay_format0,
  738. .num_modifiers = ARRAY_SIZE(format_modifier0),
  739. .modifiers = format_modifier0,
  740. .min_width = 0,
  741. .min_height = 0,
  742. .max_width = 4096,
  743. .max_height = 4096,
  744. .rotation = DRM_MODE_ROTATE_0 |
  745. DRM_MODE_ROTATE_90 |
  746. DRM_MODE_ROTATE_180 |
  747. DRM_MODE_ROTATE_270 |
  748. DRM_MODE_REFLECT_X |
  749. DRM_MODE_REFLECT_Y,
  750. .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
  751. BIT(DRM_MODE_BLEND_PREMULTI) |
  752. BIT(DRM_MODE_BLEND_COVERAGE),
  753. .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) |
  754. BIT(DRM_COLOR_YCBCR_BT2020),
  755. .degamma_size = DEGAMMA_SIZE,
  756. .min_scale = FRAC_16_16(1, 3),
  757. .max_scale = FRAC_16_16(10, 1),
  758. .zpos = 1,
  759. .watermark = true,
  760. .color_mgmt = true,
  761. .roi = true,
  762. },
  763. {
  764. .name = "Primary_1",
  765. .id = PRIMARY_PLANE_1,
  766. .type = DRM_PLANE_TYPE_PRIMARY,
  767. .num_formats = ARRAY_SIZE(primary_overlay_format0),
  768. .formats = primary_overlay_format0,
  769. .num_modifiers = ARRAY_SIZE(format_modifier0),
  770. .modifiers = format_modifier0,
  771. .min_width = 0,
  772. .min_height = 0,
  773. .max_width = 4096,
  774. .max_height = 4096,
  775. .rotation = DRM_MODE_ROTATE_0 |
  776. DRM_MODE_ROTATE_90 |
  777. DRM_MODE_ROTATE_180 |
  778. DRM_MODE_ROTATE_270 |
  779. DRM_MODE_REFLECT_X |
  780. DRM_MODE_REFLECT_Y,
  781. .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
  782. BIT(DRM_MODE_BLEND_PREMULTI) |
  783. BIT(DRM_MODE_BLEND_COVERAGE),
  784. .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) |
  785. BIT(DRM_COLOR_YCBCR_BT2020),
  786. .degamma_size = DEGAMMA_SIZE,
  787. .min_scale = FRAC_16_16(1, 3),
  788. .max_scale = FRAC_16_16(10, 1),
  789. .zpos = 2,
  790. .watermark = true,
  791. .color_mgmt = true,
  792. .roi = true,
  793. },
  794. {
  795. .name = "Overlay_2",
  796. .id = OVERLAY_PLANE_2,
  797. .type = DRM_PLANE_TYPE_OVERLAY,
  798. .num_formats = ARRAY_SIZE(primary_overlay_format0),
  799. .formats = primary_overlay_format0,
  800. .num_modifiers = ARRAY_SIZE(format_modifier0),
  801. .modifiers = format_modifier0,
  802. .min_width = 0,
  803. .min_height = 0,
  804. .max_width = 4096,
  805. .max_height = 4096,
  806. .rotation = DRM_MODE_ROTATE_0 |
  807. DRM_MODE_ROTATE_90 |
  808. DRM_MODE_ROTATE_180 |
  809. DRM_MODE_ROTATE_270 |
  810. DRM_MODE_REFLECT_X |
  811. DRM_MODE_REFLECT_Y,
  812. .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
  813. BIT(DRM_MODE_BLEND_PREMULTI) |
  814. BIT(DRM_MODE_BLEND_COVERAGE),
  815. .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) |
  816. BIT(DRM_COLOR_YCBCR_BT2020),
  817. .degamma_size = DEGAMMA_SIZE,
  818. .min_scale = FRAC_16_16(1, 3),
  819. .max_scale = FRAC_16_16(10, 1),
  820. .zpos = 3,
  821. .watermark = true,
  822. .color_mgmt = true,
  823. .roi = true,
  824. },
  825. {
  826. .name = "Cursor",
  827. .id = CURSOR_PLANE_0,
  828. .type = DRM_PLANE_TYPE_CURSOR,
  829. .num_formats = ARRAY_SIZE(cursor_formats),
  830. .formats = cursor_formats,
  831. .num_modifiers = 0,
  832. .modifiers = NULL,
  833. .min_width = 32,
  834. .min_height = 32,
  835. .max_width = 64,
  836. .max_height = 64,
  837. .rotation = 0,
  838. .degamma_size = 0,
  839. .min_scale = DRM_PLANE_HELPER_NO_SCALING,
  840. .max_scale = DRM_PLANE_HELPER_NO_SCALING,
  841. .zpos = 255,
  842. .watermark = false,
  843. .color_mgmt = false,
  844. .roi = false,
  845. },
  846. {
  847. .name = "Cursor_1",
  848. .id = CURSOR_PLANE_1,
  849. .type = DRM_PLANE_TYPE_CURSOR,
  850. .num_formats = ARRAY_SIZE(cursor_formats),
  851. .formats = cursor_formats,
  852. .num_modifiers = 0,
  853. .modifiers = NULL,
  854. .min_width = 32,
  855. .min_height = 32,
  856. .max_width = 64,
  857. .max_height = 64,
  858. .rotation = 0,
  859. .degamma_size = 0,
  860. .min_scale = DRM_PLANE_HELPER_NO_SCALING,
  861. .max_scale = DRM_PLANE_HELPER_NO_SCALING,
  862. .zpos = 255,
  863. .watermark = false,
  864. .color_mgmt = false,
  865. .roi = false,
  866. },
  867. },
  868. {
  869. /* DC_REV_2 */
  870. {
  871. .name = "Primary",
  872. .id = PRIMARY_PLANE_0,
  873. .type = DRM_PLANE_TYPE_PRIMARY,
  874. .num_formats = ARRAY_SIZE(primary_overlay_format1),
  875. .formats = primary_overlay_format1,
  876. .num_modifiers = ARRAY_SIZE(format_modifier1),
  877. .modifiers = format_modifier1,
  878. .min_width = 0,
  879. .min_height = 0,
  880. .max_width = 4096,
  881. .max_height = 4096,
  882. .rotation = DRM_MODE_ROTATE_0 |
  883. DRM_MODE_ROTATE_90 |
  884. DRM_MODE_ROTATE_180 |
  885. DRM_MODE_ROTATE_270 |
  886. DRM_MODE_REFLECT_X |
  887. DRM_MODE_REFLECT_Y,
  888. .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
  889. BIT(DRM_MODE_BLEND_PREMULTI) |
  890. BIT(DRM_MODE_BLEND_COVERAGE),
  891. .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) |
  892. BIT(DRM_COLOR_YCBCR_BT2020),
  893. .degamma_size = DEGAMMA_SIZE,
  894. .min_scale = FRAC_16_16(1, 3),
  895. .max_scale = FRAC_16_16(10, 1),
  896. .zpos = 0,
  897. .watermark = true,
  898. .color_mgmt = true,
  899. .roi = true,
  900. },
  901. {
  902. .name = "Overlay",
  903. .id = OVERLAY_PLANE_0,
  904. .type = DRM_PLANE_TYPE_OVERLAY,
  905. .num_formats = ARRAY_SIZE(primary_overlay_format1),
  906. .formats = primary_overlay_format1,
  907. .num_modifiers = ARRAY_SIZE(format_modifier1),
  908. .modifiers = format_modifier1,
  909. .min_width = 0,
  910. .min_height = 0,
  911. .max_width = 4096,
  912. .max_height = 4096,
  913. .rotation = DRM_MODE_ROTATE_0 |
  914. DRM_MODE_ROTATE_90 |
  915. DRM_MODE_ROTATE_180 |
  916. DRM_MODE_ROTATE_270 |
  917. DRM_MODE_REFLECT_X |
  918. DRM_MODE_REFLECT_Y,
  919. .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
  920. BIT(DRM_MODE_BLEND_PREMULTI) |
  921. BIT(DRM_MODE_BLEND_COVERAGE),
  922. .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) |
  923. BIT(DRM_COLOR_YCBCR_BT2020),
  924. .degamma_size = DEGAMMA_SIZE,
  925. .min_scale = FRAC_16_16(1, 3),
  926. .max_scale = FRAC_16_16(10, 1),
  927. .zpos = 1,
  928. .watermark = true,
  929. .color_mgmt = true,
  930. .roi = true,
  931. },
  932. {
  933. .name = "Overlay_1",
  934. .id = OVERLAY_PLANE_1,
  935. .type = DRM_PLANE_TYPE_OVERLAY,
  936. .num_formats = ARRAY_SIZE(primary_overlay_format1),
  937. .formats = primary_overlay_format1,
  938. .num_modifiers = ARRAY_SIZE(secondary_format_modifiers),
  939. .modifiers = secondary_format_modifiers,
  940. .min_width = 0,
  941. .min_height = 0,
  942. .max_width = 4096,
  943. .max_height = 4096,
  944. .rotation = 0,
  945. .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
  946. BIT(DRM_MODE_BLEND_PREMULTI) |
  947. BIT(DRM_MODE_BLEND_COVERAGE),
  948. .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) |
  949. BIT(DRM_COLOR_YCBCR_BT2020),
  950. .degamma_size = DEGAMMA_SIZE,
  951. .min_scale = DRM_PLANE_HELPER_NO_SCALING,
  952. .max_scale = DRM_PLANE_HELPER_NO_SCALING,
  953. .zpos = 2,
  954. .watermark = true,
  955. .color_mgmt = true,
  956. .roi = true,
  957. },
  958. {
  959. .name = "Primary_1",
  960. .id = PRIMARY_PLANE_1,
  961. .type = DRM_PLANE_TYPE_PRIMARY,
  962. .num_formats = ARRAY_SIZE(primary_overlay_format1),
  963. .formats = primary_overlay_format1,
  964. .num_modifiers = ARRAY_SIZE(format_modifier1),
  965. .modifiers = format_modifier1,
  966. .min_width = 0,
  967. .min_height = 0,
  968. .max_width = 4096,
  969. .max_height = 4096,
  970. .rotation = DRM_MODE_ROTATE_0 |
  971. DRM_MODE_ROTATE_90 |
  972. DRM_MODE_ROTATE_180 |
  973. DRM_MODE_ROTATE_270 |
  974. DRM_MODE_REFLECT_X |
  975. DRM_MODE_REFLECT_Y,
  976. .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
  977. BIT(DRM_MODE_BLEND_PREMULTI) |
  978. BIT(DRM_MODE_BLEND_COVERAGE),
  979. .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) |
  980. BIT(DRM_COLOR_YCBCR_BT2020),
  981. .degamma_size = DEGAMMA_SIZE,
  982. .min_scale = FRAC_16_16(1, 3),
  983. .max_scale = FRAC_16_16(10, 1),
  984. .zpos = 3,
  985. .watermark = true,
  986. .color_mgmt = true,
  987. .roi = true,
  988. },
  989. {
  990. .name = "Overlay_2",
  991. .id = OVERLAY_PLANE_2,
  992. .type = DRM_PLANE_TYPE_OVERLAY,
  993. .num_formats = ARRAY_SIZE(primary_overlay_format1),
  994. .formats = primary_overlay_format1,
  995. .num_modifiers = ARRAY_SIZE(format_modifier1),
  996. .modifiers = format_modifier1,
  997. .min_width = 0,
  998. .min_height = 0,
  999. .max_width = 4096,
  1000. .max_height = 4096,
  1001. .rotation = DRM_MODE_ROTATE_0 |
  1002. DRM_MODE_ROTATE_90 |
  1003. DRM_MODE_ROTATE_180 |
  1004. DRM_MODE_ROTATE_270 |
  1005. DRM_MODE_REFLECT_X |
  1006. DRM_MODE_REFLECT_Y,
  1007. .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
  1008. BIT(DRM_MODE_BLEND_PREMULTI) |
  1009. BIT(DRM_MODE_BLEND_COVERAGE),
  1010. .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) |
  1011. BIT(DRM_COLOR_YCBCR_BT2020),
  1012. .degamma_size = DEGAMMA_SIZE,
  1013. .min_scale = FRAC_16_16(1, 3),
  1014. .max_scale = FRAC_16_16(10, 1),
  1015. .zpos = 4,
  1016. .watermark = true,
  1017. .color_mgmt = true,
  1018. .roi = true,
  1019. },
  1020. {
  1021. .name = "Overlay_3",
  1022. .id = OVERLAY_PLANE_3,
  1023. .type = DRM_PLANE_TYPE_OVERLAY,
  1024. .num_formats = ARRAY_SIZE(primary_overlay_format1),
  1025. .formats = primary_overlay_format1,
  1026. .num_modifiers = ARRAY_SIZE(secondary_format_modifiers),
  1027. .modifiers = secondary_format_modifiers,
  1028. .min_width = 0,
  1029. .min_height = 0,
  1030. .max_width = 4096,
  1031. .max_height = 4096,
  1032. .rotation = 0,
  1033. .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
  1034. BIT(DRM_MODE_BLEND_PREMULTI) |
  1035. BIT(DRM_MODE_BLEND_COVERAGE),
  1036. .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) |
  1037. BIT(DRM_COLOR_YCBCR_BT2020),
  1038. .degamma_size = DEGAMMA_SIZE,
  1039. .min_scale = DRM_PLANE_HELPER_NO_SCALING,
  1040. .max_scale = DRM_PLANE_HELPER_NO_SCALING,
  1041. .zpos = 5,
  1042. .watermark = true,
  1043. .color_mgmt = true,
  1044. .roi = true,
  1045. },
  1046. {
  1047. .name = "Cursor",
  1048. .id = CURSOR_PLANE_0,
  1049. .type = DRM_PLANE_TYPE_CURSOR,
  1050. .num_formats = ARRAY_SIZE(cursor_formats),
  1051. .formats = cursor_formats,
  1052. .num_modifiers = 0,
  1053. .modifiers = NULL,
  1054. .min_width = 32,
  1055. .min_height = 32,
  1056. .max_width = 64,
  1057. .max_height = 64,
  1058. .rotation = 0,
  1059. .degamma_size = 0,
  1060. .min_scale = DRM_PLANE_HELPER_NO_SCALING,
  1061. .max_scale = DRM_PLANE_HELPER_NO_SCALING,
  1062. .zpos = 255,
  1063. .watermark = false,
  1064. .color_mgmt = false,
  1065. .roi = false,
  1066. },
  1067. {
  1068. .name = "Cursor_1",
  1069. .id = CURSOR_PLANE_1,
  1070. .type = DRM_PLANE_TYPE_CURSOR,
  1071. .num_formats = ARRAY_SIZE(cursor_formats),
  1072. .formats = cursor_formats,
  1073. .num_modifiers = 0,
  1074. .modifiers = NULL,
  1075. .min_width = 32,
  1076. .min_height = 32,
  1077. .max_width = 64,
  1078. .max_height = 64,
  1079. .rotation = 0,
  1080. .degamma_size = 0,
  1081. .min_scale = DRM_PLANE_HELPER_NO_SCALING,
  1082. .max_scale = DRM_PLANE_HELPER_NO_SCALING,
  1083. .zpos = 255,
  1084. .watermark = false,
  1085. .color_mgmt = false,
  1086. .roi = false,
  1087. },
  1088. },
  1089. };
  1090. static const struct vs_dc_info dc_info[] = {
  1091. {
  1092. /* DC_REV_0 */
  1093. .name = "DC8200",
  1094. .panel_num = 2,
  1095. .plane_num = 8,
  1096. .planes = dc_hw_planes[DC_REV_0],
  1097. .layer_num = 6,
  1098. .max_bpc = 10,
  1099. .color_formats = DRM_COLOR_FORMAT_RGB444 |
  1100. DRM_COLOR_FORMAT_YCRCB444 |
  1101. DRM_COLOR_FORMAT_YCRCB422 |
  1102. DRM_COLOR_FORMAT_YCRCB420,
  1103. .gamma_size = GAMMA_EX_SIZE,
  1104. .gamma_bits = 12,
  1105. .pitch_alignment = 128,
  1106. .pipe_sync = false,
  1107. .mmu_prefetch = false,
  1108. .background = true,
  1109. .panel_sync = true,
  1110. .cap_dec = true,
  1111. },
  1112. {
  1113. /* DC_REV_1 */
  1114. .name = "DC8200",
  1115. .panel_num = 2,
  1116. .plane_num = 6,
  1117. .planes = dc_hw_planes[DC_REV_1],
  1118. .layer_num = 4,
  1119. .max_bpc = 10,
  1120. .color_formats = DRM_COLOR_FORMAT_RGB444 |
  1121. DRM_COLOR_FORMAT_YCRCB444 |
  1122. DRM_COLOR_FORMAT_YCRCB422 |
  1123. DRM_COLOR_FORMAT_YCRCB420,
  1124. .gamma_size = GAMMA_EX_SIZE,
  1125. .gamma_bits = 12,
  1126. .pitch_alignment = 128,
  1127. .pipe_sync = false,
  1128. .mmu_prefetch = false,
  1129. .background = true,
  1130. .panel_sync = true,
  1131. .cap_dec = true,
  1132. },
  1133. {
  1134. /* DC_REV_2 */
  1135. .name = "DC8200",
  1136. .panel_num = 2,
  1137. .plane_num = 8,
  1138. .planes = dc_hw_planes[DC_REV_1],
  1139. .layer_num = 6,
  1140. .max_bpc = 10,
  1141. .color_formats = DRM_COLOR_FORMAT_RGB444 |
  1142. DRM_COLOR_FORMAT_YCRCB444 |
  1143. DRM_COLOR_FORMAT_YCRCB422 |
  1144. DRM_COLOR_FORMAT_YCRCB420,
  1145. .gamma_size = GAMMA_EX_SIZE,
  1146. .gamma_bits = 12,
  1147. .pitch_alignment = 128,
  1148. .pipe_sync = false,
  1149. .mmu_prefetch = false,
  1150. .background = true,
  1151. .panel_sync = true,
  1152. .cap_dec = false,
  1153. },
  1154. };
  1155. static const struct dc_hw_funcs hw_func;
  1156. static inline u32 hi_read(struct dc_hw *hw, u32 reg)
  1157. {
  1158. return readl(hw->hi_base + reg);
  1159. }
  1160. static inline void hi_write(struct dc_hw *hw, u32 reg, u32 value)
  1161. {
  1162. writel(value, hw->hi_base + reg);
  1163. }
  1164. static inline void dc_write(struct dc_hw *hw, u32 reg, u32 value)
  1165. {
  1166. writel(value, hw->reg_base + reg - DC_REG_BASE);
  1167. }
  1168. static inline u32 dc_read(struct dc_hw *hw, u32 reg)
  1169. {
  1170. u32 value = readl(hw->reg_base + reg - DC_REG_BASE);
  1171. return value;
  1172. }
  1173. static inline void dc_set_clear(struct dc_hw *hw, u32 reg, u32 set, u32 clear)
  1174. {
  1175. u32 value = dc_read(hw, reg);
  1176. value &= ~clear;
  1177. value |= set;
  1178. dc_write(hw, reg, value);
  1179. }
  1180. static void load_default_filter(struct dc_hw *hw,
  1181. const struct dc_hw_plane_reg *reg, u32 offset)
  1182. {
  1183. u8 i;
  1184. dc_write(hw, reg->scale_config + offset, 0x33);
  1185. dc_write(hw, reg->init_offset + offset, 0x80008000);
  1186. dc_write(hw, reg->h_filter_coef_index + offset, 0x00);
  1187. for (i = 0; i < H_COEF_SIZE; i++)
  1188. dc_write(hw, reg->h_filter_coef_data + offset, horKernel[i]);
  1189. dc_write(hw, reg->v_filter_coef_index + offset, 0x00);
  1190. for (i = 0; i < V_COEF_SIZE; i++)
  1191. dc_write(hw, reg->v_filter_coef_data + offset, verKernel[i]);
  1192. }
  1193. static void load_rgb_to_rgb(struct dc_hw *hw, const struct dc_hw_plane_reg *reg,
  1194. u32 offset, u16 *table)
  1195. {
  1196. dc_write(hw, reg->RGBToRGBCoef0 + offset, table[0] | (table[1] << 16));
  1197. dc_write(hw, reg->RGBToRGBCoef1 + offset, table[2] | (table[3] << 16));
  1198. dc_write(hw, reg->RGBToRGBCoef2 + offset, table[4] | (table[5] << 16));
  1199. dc_write(hw, reg->RGBToRGBCoef3 + offset, table[6] | (table[7] << 16));
  1200. dc_write(hw, reg->RGBToRGBCoef4 + offset, table[8]);
  1201. }
  1202. static void load_yuv_to_rgb(struct dc_hw *hw, const struct dc_hw_plane_reg *reg,
  1203. u32 offset, s32 *table)
  1204. {
  1205. dc_write(hw, reg->YUVToRGBCoef0 + offset,
  1206. (0xFFFF & table[0]) | (table[1] << 16));
  1207. dc_write(hw, reg->YUVToRGBCoef1 + offset,
  1208. (0xFFFF & table[2]) | (table[3] << 16));
  1209. dc_write(hw, reg->YUVToRGBCoef2 + offset,
  1210. (0xFFFF & table[4]) | (table[5] << 16));
  1211. dc_write(hw, reg->YUVToRGBCoef3 + offset,
  1212. (0xFFFF & table[6]) | (table[7] << 16));
  1213. dc_write(hw, reg->YUVToRGBCoef4 + offset, table[8]);
  1214. dc_write(hw, reg->YUVToRGBCoefD0 + offset, table[9]);
  1215. dc_write(hw, reg->YUVToRGBCoefD1 + offset, table[10]);
  1216. dc_write(hw, reg->YUVToRGBCoefD2 + offset, table[11]);
  1217. dc_write(hw, reg->YClampBound + offset, table[12] | (table[13] << 16));
  1218. dc_write(hw, reg->UVClampBound + offset, table[14] | (table[15] << 16));
  1219. }
  1220. static void load_rgb_to_yuv(struct dc_hw *hw, u32 offset, s16 *table)
  1221. {
  1222. dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF0 + offset,
  1223. table[0] | (table[1] << 16));
  1224. dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF1 + offset,
  1225. table[2] | (table[3] << 16));
  1226. dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF2 + offset,
  1227. table[4] | (table[5] << 16));
  1228. dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF3 + offset,
  1229. table[6] | (table[7] << 16));
  1230. dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF4 + offset, table[8]);
  1231. dc_write(hw, DC_DISPLAY_RGBTOYUV_COEFD0 + offset, table[9]);
  1232. dc_write(hw, DC_DISPLAY_RGBTOYUV_COEFD1 + offset, table[10]);
  1233. dc_write(hw, DC_DISPLAY_RGBTOYUV_COEFD2 + offset, table[11]);
  1234. }
  1235. static bool is_rgb(enum dc_hw_color_format format)
  1236. {
  1237. switch (format) {
  1238. case FORMAT_X4R4G4B4:
  1239. case FORMAT_A4R4G4B4:
  1240. case FORMAT_X1R5G5B5:
  1241. case FORMAT_A1R5G5B5:
  1242. case FORMAT_R5G6B5:
  1243. case FORMAT_X8R8G8B8:
  1244. case FORMAT_A8R8G8B8:
  1245. case FORMAT_A2R10G10B10:
  1246. return true;
  1247. default:
  1248. return false;
  1249. }
  1250. }
  1251. static void load_degamma_table(struct dc_hw *hw,
  1252. const struct dc_hw_plane_reg *reg,
  1253. u32 offset, u16 *table)
  1254. {
  1255. u16 i;
  1256. u32 value;
  1257. dc_write(hw, reg->degamma_index + offset, 0);
  1258. for (i = 0; i < DEGAMMA_SIZE; i++) {
  1259. value = table[i] | (table[i] << 16);
  1260. dc_write(hw, reg->degamma_data + offset, value);
  1261. dc_write(hw, reg->degamma_ex_data + offset, table[i]);
  1262. }
  1263. }
  1264. static u32 get_addr_offset(u32 id)
  1265. {
  1266. u32 offset = 0;
  1267. switch(id) {
  1268. case PRIMARY_PLANE_1:
  1269. case OVERLAY_PLANE_1:
  1270. offset = 0x04;
  1271. break;
  1272. case OVERLAY_PLANE_2:
  1273. offset = 0x08;
  1274. break;
  1275. case OVERLAY_PLANE_3:
  1276. offset = 0x0C;
  1277. break;
  1278. default:
  1279. break;
  1280. }
  1281. return offset;
  1282. }
  1283. int dc_hw_init(struct dc_hw *hw)
  1284. {
  1285. u8 i, id, panel_num, layer_num;
  1286. u32 offset;
  1287. u32 revision = hi_read(hw, DC_HW_REVISION);
  1288. u32 cid = hi_read(hw, DC_HW_CHIP_CID);
  1289. const struct dc_hw_plane_reg *reg;
  1290. switch (revision) {
  1291. case 0x5720:
  1292. hw->rev = DC_REV_0;
  1293. break;
  1294. case 0x5721:
  1295. switch (cid) {
  1296. case 0x30B:
  1297. hw->rev = DC_REV_1;
  1298. break;
  1299. case 0x310:
  1300. hw->rev = DC_REV_2;
  1301. break;
  1302. default:
  1303. hw->rev = DC_REV_0;
  1304. break;
  1305. }
  1306. break;
  1307. default:
  1308. return -ENXIO;
  1309. }
  1310. hw->info = (struct vs_dc_info *)&dc_info[hw->rev];
  1311. hw->func = (struct dc_hw_funcs *)&hw_func;
  1312. layer_num = hw->info->layer_num;
  1313. for (i = 0; i < layer_num; i++) {
  1314. id = hw->info->planes[i].id;
  1315. offset = get_addr_offset(id);
  1316. if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1)
  1317. reg = &dc_plane_reg[0];
  1318. else
  1319. reg = &dc_plane_reg[1];
  1320. load_default_filter(hw, reg, offset);
  1321. load_rgb_to_rgb(hw, reg, offset, RGB2RGB);
  1322. }
  1323. panel_num = hw->info->panel_num;
  1324. for (i = 0; i < panel_num; i++) {
  1325. offset = i << 2;
  1326. load_rgb_to_yuv(hw, offset, RGB2YUV);
  1327. dc_write(hw, DC_DISPLAY_PANEL_CONFIG + offset, 0x111);
  1328. offset = i ? DC_CURSOR_OFFSET : 0;
  1329. dc_write(hw, DC_CURSOR_BACKGROUND + offset, 0x00FFFFFF);
  1330. dc_write(hw, DC_CURSOR_FOREGROUND + offset, 0x00AAAAAA);
  1331. }
  1332. dc_write(hw, DC_FRAMEBUFFER_WATER_MARK, 0x3000);
  1333. dc_write(hw, DC_FRAMEBUFFER_WATER_MARK + 0x4, 0x3000);
  1334. dc_write(hw, DC_OVERLAY_WATER_MARK, 0x3000);
  1335. dc_write(hw, DC_OVERLAY_WATER_MARK + 0x4, 0x3000);
  1336. dc_write(hw, DC_OVERLAY_WATER_MARK + 0x8, 0x3000);
  1337. dc_write(hw, DC_OVERLAY_WATER_MARK + 0xc, 0x3000);
  1338. dc_write(hw, DC_QOS_CONFIG, 0xc0);
  1339. dc_write(hw, DC_CLK_GATTING, 0x0);
  1340. dc_write(hw, DC_CLK_GATTING + 0x4, 0x0);
  1341. return 0;
  1342. }
  1343. void dc_hw_deinit(struct dc_hw *hw)
  1344. {
  1345. /* Nothing to do */
  1346. }
  1347. void dc_hw_update_plane(struct dc_hw *hw, u8 id,
  1348. struct dc_hw_fb *fb, struct dc_hw_scale *scale,
  1349. struct dc_hw_position *pos, struct dc_hw_blend *blend)
  1350. {
  1351. struct dc_hw_plane *plane = &hw->plane[id];
  1352. if (plane) {
  1353. if (fb) {
  1354. if (fb->enable == false)
  1355. plane->fb.enable = false;
  1356. else
  1357. memcpy(&plane->fb, fb,
  1358. sizeof(*fb) - sizeof(fb->dirty));
  1359. plane->fb.dirty = true;
  1360. }
  1361. if (scale) {
  1362. memcpy(&plane->scale, scale,
  1363. sizeof(*scale) - sizeof(scale->dirty));
  1364. plane->scale.dirty = true;
  1365. }
  1366. if (pos) {
  1367. memcpy(&plane->pos, pos,
  1368. sizeof(*pos) - sizeof(pos->dirty));
  1369. plane->pos.dirty = true;
  1370. }
  1371. if (blend) {
  1372. memcpy(&plane->blend, blend,
  1373. sizeof(*blend) - sizeof(blend->dirty));
  1374. plane->blend.dirty = true;
  1375. }
  1376. }
  1377. }
  1378. void dc_hw_update_degamma(struct dc_hw *hw, u8 id, u32 mode)
  1379. {
  1380. struct dc_hw_plane *plane = &hw->plane[id];
  1381. if (plane) {
  1382. if (hw->info->planes[id].degamma_size) {
  1383. plane->degamma.mode = mode;
  1384. plane->degamma.dirty = true;
  1385. } else {
  1386. plane->degamma.dirty = false;
  1387. }
  1388. }
  1389. }
  1390. void dc_hw_update_roi(struct dc_hw *hw, u8 id, struct dc_hw_roi *roi)
  1391. {
  1392. struct dc_hw_plane *plane = &hw->plane[id];
  1393. if (plane) {
  1394. memcpy(&plane->roi, roi, sizeof(*roi) - sizeof(roi->dirty));
  1395. plane->roi.dirty = true;
  1396. }
  1397. }
  1398. void dc_hw_update_colorkey(struct dc_hw *hw, u8 id,
  1399. struct dc_hw_colorkey *colorkey)
  1400. {
  1401. struct dc_hw_plane *plane = &hw->plane[id];
  1402. if (plane) {
  1403. memcpy(&plane->colorkey, colorkey,
  1404. sizeof(*colorkey) - sizeof(colorkey->dirty));
  1405. plane->colorkey.dirty = true;
  1406. }
  1407. }
  1408. void dc_hw_update_qos(struct dc_hw *hw, struct dc_hw_qos *qos)
  1409. {
  1410. memcpy(&hw->qos, qos, sizeof(*qos) - sizeof(qos->dirty));
  1411. hw->qos.dirty = true;
  1412. }
  1413. void dc_hw_update_cursor(struct dc_hw *hw, u8 id, struct dc_hw_cursor *cursor)
  1414. {
  1415. memcpy(&hw->cursor[id], cursor, sizeof(*cursor) - sizeof(cursor->dirty));
  1416. hw->cursor[id].dirty = true;
  1417. }
  1418. void dc_hw_update_gamma(struct dc_hw *hw, u8 id, u16 index,
  1419. u16 r, u16 g, u16 b)
  1420. {
  1421. if (index >= hw->info->gamma_size)
  1422. return;
  1423. hw->gamma[id].gamma[index][0] = r;
  1424. hw->gamma[id].gamma[index][1] = g;
  1425. hw->gamma[id].gamma[index][2] = b;
  1426. hw->gamma[id].dirty = true;
  1427. }
  1428. void dc_hw_enable_gamma(struct dc_hw *hw, u8 id, bool enable)
  1429. {
  1430. hw->gamma[id].enable = enable;
  1431. hw->gamma[id].dirty = true;
  1432. }
  1433. void dc_hw_enable_dump(struct dc_hw *hw, u32 addr, u32 pitch)
  1434. {
  1435. dc_write(hw, 0x14F0, addr);
  1436. dc_write(hw, 0x14E8, addr);
  1437. dc_write(hw, 0x1500, pitch);
  1438. dc_write(hw, 0x14F8, 0x30000);
  1439. }
  1440. void dc_hw_disable_dump(struct dc_hw *hw)
  1441. {
  1442. dc_write(hw, 0x14F8, 0x00);
  1443. }
  1444. void dc_hw_setup_display(struct dc_hw *hw, struct dc_hw_display *display)
  1445. {
  1446. u8 id = display->id;
  1447. memcpy(&hw->display[id], display, sizeof(*display));
  1448. hw->func->display(hw, display);
  1449. }
  1450. void dc_hw_enable_interrupt(struct dc_hw *hw, bool enable)
  1451. {
  1452. if (enable)
  1453. hi_write(hw, AQ_INTR_ENBL, 0xFFFFFFFF);
  1454. else
  1455. hi_write(hw, AQ_INTR_ENBL, 0);
  1456. }
  1457. void dc_hw_enable_irq(struct dc_hw *hw, u32 irq, bool enable)
  1458. {
  1459. u32 intr_enbl = hi_read(hw, AQ_INTR_ENBL);
  1460. intr_enbl = enable ? intr_enbl | BIT(irq) : intr_enbl & ~BIT(irq);
  1461. hi_write(hw, AQ_INTR_ENBL, intr_enbl);
  1462. }
  1463. u32 dc_hw_get_interrupt(struct dc_hw *hw)
  1464. {
  1465. return hi_read(hw, AQ_INTR_ACKNOWLEDGE);
  1466. }
  1467. bool dc_hw_check_underflow(struct dc_hw *hw)
  1468. {
  1469. return dc_read(hw, DC_FRAMEBUFFER_CONFIG) & BIT(5);
  1470. }
  1471. void dc_hw_enable_shadow_register(struct dc_hw *hw, bool enable)
  1472. {
  1473. u32 i, offset;
  1474. u8 id, layer_num = hw->info->layer_num;
  1475. u8 panel_num = hw->info->panel_num;
  1476. for (i = 0; i< layer_num; i++) {
  1477. id = hw->info->planes[i].id;
  1478. offset = get_addr_offset(id);
  1479. if (enable) {
  1480. if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1)
  1481. dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset, BIT(12), 0);
  1482. else
  1483. dc_set_clear(hw, DC_OVERLAY_CONFIG + offset, BIT(31), 0);
  1484. } else {
  1485. if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1)
  1486. dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset, 0, BIT(12));
  1487. else
  1488. dc_set_clear(hw, DC_OVERLAY_CONFIG + offset, 0, BIT(31));
  1489. }
  1490. }
  1491. for (i = 0; i< panel_num; i++) {
  1492. offset = i << 2;
  1493. if (enable)
  1494. dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG_EX + offset, 0, BIT(0));
  1495. else
  1496. dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG_EX + offset, BIT(0), 0);
  1497. }
  1498. }
  1499. void dc_hw_set_out(struct dc_hw *hw, enum dc_hw_out out, u8 id)
  1500. {
  1501. if (out <= OUT_DP)
  1502. hw->out[id] = out;
  1503. }
  1504. static void gamma_ex_commit(struct dc_hw *hw)
  1505. {
  1506. u8 panel_num = hw->info->panel_num;
  1507. u16 i, j;
  1508. u32 value;
  1509. for (j = 0; j < panel_num; j++) {
  1510. if (hw->gamma[j].dirty) {
  1511. if (hw->gamma[j].enable) {
  1512. dc_write(hw, DC_DISPLAY_GAMMA_EX_INDEX + (j << 2), 0x00);
  1513. for (i = 0; i < GAMMA_EX_SIZE; i++) {
  1514. value = hw->gamma[j].gamma[i][2] |
  1515. (hw->gamma[j].gamma[i][1] << 12);
  1516. dc_write(hw, DC_DISPLAY_GAMMA_EX_DATA + (j << 2), value);
  1517. dc_write(hw, DC_DISPLAY_GAMMA_EX_ONE_DATA + (j << 2),
  1518. hw->gamma[j].gamma[i][0]);
  1519. }
  1520. dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + (j << 2),
  1521. BIT(13), 0);
  1522. } else {
  1523. dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + (j << 2),
  1524. 0, BIT(13));
  1525. }
  1526. hw->gamma[j].dirty = false;
  1527. }
  1528. }
  1529. }
  1530. static void plane_commit(struct dc_hw *hw)
  1531. {
  1532. struct dc_hw_plane *plane;
  1533. const struct dc_hw_plane_reg *reg;
  1534. bool primary = false;
  1535. u8 id, layer_num = hw->info->layer_num;
  1536. u32 i, offset;
  1537. for (i = 0; i < layer_num; i++) {
  1538. plane = &hw->plane[i];
  1539. id = hw->info->planes[i].id;
  1540. offset = get_addr_offset(id);
  1541. if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1) {
  1542. reg = &dc_plane_reg[0];
  1543. primary = true;
  1544. } else {
  1545. reg = &dc_plane_reg[1];
  1546. primary = false;
  1547. }
  1548. if (plane->fb.dirty) {
  1549. if (plane->fb.enable) {
  1550. dc_write(hw, reg->y_address + offset,
  1551. plane->fb.y_address);
  1552. dc_write(hw, reg->u_address + offset,
  1553. plane->fb.u_address);
  1554. dc_write(hw, reg->v_address + offset,
  1555. plane->fb.v_address);
  1556. dc_write(hw, reg->y_stride + offset,
  1557. plane->fb.y_stride);
  1558. dc_write(hw, reg->u_stride + offset,
  1559. plane->fb.u_stride);
  1560. dc_write(hw, reg->v_stride + offset,
  1561. plane->fb.v_stride);
  1562. dc_write(hw, reg->size + offset,
  1563. plane->fb.width |
  1564. (plane->fb.height << 15));
  1565. if (plane->fb.clear_enable)
  1566. dc_write(hw, reg->clear_value + offset,
  1567. plane->fb.clear_value);
  1568. }
  1569. if (primary) {
  1570. dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG + offset,
  1571. (plane->fb.format << 26) |
  1572. (plane->fb.uv_swizzle << 25) |
  1573. (plane->fb.swizzle << 23) |
  1574. (plane->fb.tile_mode << 17) |
  1575. (plane->fb.yuv_color_space << 14) |
  1576. (plane->fb.rotation << 11) |
  1577. (plane->fb.clear_enable << 8),
  1578. (0x1F << 26) |
  1579. BIT(25) |
  1580. (0x03 << 23) |
  1581. (0x1F << 17) |
  1582. (0x07 << 14) |
  1583. (0x07 << 11) |
  1584. BIT(8));
  1585. dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset,
  1586. (plane->fb.dec_enable << 1) |
  1587. (plane->fb.enable << 13) |
  1588. (plane->fb.zpos << 16) |
  1589. (plane->fb.display_id << 19),
  1590. BIT(1) | BIT(13) |(0x07 << 16) | BIT(19));
  1591. } else {
  1592. dc_set_clear(hw, DC_OVERLAY_CONFIG + offset,
  1593. (plane->fb.dec_enable << 27) |
  1594. (plane->fb.clear_enable << 25) |
  1595. (plane->fb.enable << 24) |
  1596. (plane->fb.format << 16) |
  1597. (plane->fb.uv_swizzle << 15) |
  1598. (plane->fb.swizzle << 13) |
  1599. (plane->fb.tile_mode << 8) |
  1600. (plane->fb.yuv_color_space << 5) |
  1601. (plane->fb.rotation << 2),
  1602. BIT(27) |
  1603. BIT(25) |
  1604. BIT(24) |
  1605. (0x1F << 16) |
  1606. BIT(15) |
  1607. (0x03 << 13) |
  1608. (0x1F << 8) |
  1609. (0x07 << 5) |
  1610. (0x07 << 2));
  1611. dc_set_clear(hw, DC_OVERLAY_CONFIG_EX + offset,
  1612. plane->fb.zpos | (plane->fb.display_id << 3),
  1613. 0x07| BIT(3));
  1614. }
  1615. plane->fb.dirty = false;
  1616. }
  1617. if (plane->scale.dirty) {
  1618. if (plane->scale.enable) {
  1619. dc_write(hw, reg->scale_factor_x + offset,
  1620. plane->scale.scale_factor_x);
  1621. dc_write(hw, reg->scale_factor_y + offset,
  1622. plane->scale.scale_factor_y);
  1623. if (primary)
  1624. dc_set_clear(hw,
  1625. DC_FRAMEBUFFER_CONFIG + offset,
  1626. BIT(22), 0);
  1627. else
  1628. dc_set_clear(hw,
  1629. DC_OVERLAY_SCALE_CONFIG + offset,
  1630. BIT(8), 0);
  1631. } else {
  1632. if (primary)
  1633. dc_set_clear(hw,
  1634. DC_FRAMEBUFFER_CONFIG + offset,
  1635. 0, BIT(22));
  1636. else
  1637. dc_set_clear(hw,
  1638. DC_OVERLAY_SCALE_CONFIG + offset,
  1639. 0, BIT(8));
  1640. }
  1641. plane->scale.dirty = false;
  1642. }
  1643. if (plane->pos.dirty) {
  1644. dc_write(hw, reg->top_left + offset,
  1645. plane->pos.start_x |
  1646. (plane->pos.start_y << 15));
  1647. dc_write(hw, reg->bottom_right + offset,
  1648. plane->pos.end_x |
  1649. (plane->pos.end_y << 15));
  1650. plane->pos.dirty = false;
  1651. }
  1652. if (plane->blend.dirty) {
  1653. dc_write(hw, reg->src_global_color + offset,
  1654. plane->blend.alpha << 24);
  1655. dc_write(hw, reg->dst_global_color + offset,
  1656. plane->blend.alpha << 24);
  1657. switch (plane->blend.blend_mode) {
  1658. case BLEND_PREMULTI:
  1659. dc_write(hw, reg->blend_config + offset, 0x3450);
  1660. break;
  1661. case BLEND_COVERAGE:
  1662. dc_write(hw, reg->blend_config + offset, 0x3950);
  1663. break;
  1664. case BLEND_PIXEL_NONE:
  1665. dc_write(hw, reg->blend_config + offset, 0x3548);
  1666. break;
  1667. default:
  1668. break;
  1669. }
  1670. plane->blend.dirty = false;
  1671. }
  1672. if (plane->colorkey.dirty) {
  1673. dc_write(hw, reg->color_key + offset, plane->colorkey.colorkey);
  1674. dc_write(hw, reg->color_key_high + offset,
  1675. plane->colorkey.colorkey_high);
  1676. if (primary)
  1677. dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG + offset,
  1678. plane->colorkey.transparency << 9, 0x03 << 9);
  1679. else
  1680. dc_set_clear(hw, DC_OVERLAY_CONFIG + offset,
  1681. plane->colorkey.transparency, 0x03);
  1682. plane->colorkey.dirty = false;
  1683. }
  1684. if (plane->roi.dirty) {
  1685. if (plane->roi.enable) {
  1686. dc_write(hw, reg->roi_origin + offset,
  1687. plane->roi.x | (plane->roi.y << 16));
  1688. dc_write(hw, reg->roi_size + offset,
  1689. plane->roi.width | (plane->roi.height << 16));
  1690. if (primary)
  1691. dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset,
  1692. BIT(0), 0);
  1693. else
  1694. dc_set_clear(hw, DC_OVERLAY_CONFIG + offset,
  1695. BIT(22), 0);
  1696. } else {
  1697. if (primary)
  1698. dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset,
  1699. 0, BIT(0));
  1700. else
  1701. dc_set_clear(hw, DC_OVERLAY_CONFIG + offset,
  1702. 0, BIT(22));
  1703. }
  1704. plane->roi.dirty = false;
  1705. }
  1706. }
  1707. }
  1708. static void plane_ex_commit(struct dc_hw *hw)
  1709. {
  1710. struct dc_hw_plane *plane;
  1711. const struct dc_hw_plane_reg *reg;
  1712. bool primary = false;
  1713. u8 id, layer_num = hw->info->layer_num;
  1714. u32 i, offset;
  1715. for (i = 0; i < layer_num; i++) {
  1716. plane = &hw->plane[i];
  1717. id = hw->info->planes[i].id;
  1718. offset = get_addr_offset(id);
  1719. if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1) {
  1720. reg = &dc_plane_reg[0];
  1721. primary = true;
  1722. } else {
  1723. reg = &dc_plane_reg[1];
  1724. primary = false;
  1725. }
  1726. if (plane->fb.dirty) {
  1727. if (is_rgb(plane->fb.format)) {
  1728. if (primary)
  1729. dc_set_clear(hw,
  1730. DC_FRAMEBUFFER_CONFIG_EX + offset,
  1731. 0, BIT(8));
  1732. else
  1733. dc_set_clear(hw,
  1734. DC_OVERLAY_CONFIG + offset,
  1735. 0, BIT(30));
  1736. } else {
  1737. if (primary)
  1738. dc_set_clear(hw,
  1739. DC_FRAMEBUFFER_CONFIG_EX + offset,
  1740. BIT(8), BIT(6));
  1741. else
  1742. dc_set_clear(hw,
  1743. DC_OVERLAY_CONFIG + offset,
  1744. BIT(30), BIT(29));
  1745. switch (plane->fb.yuv_color_space) {
  1746. case COLOR_SPACE_601:
  1747. load_yuv_to_rgb(hw, reg, offset, YUV601_2RGB);
  1748. break;
  1749. case COLOR_SPACE_709:
  1750. load_yuv_to_rgb(hw, reg, offset, YUV709_2RGB);
  1751. break;
  1752. case COLOR_SPACE_2020:
  1753. load_yuv_to_rgb(hw, reg, offset, YUV2020_2RGB);
  1754. break;
  1755. default:
  1756. break;
  1757. }
  1758. }
  1759. }
  1760. if (plane->degamma.dirty) {
  1761. switch (plane->degamma.mode) {
  1762. case VS_DEGAMMA_DISABLE:
  1763. if (primary)
  1764. dc_set_clear(hw,
  1765. DC_FRAMEBUFFER_CONFIG_EX + offset,
  1766. 0, BIT(5));
  1767. else
  1768. dc_set_clear(hw,
  1769. DC_OVERLAY_CONFIG + offset,
  1770. 0, BIT(28));
  1771. break;
  1772. case VS_DEGAMMA_BT709:
  1773. load_degamma_table(hw, reg, offset, DEGAMMA_709);
  1774. if (primary)
  1775. dc_set_clear(hw,
  1776. DC_FRAMEBUFFER_CONFIG_EX + offset,
  1777. BIT(5), 0);
  1778. else
  1779. dc_set_clear(hw,
  1780. DC_OVERLAY_CONFIG + offset,
  1781. BIT(28), 0);
  1782. break;
  1783. case VS_DEGAMMA_BT2020:
  1784. load_degamma_table(hw, reg, offset, DEGAMMA_2020);
  1785. if (primary)
  1786. dc_set_clear(hw,
  1787. DC_FRAMEBUFFER_CONFIG_EX + offset,
  1788. BIT(5), 0);
  1789. else
  1790. dc_set_clear(hw,
  1791. DC_OVERLAY_CONFIG + offset,
  1792. BIT(28), 0);
  1793. break;
  1794. default:
  1795. break;
  1796. }
  1797. plane->degamma.dirty = false;
  1798. }
  1799. }
  1800. plane_commit(hw);
  1801. }
  1802. static void setup_display(struct dc_hw *hw, struct dc_hw_display *display)
  1803. {
  1804. u8 id = display->id;
  1805. u32 i, dpi_cfg, offset = id << 2;
  1806. u32 loffset, config, config_ex;
  1807. if (hw->display[id].enable) {
  1808. switch (display->bus_format) {
  1809. case MEDIA_BUS_FMT_RGB565_1X16:
  1810. dpi_cfg = 0;
  1811. break;
  1812. case MEDIA_BUS_FMT_RGB666_1X18:
  1813. dpi_cfg = 3;
  1814. break;
  1815. case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
  1816. dpi_cfg = 4;
  1817. break;
  1818. case MEDIA_BUS_FMT_RGB888_1X24:
  1819. dpi_cfg = 5;
  1820. break;
  1821. case MEDIA_BUS_FMT_RGB101010_1X30:
  1822. dpi_cfg = 6;
  1823. break;
  1824. default:
  1825. dpi_cfg = 5;
  1826. break;
  1827. }
  1828. dc_write(hw, DC_DISPLAY_DPI_CONFIG + offset, dpi_cfg);
  1829. if (id == 0)
  1830. dc_set_clear(hw, DC_DISPLAY_PANEL_START, 0, BIT(0) | BIT(2));
  1831. else
  1832. dc_set_clear(hw, DC_DISPLAY_PANEL_START, 0, BIT(1) | BIT(2));
  1833. dc_write(hw, DC_DISPLAY_H + offset, hw->display[id].h_active |
  1834. (hw->display[id].h_total << 16));
  1835. dc_write(hw, DC_DISPLAY_H_SYNC + offset,
  1836. hw->display[id].h_sync_start |
  1837. (hw->display[id].h_sync_end << 15) |
  1838. (hw->display[id].h_sync_polarity ? 0 : BIT(31)) |
  1839. BIT(30));
  1840. dc_write(hw, DC_DISPLAY_V + offset, hw->display[id].v_active |
  1841. (hw->display[id].v_total << 16));
  1842. dc_write(hw, DC_DISPLAY_V_SYNC + offset,
  1843. hw->display[id].v_sync_start |
  1844. (hw->display[id].v_sync_end << 15) |
  1845. (hw->display[id].v_sync_polarity ? 0 : BIT(31)) |
  1846. BIT(30));
  1847. if (hw->info->pipe_sync) {
  1848. switch (display->sync_mode) {
  1849. case VS_SINGLE_DC:
  1850. dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX,
  1851. 0, BIT(3) | BIT(4));
  1852. break;
  1853. case VS_MULTI_DC_PRIMARY:
  1854. dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX,
  1855. BIT(3) | BIT(4), 0);
  1856. break;
  1857. case VS_MULTI_DC_SECONDARY:
  1858. dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX,
  1859. BIT(3), BIT(4));
  1860. break;
  1861. default:
  1862. break;
  1863. }
  1864. }
  1865. if (hw->info->background)
  1866. dc_write(hw, DC_FRAMEBUFFER_BG_COLOR + offset,
  1867. hw->display[id].bg_color);
  1868. if (hw->display[id].dither_enable) {
  1869. dc_write(hw, DC_DISPLAY_DITHER_TABLE_LOW + offset,
  1870. DC_DISPLAY_DITHERTABLE_LOW);
  1871. dc_write(hw, DC_DISPLAY_DITHER_TABLE_HIGH + offset,
  1872. DC_DISPLAY_DITHERTABLE_HIGH);
  1873. dc_write(hw, DC_DISPLAY_DITHER_CONFIG + offset, BIT(31));
  1874. } else {
  1875. dc_write(hw, DC_DISPLAY_DITHER_CONFIG + offset, 0);
  1876. }
  1877. dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + offset, BIT(12), 0);
  1878. if (hw->display[id].sync_enable)
  1879. dc_set_clear(hw, DC_DISPLAY_PANEL_START, BIT(2) | BIT(3), 0);
  1880. else if (id == 0)
  1881. dc_set_clear(hw, DC_DISPLAY_PANEL_START, BIT(0), BIT(3));
  1882. else
  1883. dc_set_clear(hw, DC_DISPLAY_PANEL_START, BIT(1), BIT(3));
  1884. } else {
  1885. /* disable layers enabled for 'id' display which is required
  1886. * by DPU IP to avoid possible dma drop issue
  1887. */
  1888. for (i = 0; i < hw->info->layer_num; i++) {
  1889. loffset = get_addr_offset(i);
  1890. if (i == PRIMARY_PLANE_0 || i == PRIMARY_PLANE_1) {
  1891. config_ex = dc_read(hw, DC_FRAMEBUFFER_CONFIG_EX + loffset);
  1892. if (!!(config_ex & BIT(19)) == id && config_ex & BIT(13)) {
  1893. dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + loffset, 0, BIT(13));
  1894. dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + loffset, BIT(12), 0);
  1895. }
  1896. } else {
  1897. config_ex = dc_read(hw, DC_OVERLAY_CONFIG_EX + loffset);
  1898. if (!!(config_ex & BIT(3)) == id) {
  1899. config = dc_read(hw, DC_OVERLAY_CONFIG + loffset);
  1900. if (config & BIT(24)) {
  1901. dc_set_clear(hw, DC_OVERLAY_CONFIG + loffset, 0, BIT(24));
  1902. dc_set_clear(hw, DC_OVERLAY_CONFIG + loffset, BIT(31), 0);
  1903. }
  1904. }
  1905. }
  1906. }
  1907. mdelay(20);
  1908. dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + offset, 0, BIT(12));
  1909. if (id == 0)
  1910. dc_set_clear(hw, DC_DISPLAY_PANEL_START, 0, BIT(0) | BIT(2));
  1911. else
  1912. dc_set_clear(hw, DC_DISPLAY_PANEL_START, 0, BIT(1) | BIT(2));
  1913. }
  1914. }
  1915. static void setup_display_ex(struct dc_hw *hw, struct dc_hw_display *display)
  1916. {
  1917. u8 id = display->id;
  1918. u32 dp_cfg, offset = id << 2;
  1919. bool is_yuv = false;
  1920. if (hw->display[id].enable && hw->out[id] == OUT_DP) {
  1921. switch (display->bus_format) {
  1922. case MEDIA_BUS_FMT_RGB565_1X16:
  1923. dp_cfg = 0;
  1924. break;
  1925. case MEDIA_BUS_FMT_RGB666_1X18:
  1926. dp_cfg = 1;
  1927. break;
  1928. case MEDIA_BUS_FMT_RGB888_1X24:
  1929. dp_cfg = 2;
  1930. break;
  1931. case MEDIA_BUS_FMT_RGB101010_1X30:
  1932. dp_cfg = 3;
  1933. break;
  1934. case MEDIA_BUS_FMT_UYVY8_1X16:
  1935. dp_cfg = 2 << 4;
  1936. is_yuv = true;
  1937. break;
  1938. case MEDIA_BUS_FMT_YUV8_1X24:
  1939. dp_cfg = 4 << 4;
  1940. is_yuv = true;
  1941. break;
  1942. case MEDIA_BUS_FMT_UYVY10_1X20:
  1943. dp_cfg = 8 << 4;
  1944. is_yuv = true;
  1945. break;
  1946. case MEDIA_BUS_FMT_YUV10_1X30:
  1947. dp_cfg = 10 << 4;
  1948. is_yuv = true;
  1949. break;
  1950. case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
  1951. dp_cfg = 12 << 4;
  1952. is_yuv = true;
  1953. break;
  1954. case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
  1955. dp_cfg = 13 << 4;
  1956. is_yuv = true;
  1957. break;
  1958. default:
  1959. dp_cfg = 2;
  1960. break;
  1961. }
  1962. if (is_yuv)
  1963. dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + offset, BIT(16), 0);
  1964. else
  1965. dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + offset, 0, BIT(16));
  1966. dc_write(hw, DC_DISPLAY_DP_CONFIG + offset, dp_cfg | BIT(3));
  1967. }
  1968. if (hw->out[id] == OUT_DPI)
  1969. dc_set_clear(hw, DC_DISPLAY_DP_CONFIG + offset, 0, BIT(3));
  1970. setup_display(hw, display);
  1971. }
  1972. static const struct dc_hw_funcs hw_func= {
  1973. .gamma = &gamma_ex_commit,
  1974. .plane = &plane_ex_commit,
  1975. .display = setup_display_ex,
  1976. };
  1977. void dc_hw_commit(struct dc_hw *hw)
  1978. {
  1979. u32 i, offset = 0;
  1980. u8 plane_num = hw->info->plane_num;
  1981. u8 layer_num = hw->info->layer_num;
  1982. u8 cursor_num = plane_num - layer_num;
  1983. hw->func->gamma(hw);
  1984. hw->func->plane(hw);
  1985. for (i = 0; i < cursor_num; i++) {
  1986. if (hw->cursor[i].dirty) {
  1987. offset = hw->cursor[i].display_id ? DC_CURSOR_OFFSET : 0;
  1988. if (hw->cursor[i].enable) {
  1989. dc_write(hw, DC_CURSOR_ADDRESS + offset,
  1990. hw->cursor[i].address);
  1991. dc_write(hw, DC_CURSOR_LOCATION + offset, hw->cursor[i].x |
  1992. (hw->cursor[i].y << 16));
  1993. dc_set_clear(hw, DC_CURSOR_CONFIG + offset,
  1994. (hw->cursor[i].hot_x << 16) |
  1995. (hw->cursor[i].hot_y << 8) |
  1996. (hw->cursor[i].size << 5) |
  1997. BIT(3) | BIT(2) | 0x02,
  1998. (0xFF << 16) |
  1999. (0xFF << 8) |
  2000. (0x07 << 5) | 0x1F);
  2001. } else {
  2002. dc_set_clear(hw, DC_CURSOR_CONFIG + offset, BIT(3), 0x03);
  2003. }
  2004. hw->cursor[i].dirty = false;
  2005. }
  2006. }
  2007. if (hw->qos.dirty) {
  2008. dc_set_clear(hw, DC_QOS_CONFIG, (hw->qos.high_value << 4) |
  2009. hw->qos.low_value, 0xFF);
  2010. hw->qos.dirty = false;
  2011. }
  2012. }
  2013. #ifdef CONFIG_VERISILICON_DEC
  2014. void dc_hw_dec_init(struct dc_hw *hw)
  2015. {
  2016. u32 config = 0;
  2017. config = DEC_CONTROL_RESET & (~COMPRESSION_DISABLE);
  2018. dc_write(hw, DEC_CONTROL, config | FLUSH_ENABLE);
  2019. config = DEC_CONTROL_EX2_RESET &
  2020. (~TILE_STATUS_READ_ID_MASK) &
  2021. (~TILE_STATUS_READ_ID_H_MASK) &
  2022. (~DISABLE_HW_DEC_FLUSH);
  2023. dc_write(hw, DEC_CONTROL_EX2,
  2024. config | (TILE_STATUS_READ_ID_H << 22) |
  2025. TILE_STATUS_READ_ID);
  2026. config = DEC_CONTROL_EX_RESET &
  2027. (~WRITE_MISS_POLICY_MASK) &
  2028. (~READ_MISS_POLICY_MASK);
  2029. dc_write(hw, DEC_CONTROL_EX, config | (WRITE_MISS_POLICY1 << 19));
  2030. }
  2031. void dc_hw_dec_stream_set(struct dc_hw *hw,u32 main_base_addr,
  2032. u32 ts_base_addr, u8 tile_mode, u8 align_mode,
  2033. u8 format, u8 depth, u8 stream_id)
  2034. {
  2035. u32 offset = stream_id << 2;
  2036. dc_set_clear(hw, DEC_READ_CONFIG + offset,
  2037. (tile_mode << 25) |
  2038. (align_mode << 16) |
  2039. (format << 3) |
  2040. COMPRESSION_EN,
  2041. TILE_MODE_MASK |
  2042. COMPRESSION_ALIGN_MODE_MASK |
  2043. COMPRESSION_FORMAT_MASK);
  2044. dc_set_clear(hw, DEC_READ_EX_CONFIG + offset,
  2045. (depth << 16), BIT_DEPTH_MASK);
  2046. dc_write(hw, DEC_READ_BUFFER_BASE + offset, main_base_addr);
  2047. dc_write(hw, DEC_READ_BUFFER_END + offset, ts_base_addr - 128);
  2048. dc_write(hw, DEC_READ_CACHE_BASE + offset, ts_base_addr);
  2049. }
  2050. void dc_hw_dec_stream_disable(struct dc_hw *hw, u8 stream_id)
  2051. {
  2052. u32 offset = stream_id << 2;
  2053. dc_write(hw, DEC_READ_CONFIG + offset, DEC_READ_CONFIG_RESET);
  2054. dc_write(hw, DEC_READ_BUFFER_BASE + offset, 0xFFFFFFFF);
  2055. dc_write(hw, DEC_READ_BUFFER_END + offset, 0xFFFFFFFF);
  2056. }
  2057. #endif
  2058. #ifdef CONFIG_VERISILICON_MMU
  2059. static u32 mmu_read(struct dc_hw *hw, u32 reg)
  2060. {
  2061. return readl(hw->mmu_base + reg - mmu_reg_base);
  2062. }
  2063. static void mmu_write(struct dc_hw *hw, u32 reg, u32 value)
  2064. {
  2065. writel(value, hw->mmu_base + reg - mmu_reg_base);
  2066. }
  2067. static void mmu_set_clear(struct dc_hw *hw, u32 reg, u32 set, u32 clear)
  2068. {
  2069. u32 value = mmu_read(hw, reg);
  2070. value &= ~clear;
  2071. value |= set;
  2072. mmu_write(hw, reg, value);
  2073. }
  2074. int dc_hw_mmu_init(struct dc_hw *hw, dc_mmu_pt mmu)
  2075. {
  2076. const struct dc_hw_mmu_reg *reg;
  2077. u32 mtlb = 0, ext_mtlb = 0;
  2078. u32 safe_addr = 0, ext_safe_addr = 0;
  2079. u32 config = 0;
  2080. reg = &dc_mmu_reg;
  2081. mtlb = (u32)(mmu->mtlb_physical & 0xFFFFFFFF);
  2082. ext_mtlb = (u32)(mmu->mtlb_physical >> 32);
  2083. /* more than 40bit physical address */
  2084. if (ext_mtlb & 0xFFFFFF00) {
  2085. pr_err("Mtlb address out of range.\n");
  2086. return -EFAULT;
  2087. }
  2088. config = (ext_mtlb << 20) | (mtlb >> 12);
  2089. if (mmu->mode == MMU_MODE_1K)
  2090. mmu_set_clear(hw, reg->context_pd_entry,
  2091. (config << 4) |BIT(0),
  2092. (0xFFFFFFF << 4) | (0x07));
  2093. else
  2094. mmu_set_clear(hw, reg->context_pd_entry,
  2095. (config << 4),
  2096. (0xFFFFFFF << 4) | (0x07));
  2097. safe_addr = (u32)(mmu->safe_page_physical & 0xFFFFFFFF);
  2098. ext_safe_addr = (u32)(mmu->safe_page_physical >> 32);
  2099. if ((safe_addr & 0x3F) || (ext_safe_addr & 0xFFFFFF00)) {
  2100. pr_err("Invalid safe_address.\n");
  2101. return -EFAULT;
  2102. }
  2103. mmu_write(hw, reg->table_array_size, 1);
  2104. mmu_write(hw, reg->safe_secure, safe_addr);
  2105. mmu_write(hw, reg->safe_non_secure, safe_addr);
  2106. mmu_set_clear(hw, reg->safe_ex,
  2107. (ext_safe_addr << 16) |ext_safe_addr,
  2108. BIT(31) |(0xFF << 16) | BIT(15) | 0xFF);
  2109. /* mmu configuration for ree driver */
  2110. mmu_write(hw, reg->mmu_control, BIT(5) | BIT(0));
  2111. mmu_write(hw, SE_MMU_REG_INTR_ENBL, 0xFFFFFFFF);
  2112. return 0;
  2113. }
  2114. void dc_hw_enable_mmu_prefetch(struct dc_hw *hw, bool enable)
  2115. {
  2116. if (!hw->info->mmu_prefetch)
  2117. return;
  2118. if (enable)
  2119. dc_write(hw, DC_MMU_PREFETCH, BIT(0));
  2120. else
  2121. dc_write(hw, DC_MMU_PREFETCH, 0);
  2122. }
  2123. void dc_hw_mmu_flush(struct dc_hw *hw)
  2124. {
  2125. const struct dc_hw_mmu_reg *reg = &dc_mmu_reg;
  2126. u32 value = mmu_read(hw, reg->mmu_config);
  2127. mmu_write(hw, reg->mmu_config, value | BIT(4));
  2128. mmu_write(hw, reg->mmu_config, value);
  2129. }
  2130. #endif