dw_mipi_dsi.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020 VeriSilicon Holdings Co., Ltd.
  4. *
  5. * refer to bridge/synopsys/dw-mipi-dsi.c
  6. */
  7. #include <linux/version.h>
  8. #include <linux/bitfield.h>
  9. #include <linux/component.h>
  10. #include <linux/clk.h>
  11. #include <linux/mfd/syscon.h>
  12. #include <linux/of_device.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/reset.h>
  15. #include <linux/phy/phy.h>
  16. #include <linux/iopoll.h>
  17. #include <linux/phy.h>
  18. #include <linux/phy/phy-mipi-dphy.h>
  19. #include <linux/regmap.h>
  20. #include <linux/delay.h>
  21. #include <drm/drm_bridge.h>
  22. #include <drm/drm_encoder.h>
  23. #include <drm/drm_modes.h>
  24. #include <drm/drm_of.h>
  25. #include <drm/drm_mipi_dsi.h>
  26. #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 5, 0)
  27. #include <drm/drm_print.h>
  28. #else
  29. #include <drm/drmP.h>
  30. #endif
  31. #include "dw_mipi_dsi.h"
  32. #define DSI_VERSION 0x00
  33. #define DSI_PWR_UP 0x04
  34. #define RESET 0
  35. #define POWERUP BIT(0)
  36. #define DSI_CLKMGR_CFG 0x08
  37. #define TO_CLK_DIVISION(div) (((div) & 0xff) << 8)
  38. #define TX_ESC_CLK_DIVISION(div) ((div) & 0xff)
  39. #define DSI_DPI_VCID 0x0c
  40. #define DPI_VCID(vcid) ((vcid) & 0x3)
  41. #define DSI_DPI_COLOR_CODING 0x10
  42. #define LOOSELY18_EN BIT(8)
  43. #define DPI_COLOR_CODING_16BIT_1 0x0
  44. #define DPI_COLOR_CODING_16BIT_2 0x1
  45. #define DPI_COLOR_CODING_16BIT_3 0x2
  46. #define DPI_COLOR_CODING_18BIT_1 0x3
  47. #define DPI_COLOR_CODING_18BIT_2 0x4
  48. #define DPI_COLOR_CODING_24BIT 0x5
  49. #define DSI_DPI_CFG_POL 0x14
  50. #define COLORM_ACTIVE_LOW BIT(4)
  51. #define SHUTD_ACTIVE_LOW BIT(3)
  52. #define HSYNC_ACTIVE_LOW BIT(2)
  53. #define VSYNC_ACTIVE_LOW BIT(1)
  54. #define DATAEN_ACTIVE_LOW BIT(0)
  55. #define DSI_DPI_LP_CMD_TIM 0x18
  56. #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
  57. #define INVACT_LPCMD_TIME(p) ((p) & 0xff)
  58. #define DSI_DBI_VCID 0x1c
  59. #define DSI_DBI_CFG 0x20
  60. #define DSI_DBI_PARTITIONING_EN 0x24
  61. #define DSI_DBI_CMDSIZE 0x28
  62. #define DSI_PCKHDL_CFG 0x2c
  63. #define EOTP_TX_LP_EN BIT(5)
  64. #define CRC_RX_EN BIT(4)
  65. #define ECC_RX_EN BIT(3)
  66. #define BTA_EN BIT(2)
  67. #define EOTP_RX_EN BIT(1)
  68. #define EOTP_TX_EN BIT(0)
  69. #define DSI_GEN_VCID 0x30
  70. #define DSI_MODE_CFG 0x34
  71. #define ENABLE_VIDEO_MODE 0
  72. #define ENABLE_CMD_MODE BIT(0)
  73. #define DSI_VID_MODE_CFG 0x38
  74. #define VPG_ORIENTATION BIT(24)
  75. #define VPG_MODE BIT(20)
  76. #define VPG_ENABLE BIT(16)
  77. #define LP_CMD_EN BIT(15)
  78. #define FRAME_BTA_ACK_EN BIT(14)
  79. #define LP_HFP_EN BIT(13)
  80. #define LP_HBP_EN BIT(12)
  81. #define LP_VACT_EN BIT(11)
  82. #define LP_VFP_EN BIT(10)
  83. #define LP_VBP_EN BIT(9)
  84. #define LP_VSA_EN BIT(8)
  85. #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0
  86. #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1
  87. #define VID_MODE_TYPE_BURST 0x2
  88. #define VID_MODE_TYPE_MASK 0x3
  89. #define DSI_VID_PKT_SIZE 0x3c
  90. #define VID_PKT_SIZE(p) ((p) & 0x3fff)
  91. #define DSI_VID_NUM_CHUNKS 0x40
  92. #define VID_NUM_CHUNKS(c) ((c) & 0x1fff)
  93. #define DSI_VID_NULL_SIZE 0x44
  94. #define VID_NULL_SIZE(b) ((b) & 0x1fff)
  95. #define DSI_VID_HSA_TIME 0x48
  96. #define DSI_VID_HBP_TIME 0x4c
  97. #define DSI_VID_HLINE_TIME 0x50
  98. #define DSI_VID_VSA_LINES 0x54
  99. #define DSI_VID_VBP_LINES 0x58
  100. #define DSI_VID_VFP_LINES 0x5c
  101. #define DSI_VID_VACTIVE_LINES 0x60
  102. #define DSI_EDPI_CMD_SIZE 0x64
  103. #define DSI_CMD_MODE_CFG 0x68
  104. #define MAX_RD_PKT_SIZE_LP BIT(24)
  105. #define DCS_LW_TX_LP BIT(19)
  106. #define DCS_SR_0P_TX_LP BIT(18)
  107. #define DCS_SW_1P_TX_LP BIT(17)
  108. #define DCS_SW_0P_TX_LP BIT(16)
  109. #define GEN_LW_TX_LP BIT(14)
  110. #define GEN_SR_2P_TX_LP BIT(13)
  111. #define GEN_SR_1P_TX_LP BIT(12)
  112. #define GEN_SR_0P_TX_LP BIT(11)
  113. #define GEN_SW_2P_TX_LP BIT(10)
  114. #define GEN_SW_1P_TX_LP BIT(9)
  115. #define GEN_SW_0P_TX_LP BIT(8)
  116. #define ACK_RQST_EN BIT(1)
  117. #define TEAR_FX_EN BIT(0)
  118. #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
  119. DCS_LW_TX_LP | \
  120. DCS_SR_0P_TX_LP | \
  121. DCS_SW_1P_TX_LP | \
  122. DCS_SW_0P_TX_LP | \
  123. GEN_LW_TX_LP | \
  124. GEN_SR_2P_TX_LP | \
  125. GEN_SR_1P_TX_LP | \
  126. GEN_SR_0P_TX_LP | \
  127. GEN_SW_2P_TX_LP | \
  128. GEN_SW_1P_TX_LP | \
  129. GEN_SW_0P_TX_LP)
  130. #define DSI_GEN_HDR 0x6c
  131. #define DSI_GEN_PLD_DATA 0x70
  132. #define DSI_CMD_PKT_STATUS 0x74
  133. #define GEN_RD_CMD_BUSY BIT(6)
  134. #define GEN_PLD_R_FULL BIT(5)
  135. #define GEN_PLD_R_EMPTY BIT(4)
  136. #define GEN_PLD_W_FULL BIT(3)
  137. #define GEN_PLD_W_EMPTY BIT(2)
  138. #define GEN_CMD_FULL BIT(1)
  139. #define GEN_CMD_EMPTY BIT(0)
  140. #define DSI_TO_CNT_CFG 0x78
  141. #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
  142. #define LPRX_TO_CNT(p) ((p) & 0xffff)
  143. #define DSI_HS_RD_TO_CNT 0x7c
  144. #define DSI_LP_RD_TO_CNT 0x80
  145. #define DSI_HS_WR_TO_CNT 0x84
  146. #define DSI_LP_WR_TO_CNT 0x88
  147. #define DSI_BTA_TO_CNT 0x8c
  148. #define DSI_LPCLK_CTRL 0x94
  149. #define AUTO_CLKLANE_CTRL BIT(1)
  150. #define PHY_TXREQUESTCLKHS BIT(0)
  151. #define DSI_PHY_TMR_LPCLK_CFG 0x98
  152. #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
  153. #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
  154. #define DSI_PHY_TMR_CFG 0x9c
  155. #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
  156. #define PHY_LP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
  157. #define DSI_PHY_RSTZ 0xa0
  158. #define PHY_DISFORCEPLL 0
  159. #define PHY_ENFORCEPLL BIT(3)
  160. #define PHY_DISABLECLK 0
  161. #define PHY_ENABLECLK BIT(2)
  162. #define PHY_RSTZ 0
  163. #define PHY_UNRSTZ BIT(1)
  164. #define PHY_SHUTDOWNZ 0
  165. #define PHY_UNSHUTDOWNZ BIT(0)
  166. #define DSI_PHY_IF_CFG 0xa4
  167. #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
  168. #define N_LANES(n) (((n) - 1) & 0x3)
  169. #define DSI_PHY_ULPS_CTRL 0xa8
  170. #define DSI_PHY_TX_TRIGGERS 0xac
  171. #define DSI_PHY_STATUS 0xb0
  172. #define PHY_STOP_STATE_CLK_LANE BIT(2)
  173. #define PHY_LOCK BIT(0)
  174. #define DSI_INT_ST0 0xbc
  175. #define DSI_INT_ST1 0xc0
  176. #define DSI_INT_MSK0 0xc4
  177. #define DSI_INT_MSK1 0xc8
  178. #define DSI_PHY_TMR_RD_CFG 0xf4
  179. #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
  180. #define PHY_STATUS_TIMEOUT_US 10000
  181. #define CMD_PKT_STATUS_TIMEOUT_US 20000
  182. #define MAX_LANE_COUNT 4
  183. struct dw_mipi_dsi;
  184. static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi);
  185. struct dw_mipi_dsi_funcs {
  186. struct dw_mipi_dsi *(*get_dsi)(struct device *dev);
  187. int (*bind)(struct dw_mipi_dsi *dsi);
  188. void (*unbind)(struct dw_mipi_dsi *dsi);
  189. };
  190. struct dw_mipi_dsi {
  191. struct device *dev;
  192. struct regmap *regmap;
  193. /* apb slave bus clock */
  194. struct clk *pclk;
  195. struct clk *pixclk;
  196. struct phy *dphy;
  197. union phy_configure_opts phy_opts;
  198. struct mipi_dsi_host host;
  199. unsigned int channel;
  200. unsigned int lanes;
  201. enum mipi_dsi_pixel_format format;
  202. unsigned long mode_flags;
  203. unsigned int lane_link_rate; /* kHz */
  204. const struct dw_mipi_dsi_funcs *funcs;
  205. };
  206. struct dw_mipi_dsi_primary {
  207. struct dw_mipi_dsi dsi;
  208. struct dw_mipi_dsi *secondary_dsi;
  209. struct drm_bridge bridge;
  210. struct drm_bridge *panel_bridge;
  211. u32 bus_format;
  212. };
  213. static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
  214. {
  215. return container_of(host, struct dw_mipi_dsi, host);
  216. }
  217. static inline struct
  218. dw_mipi_dsi_primary *dsi_to_primary(struct dw_mipi_dsi *dsi)
  219. {
  220. return container_of(dsi, struct dw_mipi_dsi_primary, dsi);
  221. }
  222. static inline struct
  223. dw_mipi_dsi_primary *bridge_to_primary(struct drm_bridge *bridge)
  224. {
  225. return container_of(bridge, struct dw_mipi_dsi_primary, bridge);
  226. }
  227. static inline int dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
  228. {
  229. int ret;
  230. WARN_ON(ret = regmap_write(dsi->regmap, reg, val));
  231. return ret;
  232. }
  233. static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg, u32 *val)
  234. {
  235. int ret;
  236. WARN_ON(ret = regmap_read(dsi->regmap, reg, val));
  237. return ret;
  238. }
  239. static int dsi_host_attach(struct mipi_dsi_host *host,
  240. struct mipi_dsi_device *device)
  241. {
  242. struct dw_mipi_dsi *dsi = host_to_dsi(host);
  243. if (device->lanes > MAX_LANE_COUNT) {
  244. DRM_ERROR("the number of data lanes(%u) is too many\n",
  245. device->lanes);
  246. return -EINVAL;
  247. }
  248. if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST))
  249. DRM_WARN("This DSI driver only support burst mode\n");
  250. dsi->lanes = device->lanes;
  251. dsi->channel = device->channel;
  252. dsi->format = device->format;
  253. dsi->mode_flags = device->mode_flags;
  254. return 0;
  255. }
  256. static int dsi_host_detach(struct mipi_dsi_host *host,
  257. struct mipi_dsi_device *device)
  258. {
  259. return 0;
  260. }
  261. static void dw_mipi_dsi_lpclk_config(struct dw_mipi_dsi *dsi, bool hsclk)
  262. {
  263. u32 lpclk_ctrl = 0;
  264. lpclk_ctrl |= hsclk ? PHY_TXREQUESTCLKHS : 0;
  265. lpclk_ctrl |= dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS ?
  266. AUTO_CLKLANE_CTRL : 0;
  267. dsi_write(dsi, DSI_LPCLK_CTRL, lpclk_ctrl);
  268. }
  269. static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
  270. unsigned long mode_flags)
  271. {
  272. u32 mode_cfg;
  273. mode_cfg = mode_flags & MIPI_DSI_MODE_VIDEO ?
  274. ENABLE_VIDEO_MODE : ENABLE_CMD_MODE;
  275. dsi_write(dsi, DSI_MODE_CFG, mode_cfg);
  276. }
  277. static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
  278. const struct mipi_dsi_msg *msg)
  279. {
  280. bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
  281. u32 val = 0;
  282. if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
  283. val |= ACK_RQST_EN;
  284. if (lpm)
  285. val |= CMD_MODE_ALL_LP | MAX_RD_PKT_SIZE_LP;
  286. dsi_write(dsi, DSI_CMD_MODE_CFG, val);
  287. }
  288. static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
  289. {
  290. int ret;
  291. u32 val, mask;
  292. ret = regmap_read_poll_timeout(dsi->regmap, DSI_CMD_PKT_STATUS,
  293. val, !(val & GEN_CMD_FULL), 1000,
  294. CMD_PKT_STATUS_TIMEOUT_US);
  295. if (ret) {
  296. DRM_ERROR("failed to get available command FIFO\n");
  297. return ret;
  298. }
  299. dsi_write(dsi, DSI_GEN_HDR, hdr_val);
  300. mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
  301. ret = regmap_read_poll_timeout(dsi->regmap, DSI_CMD_PKT_STATUS,
  302. val, (val & mask) == mask,
  303. 1000, CMD_PKT_STATUS_TIMEOUT_US);
  304. if (ret) {
  305. DRM_ERROR("failed to write command FIFO\n");
  306. return ret;
  307. }
  308. return 0;
  309. }
  310. static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
  311. const struct mipi_dsi_packet *packet)
  312. {
  313. const u8 *tx_buf = packet->payload;
  314. int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
  315. __le32 word;
  316. u32 val;
  317. while (len) {
  318. if (len < pld_data_bytes) {
  319. word = 0;
  320. memcpy(&word, tx_buf, len);
  321. dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
  322. len = 0;
  323. } else {
  324. memcpy(&word, tx_buf, pld_data_bytes);
  325. dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
  326. tx_buf += pld_data_bytes;
  327. len -= pld_data_bytes;
  328. }
  329. ret = regmap_read_poll_timeout(dsi->regmap, DSI_CMD_PKT_STATUS,
  330. val, !(val & GEN_PLD_W_FULL), 1000,
  331. CMD_PKT_STATUS_TIMEOUT_US);
  332. if (ret) {
  333. DRM_ERROR("failed to get write payload FIFO\n");
  334. return ret;
  335. }
  336. }
  337. word = 0;
  338. memcpy(&word, packet->header, sizeof(packet->header));
  339. return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
  340. }
  341. static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
  342. const struct mipi_dsi_msg *msg)
  343. {
  344. int i, j, ret, len = msg->rx_len;
  345. u8 *buf = msg->rx_buf;
  346. u32 val;
  347. /* Wait end of the read operation */
  348. ret = regmap_read_poll_timeout(dsi->regmap, DSI_CMD_PKT_STATUS,
  349. val, !(val & GEN_RD_CMD_BUSY),
  350. 1000, CMD_PKT_STATUS_TIMEOUT_US);
  351. if (ret) {
  352. DRM_ERROR("Timeout during read operation\n");
  353. return ret;
  354. }
  355. for (i = 0; i < len; i += 4) {
  356. /* Read fifo must not be empty before all bytes are read */
  357. ret = regmap_read_poll_timeout(dsi->regmap, DSI_CMD_PKT_STATUS,
  358. val, !(val & GEN_PLD_R_EMPTY),
  359. 1000, CMD_PKT_STATUS_TIMEOUT_US);
  360. if (ret) {
  361. DRM_ERROR("Read payload FIFO is empty\n");
  362. return ret;
  363. }
  364. ret = dsi_read(dsi, DSI_GEN_PLD_DATA, &val);
  365. if (unlikely(ret))
  366. return ret;
  367. for (j = 0; j < 4 && j + i < len; j++)
  368. buf[i + j] = val >> (8 * j);
  369. }
  370. return ret;
  371. }
  372. static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
  373. const struct mipi_dsi_msg *msg)
  374. {
  375. struct dw_mipi_dsi *dsi = host_to_dsi(host);
  376. struct mipi_dsi_packet packet;
  377. int ret, nb_bytes;
  378. ret = mipi_dsi_create_packet(&packet, msg);
  379. if (ret) {
  380. DRM_ERROR("failed to create packet: %d\n", ret);
  381. return ret;
  382. }
  383. dw_mipi_message_config(dsi, msg);
  384. ret = dw_mipi_dsi_write(dsi, &packet);
  385. if (ret)
  386. return ret;
  387. if (msg->rx_buf && msg->rx_len) {
  388. ret = dw_mipi_dsi_read(dsi, msg);
  389. if (ret)
  390. return ret;
  391. nb_bytes = msg->rx_len;
  392. } else {
  393. nb_bytes = packet.size;
  394. }
  395. return nb_bytes;
  396. }
  397. static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
  398. .attach = dsi_host_attach,
  399. .detach = dsi_host_detach,
  400. .transfer = dsi_host_transfer,
  401. };
  402. static void dw_mipi_dsi_power_config(struct dw_mipi_dsi *dsi, bool on)
  403. {
  404. dsi_write(dsi, DSI_PWR_UP, on ? POWERUP : RESET);
  405. }
  406. static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
  407. {
  408. u32 vid_mode_cfg = 0;
  409. /* configure low-power transitions */
  410. vid_mode_cfg |= LP_HFP_EN |
  411. LP_HBP_EN |
  412. LP_VACT_EN |
  413. LP_VFP_EN |
  414. LP_VBP_EN |
  415. LP_VSA_EN;
  416. /* configure commands transfer in high speed mode */
  417. vid_mode_cfg &= ~LP_CMD_EN;
  418. /* configure burs-mode or non-burst mode */
  419. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
  420. vid_mode_cfg |= VID_MODE_TYPE_BURST;
  421. else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
  422. vid_mode_cfg |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
  423. else
  424. vid_mode_cfg |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
  425. #if 0
  426. /* enable colorbar mode */
  427. vid_mode_cfg |= VPG_ENABLE;
  428. #endif
  429. dsi_write(dsi, DSI_VID_MODE_CFG, vid_mode_cfg);
  430. }
  431. static void dw_mipi_dsi_set_esc_div(struct dw_mipi_dsi *dsi)
  432. {
  433. u8 esc_clk;
  434. u32 esc_clk_division;
  435. esc_clk = 20; /* 20MHz */
  436. /*
  437. * The maximum permitted escape clock is 20MHz and it is derived from
  438. * lanebyteclk, which is running at "lane_link_rate / 8". Thus we want:
  439. *
  440. * (lane_link_rate >> 3) / esc_clk_division < 20
  441. * which is:
  442. * (lane_link_rate >> 3) / 20 > esc_clk_division
  443. */
  444. esc_clk_division = ((dsi->lane_link_rate / 1000) >> 3) / esc_clk + 1;
  445. /*
  446. * TODO dw drv improvements
  447. * timeout clock division should be computed with the
  448. * high speed transmission counter timeout and byte lane...
  449. */
  450. dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
  451. TX_ESC_CLK_DIVISION(esc_clk_division));
  452. }
  453. static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
  454. const struct drm_display_mode *mode)
  455. {
  456. u32 dpi_cfg_pol = 0, dpi_color_coding = 0;
  457. dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
  458. switch (dsi->format) {
  459. case MIPI_DSI_FMT_RGB888:
  460. dpi_color_coding = DPI_COLOR_CODING_24BIT;
  461. break;
  462. case MIPI_DSI_FMT_RGB666:
  463. dpi_color_coding = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
  464. break;
  465. case MIPI_DSI_FMT_RGB666_PACKED:
  466. dpi_color_coding = DPI_COLOR_CODING_18BIT_1;
  467. break;
  468. case MIPI_DSI_FMT_RGB565:
  469. dpi_color_coding = DPI_COLOR_CODING_16BIT_1;
  470. break;
  471. }
  472. dsi_write(dsi, DSI_DPI_COLOR_CODING, dpi_color_coding);
  473. /* TODO: negotiate bus flags for DE polarity */
  474. if (mode->flags & DRM_MODE_FLAG_NVSYNC)
  475. dpi_cfg_pol |= VSYNC_ACTIVE_LOW;
  476. if (mode->flags & DRM_MODE_FLAG_NHSYNC)
  477. dpi_cfg_pol |= HSYNC_ACTIVE_LOW;
  478. dsi_write(dsi, DSI_DPI_CFG_POL, dpi_cfg_pol);
  479. /*
  480. * TODO dw drv improvements
  481. * largest packet sizes during hfp or during vsa/vpb/vfp
  482. * should be computed according to byte lane, lane number and only
  483. * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
  484. */
  485. dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
  486. | INVACT_LPCMD_TIME(4));
  487. }
  488. static void __maybe_unused dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
  489. {
  490. u32 pkthdl_cfg;
  491. pkthdl_cfg = EOTP_TX_LP_EN | EOTP_TX_EN | BTA_EN;
  492. dsi_write(dsi, DSI_PCKHDL_CFG, pkthdl_cfg);
  493. }
  494. static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
  495. {
  496. u32 cmd_mode_cfg;
  497. /*
  498. * TODO dw drv improvements
  499. * compute high speed transmission counter timeout according
  500. * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
  501. */
  502. dsi_write(dsi, DSI_TO_CNT_CFG,
  503. HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
  504. /*
  505. * TODO dw drv improvements
  506. * the Bus-Turn-Around Timeout Counter should be computed
  507. * according to byte lane...
  508. */
  509. dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
  510. /* TODO use low power mode to transfer
  511. * commands in command mode in default
  512. */
  513. cmd_mode_cfg = MAX_RD_PKT_SIZE_LP |
  514. DCS_LW_TX_LP |
  515. DCS_SR_0P_TX_LP |
  516. DCS_SW_1P_TX_LP |
  517. DCS_SW_0P_TX_LP |
  518. GEN_LW_TX_LP |
  519. GEN_SR_2P_TX_LP |
  520. GEN_SR_1P_TX_LP |
  521. GEN_SR_0P_TX_LP |
  522. GEN_SW_2P_TX_LP |
  523. GEN_SW_1P_TX_LP |
  524. GEN_SW_0P_TX_LP;
  525. dsi_write(dsi, DSI_CMD_MODE_CFG, cmd_mode_cfg);
  526. }
  527. /* Get lane byte clock cycles. */
  528. static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
  529. const struct drm_display_mode *mode,
  530. u32 hcomponent)
  531. {
  532. u32 frac, lbcc;
  533. lbcc = hcomponent * dsi->lane_link_rate / 8;
  534. frac = lbcc % mode->clock;
  535. lbcc = lbcc / mode->clock;
  536. if (frac)
  537. lbcc++;
  538. return lbcc;
  539. }
  540. static void dw_mipi_dsi_timing_config(struct dw_mipi_dsi *dsi,
  541. const struct drm_display_mode *mode)
  542. {
  543. u32 htotal, hsa, hbp, lbcc;
  544. htotal = mode->htotal;
  545. hsa = mode->hsync_end - mode->hsync_start;
  546. hbp = mode->htotal - mode->hsync_end;
  547. lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
  548. dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
  549. lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
  550. dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
  551. lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
  552. dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
  553. dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
  554. /* vertical */
  555. dsi_write(dsi, DSI_VID_VACTIVE_LINES, mode->vdisplay);
  556. dsi_write(dsi, DSI_VID_VSA_LINES, mode->vsync_end - mode->vsync_start);
  557. dsi_write(dsi, DSI_VID_VFP_LINES, mode->vsync_start - mode->vdisplay);
  558. dsi_write(dsi, DSI_VID_VBP_LINES, mode->vtotal - mode->vsync_end);
  559. }
  560. static void __maybe_unused dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
  561. {
  562. /*
  563. * TODO dw drv improvements
  564. * stop wait time should be the maximum between host dsi
  565. * and panel stop wait times
  566. */
  567. dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
  568. N_LANES(dsi->lanes));
  569. }
  570. static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
  571. {
  572. u32 val;
  573. int ret;
  574. phy_power_on(dsi->dphy);
  575. ret = regmap_read_poll_timeout(dsi->regmap, DSI_PHY_STATUS, val,
  576. val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US);
  577. if (ret)
  578. DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
  579. ret = regmap_read_poll_timeout(dsi->regmap, DSI_PHY_STATUS,
  580. val, val & PHY_STOP_STATE_CLK_LANE, 1000,
  581. PHY_STATUS_TIMEOUT_US);
  582. if (ret)
  583. DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
  584. }
  585. /*
  586. * The controller should generate 2 frames before
  587. * preparing the peripheral.
  588. */
  589. static void __maybe_unused dw_mipi_dsi_wait_for_two_frames(const struct drm_display_mode *mode)
  590. {
  591. int refresh, two_frames;
  592. refresh = drm_mode_vrefresh(mode);
  593. two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
  594. msleep(two_frames);
  595. }
  596. static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
  597. {
  598. regmap_update_bits(dsi->regmap, DSI_PHY_RSTZ, PHY_UNRSTZ, PHY_RSTZ);
  599. regmap_update_bits(dsi->regmap, DSI_PHY_RSTZ, PHY_UNSHUTDOWNZ, PHY_SHUTDOWNZ);
  600. phy_init(dsi->dphy);
  601. phy_configure(dsi->dphy, &dsi->phy_opts);
  602. dw_mipi_dsi_set_esc_div(dsi);
  603. }
  604. static void dw_mipi_dsi_mode_set(struct dw_mipi_dsi *dsi,
  605. const struct drm_display_mode *mode)
  606. {
  607. pm_runtime_get_sync(dsi->dev);
  608. /* configure DSI hosts */
  609. dw_mipi_dsi_dpi_config(dsi, mode);
  610. dw_mipi_dsi_video_mode_config(dsi);
  611. dw_mipi_dsi_timing_config(dsi, mode);
  612. dw_mipi_dsi_packet_handler_config(dsi);
  613. dw_mipi_dsi_command_mode_config(dsi);
  614. dw_mipi_dsi_dphy_init(dsi);
  615. dw_mipi_dsi_wait_for_two_frames(mode);
  616. /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
  617. dw_mipi_dsi_set_mode(dsi, 0);
  618. dw_mipi_dsi_power_config(dsi, true);
  619. pm_runtime_put(dsi->dev);
  620. }
  621. static enum drm_mode_status bridge_mode_valid(struct drm_bridge *bridge,
  622. const struct drm_display_info *info,
  623. const struct drm_display_mode *mode)
  624. {
  625. int bpp, ret;
  626. struct dw_mipi_dsi_primary *primary = bridge_to_primary(bridge);
  627. struct dw_mipi_dsi *dsi = &primary->dsi;
  628. struct phy_configure_opts_mipi_dphy *dphy_cfg = &dsi->phy_opts.mipi_dphy;
  629. bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
  630. if (bpp < 0)
  631. return MODE_BAD;
  632. phy_mipi_dphy_get_default_config(mode->clock * 1000, bpp,
  633. dsi->lanes, dphy_cfg);
  634. ret = phy_validate(dsi->dphy, PHY_MODE_MIPI_DPHY, 0, &dsi->phy_opts);
  635. if (!ret)
  636. dsi->lane_link_rate = dphy_cfg->hs_clk_rate / 1000;
  637. return ret ? MODE_BAD : MODE_OK;
  638. }
  639. static void bridge_mode_set(struct drm_bridge *bridge,
  640. const struct drm_display_mode *mode,
  641. const struct drm_display_mode *adjusted_mode)
  642. {
  643. struct dw_mipi_dsi_primary *primary = bridge_to_primary(bridge);
  644. struct drm_display_mode *new_mode =
  645. drm_mode_duplicate(bridge->dev, adjusted_mode);
  646. if (primary->secondary_dsi) {
  647. new_mode->hdisplay /= 2;
  648. new_mode->hsync_start /= 2;
  649. new_mode->hsync_end /= 2;
  650. new_mode->htotal /= 2;
  651. new_mode->clock /= 2;
  652. }
  653. dw_mipi_dsi_mode_set(&primary->dsi, new_mode);
  654. if (primary->secondary_dsi)
  655. dw_mipi_dsi_mode_set(primary->secondary_dsi, new_mode);
  656. drm_mode_destroy(bridge->dev, new_mode);
  657. }
  658. static void bridge_enable(struct drm_bridge *bridge)
  659. {
  660. struct dw_mipi_dsi_primary *primary = bridge_to_primary(bridge);
  661. struct dw_mipi_dsi *dsi = &primary->dsi;
  662. #if 0
  663. if (primary->secondary_dsi)
  664. dw_mipi_dsi_mode_config(primary->secondary_dsi,
  665. MIPI_DSI_MODE_VIDEO);
  666. #endif
  667. pm_runtime_get_sync(dsi->dev);
  668. dw_mipi_dsi_dphy_enable(dsi);
  669. dw_mipi_dsi_power_config(dsi, true);
  670. dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
  671. dw_mipi_dsi_lpclk_config(dsi, true);
  672. }
  673. static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
  674. {
  675. dw_mipi_dsi_power_config(dsi, false);
  676. phy_power_off(dsi->dphy);
  677. pm_runtime_put(dsi->dev);
  678. }
  679. static void bridge_post_disable(struct drm_bridge *bridge)
  680. {
  681. struct dw_mipi_dsi_primary *primary = bridge_to_primary(bridge);
  682. /*
  683. * Switch to command mode before panel-bridge post_disable &
  684. * panel unprepare.
  685. * Note: panel-bridge disable & panel disable has been called
  686. * before by the drm framework.
  687. */
  688. dw_mipi_dsi_set_mode(&primary->dsi, 0);
  689. /*
  690. * TODO Only way found to call panel-bridge post_disable &
  691. * panel unprepare before the dsi "final" disable...
  692. * This needs to be fixed in the drm_bridge framework and the API
  693. * needs to be updated to manage our own call chains...
  694. */
  695. primary->panel_bridge->funcs->post_disable(primary->panel_bridge);
  696. if (primary->secondary_dsi)
  697. dw_mipi_dsi_disable(primary->secondary_dsi);
  698. dw_mipi_dsi_disable(&primary->dsi);
  699. }
  700. #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 7, 0)
  701. static int bridge_attach(struct drm_bridge *bridge,
  702. enum drm_bridge_attach_flags flags)
  703. #else
  704. static int bridge_attach(struct drm_bridge *bridge)
  705. #endif
  706. {
  707. struct dw_mipi_dsi_primary *primary = bridge_to_primary(bridge);
  708. if (!bridge->encoder) {
  709. DRM_ERROR("Parent encoder object not found\n");
  710. return -ENODEV;
  711. }
  712. /* Attach the panel-bridge to the dsi bridge */
  713. #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 7, 0)
  714. return drm_bridge_attach(bridge->encoder, primary->panel_bridge,
  715. bridge, 0);
  716. #else
  717. return drm_bridge_attach(bridge->encoder, primary->panel_bridge,
  718. bridge);
  719. #endif
  720. }
  721. static void bridge_update_bus_format(struct drm_bridge *bridge)
  722. {
  723. struct dw_mipi_dsi_primary *primary = bridge_to_primary(bridge);
  724. struct drm_connector *connector;
  725. struct drm_connector_list_iter conn_iter;
  726. struct drm_encoder *encoder;
  727. u32 bus_format;
  728. #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)
  729. int i;
  730. #endif
  731. /* set bus format according to DSI format */
  732. switch (primary->dsi.format) {
  733. case MIPI_DSI_FMT_RGB888:
  734. bus_format = MEDIA_BUS_FMT_RGB888_1X24;
  735. break;
  736. case MIPI_DSI_FMT_RGB666:
  737. bus_format = MEDIA_BUS_FMT_RGB666_1X24_CPADHI;
  738. break;
  739. case MIPI_DSI_FMT_RGB666_PACKED:
  740. bus_format = MEDIA_BUS_FMT_RGB666_1X18;
  741. break;
  742. case MIPI_DSI_FMT_RGB565:
  743. bus_format = MEDIA_BUS_FMT_RGB565_1X16;
  744. break;
  745. default:
  746. bus_format = MEDIA_BUS_FMT_RGB888_1X24;
  747. }
  748. if (bus_format == primary->bus_format)
  749. return;
  750. drm_connector_list_iter_begin(bridge->dev, &conn_iter);
  751. drm_for_each_connector_iter(connector, &conn_iter) {
  752. #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)
  753. drm_connector_for_each_possible_encoder(connector, encoder, i) {
  754. #else
  755. drm_connector_for_each_possible_encoder(connector, encoder) {
  756. #endif
  757. if (encoder == bridge->encoder) {
  758. drm_display_info_set_bus_formats(
  759. &connector->display_info,
  760. &bus_format, 1);
  761. primary->bus_format = bus_format;
  762. drm_connector_list_iter_end(&conn_iter);
  763. return;
  764. }
  765. }
  766. }
  767. drm_connector_list_iter_end(&conn_iter);
  768. }
  769. #if 1
  770. static bool bridge_mode_fixup(struct drm_bridge *bridge,
  771. const struct drm_display_mode *mode,
  772. struct drm_display_mode *adjusted_mode)
  773. {
  774. bridge_update_bus_format(bridge);
  775. return true;
  776. }
  777. #else
  778. static int bridge_atomic_check(struct drm_bridge *bridge,
  779. struct drm_bridge_state *bridge_state,
  780. struct drm_crtc_state *crtc_state,
  781. struct drm_connector_state *conn_state)
  782. {
  783. return 0;
  784. }
  785. #endif
  786. static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = {
  787. .mode_valid = bridge_mode_valid,
  788. .mode_set = bridge_mode_set,
  789. .enable = bridge_enable,
  790. .post_disable = bridge_post_disable,
  791. .attach = bridge_attach,
  792. #if 1
  793. .mode_fixup = bridge_mode_fixup,
  794. #else
  795. .atomic_check = bridge_atomic_check,
  796. .atomic_reset = drm_atomic_helper_bridge_reset,
  797. .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
  798. .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
  799. .atomic_get_input_bus_fmts = bridge_atomic_get_input_bus_fmts,
  800. #endif
  801. };
  802. static int dsi_attach_primary(struct dw_mipi_dsi *secondary, struct device *dev)
  803. {
  804. struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
  805. struct dw_mipi_dsi_primary *primary = dsi_to_primary(dsi);
  806. if (!of_device_is_compatible(dev->of_node, "verisilicon,dw-mipi-dsi0"))
  807. return -EINVAL;
  808. primary->secondary_dsi = secondary;
  809. return 0;
  810. }
  811. struct dw_mipi_dsi *get_primary_dsi(struct device *dev)
  812. {
  813. struct dw_mipi_dsi_primary *primary;
  814. primary = devm_kzalloc(dev, sizeof(*primary), GFP_KERNEL);
  815. if (!primary)
  816. return NULL;
  817. primary->dsi.dev = dev;
  818. return &primary->dsi;
  819. }
  820. static int primary_bind(struct dw_mipi_dsi *dsi)
  821. {
  822. struct dw_mipi_dsi_primary *primary = dsi_to_primary(dsi);
  823. struct device *dev = primary->dsi.dev;
  824. struct drm_bridge *bridge;
  825. struct drm_panel *panel;
  826. int ret;
  827. ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, &bridge);
  828. if (ret)
  829. return ret;
  830. if (panel) {
  831. bridge = drm_panel_bridge_add(panel);
  832. if (IS_ERR(bridge))
  833. return PTR_ERR(bridge);
  834. }
  835. primary->panel_bridge = bridge;
  836. primary->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
  837. primary->bridge.of_node = dev->of_node;
  838. drm_bridge_add(&primary->bridge);
  839. return 0;
  840. }
  841. static void primary_unbind(struct dw_mipi_dsi *dsi)
  842. {
  843. struct dw_mipi_dsi_primary *primary = dsi_to_primary(dsi);
  844. struct device *dev = primary->dsi.dev;
  845. drm_bridge_remove(&primary->bridge);
  846. drm_of_panel_bridge_remove(dev->of_node, 1, 0);
  847. }
  848. static const struct dw_mipi_dsi_funcs primary = {
  849. .get_dsi = &get_primary_dsi,
  850. .bind = &primary_bind,
  851. .unbind = &primary_unbind,
  852. };
  853. struct dw_mipi_dsi *get_secondary_dsi(struct device *dev)
  854. {
  855. struct dw_mipi_dsi *dsi;
  856. dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
  857. if (!dsi)
  858. return NULL;
  859. dsi->dev = dev;
  860. return dsi;
  861. }
  862. static int secondary_bind(struct dw_mipi_dsi *dsi)
  863. {
  864. struct device_node *np;
  865. struct platform_device *pdev;
  866. np = of_find_compatible_node(NULL, NULL, "verisilicon,dw-mipi-dsi0");
  867. if (!np)
  868. return -ENODEV;
  869. pdev = of_find_device_by_node(np);
  870. of_node_put(np);
  871. if (!pdev)
  872. return -ENODEV;
  873. return dsi_attach_primary(dsi, &pdev->dev);
  874. }
  875. static void secondary_unbind(struct dw_mipi_dsi *dsi)
  876. {
  877. }
  878. static const struct dw_mipi_dsi_funcs secondary = {
  879. .get_dsi = &get_secondary_dsi,
  880. .bind = &secondary_bind,
  881. .unbind = &secondary_unbind,
  882. };
  883. static int dsi_bind(struct device *dev, struct device *primary, void *data)
  884. {
  885. struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
  886. return dsi->funcs->bind(dsi);
  887. }
  888. static void dsi_unbind(struct device *dev, struct device *primary, void *data)
  889. {
  890. struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
  891. dsi->funcs->unbind(dsi);
  892. }
  893. static const struct component_ops dsi_component_ops = {
  894. .bind = dsi_bind,
  895. .unbind = dsi_unbind,
  896. };
  897. static const struct of_device_id dw_mipi_dsi_dt_match[] = {
  898. { .compatible = "verisilicon,dw-mipi-dsi", .data = &primary},
  899. { .compatible = "verisilicon,dw-mipi-dsi-2nd", .data = &secondary},
  900. {},
  901. };
  902. MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_match);
  903. static int dsi_probe(struct platform_device *pdev)
  904. {
  905. struct device *dev = &pdev->dev;
  906. struct device_node *np = dev->of_node;
  907. const struct dw_mipi_dsi_funcs *funcs;
  908. struct dw_mipi_dsi *dsi;
  909. int ret;
  910. funcs = of_device_get_match_data(dev);
  911. dsi = funcs->get_dsi(dev);
  912. if (!dsi)
  913. return -ENOMEM;
  914. dsi->regmap = syscon_regmap_lookup_by_phandle(np, "regmap");
  915. if (IS_ERR(dsi->regmap))
  916. return PTR_ERR(dsi->regmap);
  917. dsi->pclk = devm_clk_get_optional(dev, "pclk");
  918. if (IS_ERR(dsi->pclk))
  919. return PTR_ERR(dsi->pclk);
  920. dsi->pixclk = devm_clk_get_optional(dev, "pixclk");
  921. if (IS_ERR(dsi->pixclk))
  922. return PTR_ERR(dsi->pixclk);
  923. dsi->dphy = devm_phy_get(dev, "dphy");
  924. if (IS_ERR(dsi->dphy))
  925. return PTR_ERR(dsi->dphy);
  926. dsi->host.ops = &dw_mipi_dsi_host_ops;
  927. dsi->host.dev = dev;
  928. ret = mipi_dsi_host_register(&dsi->host);
  929. if (ret)
  930. return ret;
  931. dsi->funcs = funcs;
  932. dev_set_drvdata(dev, dsi);
  933. pm_runtime_enable(dev);
  934. ret = component_add(dev, &dsi_component_ops);
  935. if (ret)
  936. goto host_unregister;
  937. return 0;
  938. host_unregister:
  939. pm_runtime_disable(dev);
  940. mipi_dsi_host_unregister(&dsi->host);
  941. return ret;
  942. }
  943. static int dsi_remove(struct platform_device *pdev)
  944. {
  945. struct device *dev = &pdev->dev;
  946. struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
  947. mipi_dsi_host_unregister(&dsi->host);
  948. pm_runtime_disable(dev);
  949. component_del(dev, &dsi_component_ops);
  950. dev_set_drvdata(dev, NULL);
  951. return 0;
  952. }
  953. #ifdef CONFIG_PM
  954. static int dsi_runtime_suspend(struct device *dev)
  955. {
  956. struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
  957. clk_disable_unprepare(dsi->pixclk);
  958. clk_disable_unprepare(dsi->pclk);
  959. return 0;
  960. }
  961. static int dsi_runtime_resume(struct device *dev)
  962. {
  963. struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
  964. clk_prepare_enable(dsi->pclk);
  965. clk_prepare_enable(dsi->pixclk);
  966. return 0;
  967. }
  968. #endif
  969. static const struct dev_pm_ops dsi_pm_ops = {
  970. SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  971. pm_runtime_force_resume)
  972. SET_RUNTIME_PM_OPS(dsi_runtime_suspend, dsi_runtime_resume, NULL)
  973. };
  974. struct platform_driver dw_mipi_dsi_driver = {
  975. .probe = dsi_probe,
  976. .remove = dsi_remove,
  977. .driver = {
  978. .name = "dw-mipi-dsi",
  979. .of_match_table = of_match_ptr(dw_mipi_dsi_dt_match),
  980. .pm = &dsi_pm_ops,
  981. },
  982. };
  983. MODULE_DESCRIPTION("DW MIPI DSI Controller Driver");
  984. MODULE_LICENSE("GPL v2");