vc4_txp.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright © 2018 Broadcom
  4. *
  5. * Authors:
  6. * Eric Anholt <eric@anholt.net>
  7. * Boris Brezillon <boris.brezillon@bootlin.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/component.h>
  11. #include <linux/of_graph.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/pm_runtime.h>
  14. #include <drm/drm_atomic_helper.h>
  15. #include <drm/drm_edid.h>
  16. #include <drm/drm_fb_cma_helper.h>
  17. #include <drm/drm_fourcc.h>
  18. #include <drm/drm_panel.h>
  19. #include <drm/drm_probe_helper.h>
  20. #include <drm/drm_vblank.h>
  21. #include <drm/drm_writeback.h>
  22. #include "vc4_drv.h"
  23. #include "vc4_regs.h"
  24. /* Base address of the output. Raster formats must be 4-byte aligned,
  25. * T and LT must be 16-byte aligned or maybe utile-aligned (docs are
  26. * inconsistent, but probably utile).
  27. */
  28. #define TXP_DST_PTR 0x00
  29. /* Pitch in bytes for raster images, 16-byte aligned. For tiled, it's
  30. * the width in tiles.
  31. */
  32. #define TXP_DST_PITCH 0x04
  33. /* For T-tiled imgaes, DST_PITCH should be the number of tiles wide,
  34. * shifted up.
  35. */
  36. # define TXP_T_TILE_WIDTH_SHIFT 7
  37. /* For LT-tiled images, DST_PITCH should be the number of utiles wide,
  38. * shifted up.
  39. */
  40. # define TXP_LT_TILE_WIDTH_SHIFT 4
  41. /* Pre-rotation width/height of the image. Must match HVS config.
  42. *
  43. * If TFORMAT and 32-bit, limit is 1920 for 32-bit and 3840 to 16-bit
  44. * and width/height must be tile or utile-aligned as appropriate. If
  45. * transposing (rotating), width is limited to 1920.
  46. *
  47. * Height is limited to various numbers between 4088 and 4095. I'd
  48. * just use 4088 to be safe.
  49. */
  50. #define TXP_DIM 0x08
  51. # define TXP_HEIGHT_SHIFT 16
  52. # define TXP_HEIGHT_MASK GENMASK(31, 16)
  53. # define TXP_WIDTH_SHIFT 0
  54. # define TXP_WIDTH_MASK GENMASK(15, 0)
  55. #define TXP_DST_CTRL 0x0c
  56. /* These bits are set to 0x54 */
  57. #define TXP_PILOT_SHIFT 24
  58. #define TXP_PILOT_MASK GENMASK(31, 24)
  59. /* Bits 22-23 are set to 0x01 */
  60. #define TXP_VERSION_SHIFT 22
  61. #define TXP_VERSION_MASK GENMASK(23, 22)
  62. /* Powers down the internal memory. */
  63. # define TXP_POWERDOWN BIT(21)
  64. /* Enables storing the alpha component in 8888/4444, instead of
  65. * filling with ~ALPHA_INVERT.
  66. */
  67. # define TXP_ALPHA_ENABLE BIT(20)
  68. /* 4 bits, each enables stores for a channel in each set of 4 bytes.
  69. * Set to 0xf for normal operation.
  70. */
  71. # define TXP_BYTE_ENABLE_SHIFT 16
  72. # define TXP_BYTE_ENABLE_MASK GENMASK(19, 16)
  73. /* Debug: Generate VSTART again at EOF. */
  74. # define TXP_VSTART_AT_EOF BIT(15)
  75. /* Debug: Terminate the current frame immediately. Stops AXI
  76. * writes.
  77. */
  78. # define TXP_ABORT BIT(14)
  79. # define TXP_DITHER BIT(13)
  80. /* Inverts alpha if TXP_ALPHA_ENABLE, chooses fill value for
  81. * !TXP_ALPHA_ENABLE.
  82. */
  83. # define TXP_ALPHA_INVERT BIT(12)
  84. /* Note: I've listed the channels here in high bit (in byte 3/2/1) to
  85. * low bit (in byte 0) order.
  86. */
  87. # define TXP_FORMAT_SHIFT 8
  88. # define TXP_FORMAT_MASK GENMASK(11, 8)
  89. # define TXP_FORMAT_ABGR4444 0
  90. # define TXP_FORMAT_ARGB4444 1
  91. # define TXP_FORMAT_BGRA4444 2
  92. # define TXP_FORMAT_RGBA4444 3
  93. # define TXP_FORMAT_BGR565 6
  94. # define TXP_FORMAT_RGB565 7
  95. /* 888s are non-rotated, raster-only */
  96. # define TXP_FORMAT_BGR888 8
  97. # define TXP_FORMAT_RGB888 9
  98. # define TXP_FORMAT_ABGR8888 12
  99. # define TXP_FORMAT_ARGB8888 13
  100. # define TXP_FORMAT_BGRA8888 14
  101. # define TXP_FORMAT_RGBA8888 15
  102. /* If TFORMAT is set, generates LT instead of T format. */
  103. # define TXP_LINEAR_UTILE BIT(7)
  104. /* Rotate output by 90 degrees. */
  105. # define TXP_TRANSPOSE BIT(6)
  106. /* Generate a tiled format for V3D. */
  107. # define TXP_TFORMAT BIT(5)
  108. /* Generates some undefined test mode output. */
  109. # define TXP_TEST_MODE BIT(4)
  110. /* Request odd field from HVS. */
  111. # define TXP_FIELD BIT(3)
  112. /* Raise interrupt when idle. */
  113. # define TXP_EI BIT(2)
  114. /* Set when generating a frame, clears when idle. */
  115. # define TXP_BUSY BIT(1)
  116. /* Starts a frame. Self-clearing. */
  117. # define TXP_GO BIT(0)
  118. /* Number of lines received and committed to memory. */
  119. #define TXP_PROGRESS 0x10
  120. #define TXP_READ(offset) readl(txp->regs + (offset))
  121. #define TXP_WRITE(offset, val) writel(val, txp->regs + (offset))
  122. struct vc4_txp {
  123. struct vc4_crtc base;
  124. struct platform_device *pdev;
  125. struct drm_writeback_connector connector;
  126. void __iomem *regs;
  127. struct debugfs_regset32 regset;
  128. };
  129. static inline struct vc4_txp *encoder_to_vc4_txp(struct drm_encoder *encoder)
  130. {
  131. return container_of(encoder, struct vc4_txp, connector.encoder);
  132. }
  133. static inline struct vc4_txp *connector_to_vc4_txp(struct drm_connector *conn)
  134. {
  135. return container_of(conn, struct vc4_txp, connector.base);
  136. }
  137. static const struct debugfs_reg32 txp_regs[] = {
  138. VC4_REG32(TXP_DST_PTR),
  139. VC4_REG32(TXP_DST_PITCH),
  140. VC4_REG32(TXP_DIM),
  141. VC4_REG32(TXP_DST_CTRL),
  142. VC4_REG32(TXP_PROGRESS),
  143. };
  144. static int vc4_txp_connector_get_modes(struct drm_connector *connector)
  145. {
  146. struct drm_device *dev = connector->dev;
  147. return drm_add_modes_noedid(connector, dev->mode_config.max_width,
  148. dev->mode_config.max_height);
  149. }
  150. static enum drm_mode_status
  151. vc4_txp_connector_mode_valid(struct drm_connector *connector,
  152. struct drm_display_mode *mode)
  153. {
  154. struct drm_device *dev = connector->dev;
  155. struct drm_mode_config *mode_config = &dev->mode_config;
  156. int w = mode->hdisplay, h = mode->vdisplay;
  157. if (w < mode_config->min_width || w > mode_config->max_width)
  158. return MODE_BAD_HVALUE;
  159. if (h < mode_config->min_height || h > mode_config->max_height)
  160. return MODE_BAD_VVALUE;
  161. return MODE_OK;
  162. }
  163. static const u32 drm_fmts[] = {
  164. DRM_FORMAT_RGB888,
  165. DRM_FORMAT_BGR888,
  166. DRM_FORMAT_XRGB8888,
  167. DRM_FORMAT_XBGR8888,
  168. DRM_FORMAT_ARGB8888,
  169. DRM_FORMAT_ABGR8888,
  170. DRM_FORMAT_RGBX8888,
  171. DRM_FORMAT_BGRX8888,
  172. DRM_FORMAT_RGBA8888,
  173. DRM_FORMAT_BGRA8888,
  174. };
  175. static const u32 txp_fmts[] = {
  176. TXP_FORMAT_RGB888,
  177. TXP_FORMAT_BGR888,
  178. TXP_FORMAT_ARGB8888,
  179. TXP_FORMAT_ABGR8888,
  180. TXP_FORMAT_ARGB8888,
  181. TXP_FORMAT_ABGR8888,
  182. TXP_FORMAT_RGBA8888,
  183. TXP_FORMAT_BGRA8888,
  184. TXP_FORMAT_RGBA8888,
  185. TXP_FORMAT_BGRA8888,
  186. };
  187. static void vc4_txp_armed(struct drm_crtc_state *state)
  188. {
  189. struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
  190. vc4_state->txp_armed = true;
  191. }
  192. static int vc4_txp_connector_atomic_check(struct drm_connector *conn,
  193. struct drm_atomic_state *state)
  194. {
  195. struct drm_connector_state *conn_state;
  196. struct drm_crtc_state *crtc_state;
  197. struct drm_framebuffer *fb;
  198. int i;
  199. conn_state = drm_atomic_get_new_connector_state(state, conn);
  200. if (!conn_state->writeback_job)
  201. return 0;
  202. crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
  203. fb = conn_state->writeback_job->fb;
  204. if (fb->width != crtc_state->mode.hdisplay ||
  205. fb->height != crtc_state->mode.vdisplay) {
  206. DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n",
  207. fb->width, fb->height);
  208. return -EINVAL;
  209. }
  210. for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) {
  211. if (fb->format->format == drm_fmts[i])
  212. break;
  213. }
  214. if (i == ARRAY_SIZE(drm_fmts))
  215. return -EINVAL;
  216. /* Pitch must be aligned on 16 bytes. */
  217. if (fb->pitches[0] & GENMASK(3, 0))
  218. return -EINVAL;
  219. vc4_txp_armed(crtc_state);
  220. return 0;
  221. }
  222. static void vc4_txp_connector_atomic_commit(struct drm_connector *conn,
  223. struct drm_connector_state *conn_state)
  224. {
  225. struct vc4_txp *txp = connector_to_vc4_txp(conn);
  226. struct drm_gem_cma_object *gem;
  227. struct drm_display_mode *mode;
  228. struct drm_framebuffer *fb;
  229. u32 ctrl;
  230. int i;
  231. if (WARN_ON(!conn_state->writeback_job))
  232. return;
  233. mode = &conn_state->crtc->state->adjusted_mode;
  234. fb = conn_state->writeback_job->fb;
  235. for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) {
  236. if (fb->format->format == drm_fmts[i])
  237. break;
  238. }
  239. if (WARN_ON(i == ARRAY_SIZE(drm_fmts)))
  240. return;
  241. ctrl = TXP_GO | TXP_VSTART_AT_EOF | TXP_EI |
  242. VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) |
  243. VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT);
  244. if (fb->format->has_alpha)
  245. ctrl |= TXP_ALPHA_ENABLE;
  246. gem = drm_fb_cma_get_gem_obj(fb, 0);
  247. TXP_WRITE(TXP_DST_PTR, gem->paddr + fb->offsets[0]);
  248. TXP_WRITE(TXP_DST_PITCH, fb->pitches[0]);
  249. TXP_WRITE(TXP_DIM,
  250. VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) |
  251. VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT));
  252. TXP_WRITE(TXP_DST_CTRL, ctrl);
  253. drm_writeback_queue_job(&txp->connector, conn_state);
  254. }
  255. static const struct drm_connector_helper_funcs vc4_txp_connector_helper_funcs = {
  256. .get_modes = vc4_txp_connector_get_modes,
  257. .mode_valid = vc4_txp_connector_mode_valid,
  258. .atomic_check = vc4_txp_connector_atomic_check,
  259. .atomic_commit = vc4_txp_connector_atomic_commit,
  260. };
  261. static enum drm_connector_status
  262. vc4_txp_connector_detect(struct drm_connector *connector, bool force)
  263. {
  264. return connector_status_connected;
  265. }
  266. static void vc4_txp_connector_destroy(struct drm_connector *connector)
  267. {
  268. drm_connector_unregister(connector);
  269. drm_connector_cleanup(connector);
  270. }
  271. static const struct drm_connector_funcs vc4_txp_connector_funcs = {
  272. .detect = vc4_txp_connector_detect,
  273. .fill_modes = drm_helper_probe_single_connector_modes,
  274. .destroy = vc4_txp_connector_destroy,
  275. .reset = drm_atomic_helper_connector_reset,
  276. .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  277. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  278. };
  279. static void vc4_txp_encoder_disable(struct drm_encoder *encoder)
  280. {
  281. struct vc4_txp *txp = encoder_to_vc4_txp(encoder);
  282. if (TXP_READ(TXP_DST_CTRL) & TXP_BUSY) {
  283. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  284. TXP_WRITE(TXP_DST_CTRL, TXP_ABORT);
  285. while (TXP_READ(TXP_DST_CTRL) & TXP_BUSY &&
  286. time_before(jiffies, timeout))
  287. ;
  288. WARN_ON(TXP_READ(TXP_DST_CTRL) & TXP_BUSY);
  289. }
  290. TXP_WRITE(TXP_DST_CTRL, TXP_POWERDOWN);
  291. }
  292. static const struct drm_encoder_helper_funcs vc4_txp_encoder_helper_funcs = {
  293. .disable = vc4_txp_encoder_disable,
  294. };
  295. static int vc4_txp_enable_vblank(struct drm_crtc *crtc)
  296. {
  297. return 0;
  298. }
  299. static void vc4_txp_disable_vblank(struct drm_crtc *crtc) {}
  300. static const struct drm_crtc_funcs vc4_txp_crtc_funcs = {
  301. .set_config = drm_atomic_helper_set_config,
  302. .destroy = vc4_crtc_destroy,
  303. .page_flip = vc4_page_flip,
  304. .reset = vc4_crtc_reset,
  305. .atomic_duplicate_state = vc4_crtc_duplicate_state,
  306. .atomic_destroy_state = vc4_crtc_destroy_state,
  307. .gamma_set = drm_atomic_helper_legacy_gamma_set,
  308. .enable_vblank = vc4_txp_enable_vblank,
  309. .disable_vblank = vc4_txp_disable_vblank,
  310. };
  311. static int vc4_txp_atomic_check(struct drm_crtc *crtc,
  312. struct drm_crtc_state *state)
  313. {
  314. struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
  315. int ret;
  316. ret = vc4_hvs_atomic_check(crtc, state);
  317. if (ret)
  318. return ret;
  319. state->no_vblank = true;
  320. vc4_state->feed_txp = true;
  321. return 0;
  322. }
  323. static void vc4_txp_atomic_enable(struct drm_crtc *crtc,
  324. struct drm_crtc_state *old_state)
  325. {
  326. drm_crtc_vblank_on(crtc);
  327. vc4_hvs_atomic_enable(crtc, old_state);
  328. }
  329. static void vc4_txp_atomic_disable(struct drm_crtc *crtc,
  330. struct drm_crtc_state *old_state)
  331. {
  332. struct drm_device *dev = crtc->dev;
  333. /* Disable vblank irq handling before crtc is disabled. */
  334. drm_crtc_vblank_off(crtc);
  335. vc4_hvs_atomic_disable(crtc, old_state);
  336. /*
  337. * Make sure we issue a vblank event after disabling the CRTC if
  338. * someone was waiting it.
  339. */
  340. if (crtc->state->event) {
  341. unsigned long flags;
  342. spin_lock_irqsave(&dev->event_lock, flags);
  343. drm_crtc_send_vblank_event(crtc, crtc->state->event);
  344. crtc->state->event = NULL;
  345. spin_unlock_irqrestore(&dev->event_lock, flags);
  346. }
  347. }
  348. static const struct drm_crtc_helper_funcs vc4_txp_crtc_helper_funcs = {
  349. .atomic_check = vc4_txp_atomic_check,
  350. .atomic_flush = vc4_hvs_atomic_flush,
  351. .atomic_enable = vc4_txp_atomic_enable,
  352. .atomic_disable = vc4_txp_atomic_disable,
  353. };
  354. static irqreturn_t vc4_txp_interrupt(int irq, void *data)
  355. {
  356. struct vc4_txp *txp = data;
  357. struct vc4_crtc *vc4_crtc = &txp->base;
  358. TXP_WRITE(TXP_DST_CTRL, TXP_READ(TXP_DST_CTRL) & ~TXP_EI);
  359. vc4_crtc_handle_vblank(vc4_crtc);
  360. drm_writeback_signal_completion(&txp->connector, 0);
  361. return IRQ_HANDLED;
  362. }
  363. static const struct vc4_crtc_data vc4_txp_crtc_data = {
  364. .hvs_available_channels = BIT(2),
  365. .hvs_output = 2,
  366. };
  367. static int vc4_txp_bind(struct device *dev, struct device *master, void *data)
  368. {
  369. struct platform_device *pdev = to_platform_device(dev);
  370. struct drm_device *drm = dev_get_drvdata(master);
  371. struct vc4_dev *vc4 = to_vc4_dev(drm);
  372. struct vc4_crtc *vc4_crtc;
  373. struct vc4_txp *txp;
  374. struct drm_crtc *crtc;
  375. struct drm_encoder *encoder;
  376. int ret, irq;
  377. irq = platform_get_irq(pdev, 0);
  378. if (irq < 0)
  379. return irq;
  380. txp = devm_kzalloc(dev, sizeof(*txp), GFP_KERNEL);
  381. if (!txp)
  382. return -ENOMEM;
  383. vc4_crtc = &txp->base;
  384. crtc = &vc4_crtc->base;
  385. vc4_crtc->pdev = pdev;
  386. vc4_crtc->data = &vc4_txp_crtc_data;
  387. txp->pdev = pdev;
  388. txp->regs = vc4_ioremap_regs(pdev, 0);
  389. if (IS_ERR(txp->regs))
  390. return PTR_ERR(txp->regs);
  391. txp->regset.base = txp->regs;
  392. txp->regset.regs = txp_regs;
  393. txp->regset.nregs = ARRAY_SIZE(txp_regs);
  394. drm_connector_helper_add(&txp->connector.base,
  395. &vc4_txp_connector_helper_funcs);
  396. ret = drm_writeback_connector_init(drm, &txp->connector,
  397. &vc4_txp_connector_funcs,
  398. &vc4_txp_encoder_helper_funcs,
  399. drm_fmts, ARRAY_SIZE(drm_fmts));
  400. if (ret)
  401. return ret;
  402. ret = vc4_crtc_init(drm, vc4_crtc,
  403. &vc4_txp_crtc_funcs, &vc4_txp_crtc_helper_funcs);
  404. if (ret)
  405. return ret;
  406. encoder = &txp->connector.encoder;
  407. encoder->possible_crtcs = drm_crtc_mask(crtc);
  408. ret = devm_request_irq(dev, irq, vc4_txp_interrupt, 0,
  409. dev_name(dev), txp);
  410. if (ret)
  411. return ret;
  412. dev_set_drvdata(dev, txp);
  413. vc4->txp = txp;
  414. vc4_debugfs_add_regset32(drm, "txp_regs", &txp->regset);
  415. return 0;
  416. }
  417. static void vc4_txp_unbind(struct device *dev, struct device *master,
  418. void *data)
  419. {
  420. struct drm_device *drm = dev_get_drvdata(master);
  421. struct vc4_dev *vc4 = to_vc4_dev(drm);
  422. struct vc4_txp *txp = dev_get_drvdata(dev);
  423. vc4_txp_connector_destroy(&txp->connector.base);
  424. vc4->txp = NULL;
  425. }
  426. static const struct component_ops vc4_txp_ops = {
  427. .bind = vc4_txp_bind,
  428. .unbind = vc4_txp_unbind,
  429. };
  430. static int vc4_txp_probe(struct platform_device *pdev)
  431. {
  432. return component_add(&pdev->dev, &vc4_txp_ops);
  433. }
  434. static int vc4_txp_remove(struct platform_device *pdev)
  435. {
  436. component_del(&pdev->dev, &vc4_txp_ops);
  437. return 0;
  438. }
  439. static const struct of_device_id vc4_txp_dt_match[] = {
  440. { .compatible = "brcm,bcm2835-txp" },
  441. { /* sentinel */ },
  442. };
  443. struct platform_driver vc4_txp_driver = {
  444. .probe = vc4_txp_probe,
  445. .remove = vc4_txp_remove,
  446. .driver = {
  447. .name = "vc4_txp",
  448. .of_match_table = vc4_txp_dt_match,
  449. },
  450. };