vc4_kms.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2015 Broadcom
  4. */
  5. /**
  6. * DOC: VC4 KMS
  7. *
  8. * This is the general code for implementing KMS mode setting that
  9. * doesn't clearly associate with any of the other objects (plane,
  10. * crtc, HDMI encoder).
  11. */
  12. #include <linux/clk.h>
  13. #include <drm/drm_atomic.h>
  14. #include <drm/drm_atomic_helper.h>
  15. #include <drm/drm_crtc.h>
  16. #include <drm/drm_gem_framebuffer_helper.h>
  17. #include <drm/drm_plane_helper.h>
  18. #include <drm/drm_probe_helper.h>
  19. #include <drm/drm_vblank.h>
  20. #include "vc4_drv.h"
  21. #include "vc4_regs.h"
  22. #define HVS_NUM_CHANNELS 3
  23. struct vc4_ctm_state {
  24. struct drm_private_state base;
  25. struct drm_color_ctm *ctm;
  26. int fifo;
  27. };
  28. static struct vc4_ctm_state *to_vc4_ctm_state(struct drm_private_state *priv)
  29. {
  30. return container_of(priv, struct vc4_ctm_state, base);
  31. }
  32. struct vc4_hvs_state {
  33. struct drm_private_state base;
  34. unsigned int unassigned_channels;
  35. };
  36. static struct vc4_hvs_state *
  37. to_vc4_hvs_state(struct drm_private_state *priv)
  38. {
  39. return container_of(priv, struct vc4_hvs_state, base);
  40. }
  41. struct vc4_load_tracker_state {
  42. struct drm_private_state base;
  43. u64 hvs_load;
  44. u64 membus_load;
  45. };
  46. static struct vc4_load_tracker_state *
  47. to_vc4_load_tracker_state(struct drm_private_state *priv)
  48. {
  49. return container_of(priv, struct vc4_load_tracker_state, base);
  50. }
  51. static struct vc4_ctm_state *vc4_get_ctm_state(struct drm_atomic_state *state,
  52. struct drm_private_obj *manager)
  53. {
  54. struct drm_device *dev = state->dev;
  55. struct vc4_dev *vc4 = to_vc4_dev(dev);
  56. struct drm_private_state *priv_state;
  57. int ret;
  58. ret = drm_modeset_lock(&vc4->ctm_state_lock, state->acquire_ctx);
  59. if (ret)
  60. return ERR_PTR(ret);
  61. priv_state = drm_atomic_get_private_obj_state(state, manager);
  62. if (IS_ERR(priv_state))
  63. return ERR_CAST(priv_state);
  64. return to_vc4_ctm_state(priv_state);
  65. }
  66. static struct drm_private_state *
  67. vc4_ctm_duplicate_state(struct drm_private_obj *obj)
  68. {
  69. struct vc4_ctm_state *state;
  70. state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
  71. if (!state)
  72. return NULL;
  73. __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
  74. return &state->base;
  75. }
  76. static void vc4_ctm_destroy_state(struct drm_private_obj *obj,
  77. struct drm_private_state *state)
  78. {
  79. struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(state);
  80. kfree(ctm_state);
  81. }
  82. static const struct drm_private_state_funcs vc4_ctm_state_funcs = {
  83. .atomic_duplicate_state = vc4_ctm_duplicate_state,
  84. .atomic_destroy_state = vc4_ctm_destroy_state,
  85. };
  86. static void vc4_ctm_obj_fini(struct drm_device *dev, void *unused)
  87. {
  88. struct vc4_dev *vc4 = to_vc4_dev(dev);
  89. drm_atomic_private_obj_fini(&vc4->ctm_manager);
  90. }
  91. static int vc4_ctm_obj_init(struct vc4_dev *vc4)
  92. {
  93. struct vc4_ctm_state *ctm_state;
  94. drm_modeset_lock_init(&vc4->ctm_state_lock);
  95. ctm_state = kzalloc(sizeof(*ctm_state), GFP_KERNEL);
  96. if (!ctm_state)
  97. return -ENOMEM;
  98. drm_atomic_private_obj_init(&vc4->base, &vc4->ctm_manager, &ctm_state->base,
  99. &vc4_ctm_state_funcs);
  100. return drmm_add_action_or_reset(&vc4->base, vc4_ctm_obj_fini, NULL);
  101. }
  102. /* Converts a DRM S31.32 value to the HW S0.9 format. */
  103. static u16 vc4_ctm_s31_32_to_s0_9(u64 in)
  104. {
  105. u16 r;
  106. /* Sign bit. */
  107. r = in & BIT_ULL(63) ? BIT(9) : 0;
  108. if ((in & GENMASK_ULL(62, 32)) > 0) {
  109. /* We have zero integer bits so we can only saturate here. */
  110. r |= GENMASK(8, 0);
  111. } else {
  112. /* Otherwise take the 9 most important fractional bits. */
  113. r |= (in >> 23) & GENMASK(8, 0);
  114. }
  115. return r;
  116. }
  117. static void
  118. vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state)
  119. {
  120. struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state);
  121. struct drm_color_ctm *ctm = ctm_state->ctm;
  122. if (ctm_state->fifo) {
  123. HVS_WRITE(SCALER_OLEDCOEF2,
  124. VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]),
  125. SCALER_OLEDCOEF2_R_TO_R) |
  126. VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]),
  127. SCALER_OLEDCOEF2_R_TO_G) |
  128. VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]),
  129. SCALER_OLEDCOEF2_R_TO_B));
  130. HVS_WRITE(SCALER_OLEDCOEF1,
  131. VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]),
  132. SCALER_OLEDCOEF1_G_TO_R) |
  133. VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]),
  134. SCALER_OLEDCOEF1_G_TO_G) |
  135. VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]),
  136. SCALER_OLEDCOEF1_G_TO_B));
  137. HVS_WRITE(SCALER_OLEDCOEF0,
  138. VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]),
  139. SCALER_OLEDCOEF0_B_TO_R) |
  140. VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]),
  141. SCALER_OLEDCOEF0_B_TO_G) |
  142. VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]),
  143. SCALER_OLEDCOEF0_B_TO_B));
  144. }
  145. HVS_WRITE(SCALER_OLEDOFFS,
  146. VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO));
  147. }
  148. static struct vc4_hvs_state *
  149. vc4_hvs_get_global_state(struct drm_atomic_state *state)
  150. {
  151. struct vc4_dev *vc4 = to_vc4_dev(state->dev);
  152. struct drm_private_state *priv_state;
  153. priv_state = drm_atomic_get_private_obj_state(state, &vc4->hvs_channels);
  154. if (IS_ERR(priv_state))
  155. return ERR_CAST(priv_state);
  156. return to_vc4_hvs_state(priv_state);
  157. }
  158. static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4,
  159. struct drm_atomic_state *state)
  160. {
  161. struct drm_crtc_state *crtc_state;
  162. struct drm_crtc *crtc;
  163. unsigned int i;
  164. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  165. struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
  166. u32 dispctrl;
  167. u32 dsp3_mux;
  168. if (!crtc_state->active)
  169. continue;
  170. if (vc4_state->assigned_channel != 2)
  171. continue;
  172. /*
  173. * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
  174. * FIFO X'.
  175. * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
  176. *
  177. * DSP3 is connected to FIFO2 unless the transposer is
  178. * enabled. In this case, FIFO 2 is directly accessed by the
  179. * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
  180. * route.
  181. */
  182. if (vc4_state->feed_txp)
  183. dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
  184. else
  185. dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
  186. dispctrl = HVS_READ(SCALER_DISPCTRL) &
  187. ~SCALER_DISPCTRL_DSP3_MUX_MASK;
  188. HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
  189. }
  190. }
  191. static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4,
  192. struct drm_atomic_state *state)
  193. {
  194. struct drm_crtc_state *crtc_state;
  195. struct drm_crtc *crtc;
  196. unsigned char mux;
  197. unsigned int i;
  198. u32 reg;
  199. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  200. struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
  201. struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  202. if (!vc4_state->update_muxing)
  203. continue;
  204. switch (vc4_crtc->data->hvs_output) {
  205. case 2:
  206. mux = (vc4_state->assigned_channel == 2) ? 0 : 1;
  207. reg = HVS_READ(SCALER_DISPECTRL);
  208. HVS_WRITE(SCALER_DISPECTRL,
  209. (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) |
  210. VC4_SET_FIELD(mux, SCALER_DISPECTRL_DSP2_MUX));
  211. break;
  212. case 3:
  213. if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED)
  214. mux = 3;
  215. else
  216. mux = vc4_state->assigned_channel;
  217. reg = HVS_READ(SCALER_DISPCTRL);
  218. HVS_WRITE(SCALER_DISPCTRL,
  219. (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) |
  220. VC4_SET_FIELD(mux, SCALER_DISPCTRL_DSP3_MUX));
  221. break;
  222. case 4:
  223. if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED)
  224. mux = 3;
  225. else
  226. mux = vc4_state->assigned_channel;
  227. reg = HVS_READ(SCALER_DISPEOLN);
  228. HVS_WRITE(SCALER_DISPEOLN,
  229. (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) |
  230. VC4_SET_FIELD(mux, SCALER_DISPEOLN_DSP4_MUX));
  231. break;
  232. case 5:
  233. if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED)
  234. mux = 3;
  235. else
  236. mux = vc4_state->assigned_channel;
  237. reg = HVS_READ(SCALER_DISPDITHER);
  238. HVS_WRITE(SCALER_DISPDITHER,
  239. (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) |
  240. VC4_SET_FIELD(mux, SCALER_DISPDITHER_DSP5_MUX));
  241. break;
  242. default:
  243. break;
  244. }
  245. }
  246. }
  247. static void
  248. vc4_atomic_complete_commit(struct drm_atomic_state *state)
  249. {
  250. struct drm_device *dev = state->dev;
  251. struct vc4_dev *vc4 = to_vc4_dev(dev);
  252. struct vc4_hvs *hvs = vc4->hvs;
  253. struct drm_crtc_state *new_crtc_state;
  254. struct drm_crtc *crtc;
  255. int i;
  256. for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
  257. struct vc4_crtc_state *vc4_crtc_state;
  258. if (!new_crtc_state->commit)
  259. continue;
  260. vc4_crtc_state = to_vc4_crtc_state(new_crtc_state);
  261. vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel);
  262. }
  263. if (vc4->hvs->hvs5)
  264. clk_set_min_rate(hvs->core_clk, 500000000);
  265. drm_atomic_helper_wait_for_fences(dev, state, false);
  266. drm_atomic_helper_wait_for_dependencies(state);
  267. drm_atomic_helper_commit_modeset_disables(dev, state);
  268. vc4_ctm_commit(vc4, state);
  269. if (vc4->hvs->hvs5)
  270. vc5_hvs_pv_muxing_commit(vc4, state);
  271. else
  272. vc4_hvs_pv_muxing_commit(vc4, state);
  273. drm_atomic_helper_commit_planes(dev, state, 0);
  274. drm_atomic_helper_commit_modeset_enables(dev, state);
  275. drm_atomic_helper_fake_vblank(state);
  276. drm_atomic_helper_commit_hw_done(state);
  277. drm_atomic_helper_wait_for_flip_done(dev, state);
  278. drm_atomic_helper_cleanup_planes(dev, state);
  279. drm_atomic_helper_commit_cleanup_done(state);
  280. if (vc4->hvs->hvs5)
  281. clk_set_min_rate(hvs->core_clk, 0);
  282. drm_atomic_state_put(state);
  283. up(&vc4->async_modeset);
  284. }
  285. static void commit_work(struct work_struct *work)
  286. {
  287. struct drm_atomic_state *state = container_of(work,
  288. struct drm_atomic_state,
  289. commit_work);
  290. vc4_atomic_complete_commit(state);
  291. }
  292. /**
  293. * vc4_atomic_commit - commit validated state object
  294. * @dev: DRM device
  295. * @state: the driver state object
  296. * @nonblock: nonblocking commit
  297. *
  298. * This function commits a with drm_atomic_helper_check() pre-validated state
  299. * object. This can still fail when e.g. the framebuffer reservation fails. For
  300. * now this doesn't implement asynchronous commits.
  301. *
  302. * RETURNS
  303. * Zero for success or -errno.
  304. */
  305. static int vc4_atomic_commit(struct drm_device *dev,
  306. struct drm_atomic_state *state,
  307. bool nonblock)
  308. {
  309. struct vc4_dev *vc4 = to_vc4_dev(dev);
  310. int ret;
  311. if (state->async_update) {
  312. ret = down_interruptible(&vc4->async_modeset);
  313. if (ret)
  314. return ret;
  315. ret = drm_atomic_helper_prepare_planes(dev, state);
  316. if (ret) {
  317. up(&vc4->async_modeset);
  318. return ret;
  319. }
  320. drm_atomic_helper_async_commit(dev, state);
  321. drm_atomic_helper_cleanup_planes(dev, state);
  322. up(&vc4->async_modeset);
  323. return 0;
  324. }
  325. /* We know for sure we don't want an async update here. Set
  326. * state->legacy_cursor_update to false to prevent
  327. * drm_atomic_helper_setup_commit() from auto-completing
  328. * commit->flip_done.
  329. */
  330. state->legacy_cursor_update = false;
  331. ret = drm_atomic_helper_setup_commit(state, nonblock);
  332. if (ret)
  333. return ret;
  334. INIT_WORK(&state->commit_work, commit_work);
  335. ret = down_interruptible(&vc4->async_modeset);
  336. if (ret)
  337. return ret;
  338. ret = drm_atomic_helper_prepare_planes(dev, state);
  339. if (ret) {
  340. up(&vc4->async_modeset);
  341. return ret;
  342. }
  343. if (!nonblock) {
  344. ret = drm_atomic_helper_wait_for_fences(dev, state, true);
  345. if (ret) {
  346. drm_atomic_helper_cleanup_planes(dev, state);
  347. up(&vc4->async_modeset);
  348. return ret;
  349. }
  350. }
  351. /*
  352. * This is the point of no return - everything below never fails except
  353. * when the hw goes bonghits. Which means we can commit the new state on
  354. * the software side now.
  355. */
  356. BUG_ON(drm_atomic_helper_swap_state(state, false) < 0);
  357. /*
  358. * Everything below can be run asynchronously without the need to grab
  359. * any modeset locks at all under one condition: It must be guaranteed
  360. * that the asynchronous work has either been cancelled (if the driver
  361. * supports it, which at least requires that the framebuffers get
  362. * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
  363. * before the new state gets committed on the software side with
  364. * drm_atomic_helper_swap_state().
  365. *
  366. * This scheme allows new atomic state updates to be prepared and
  367. * checked in parallel to the asynchronous completion of the previous
  368. * update. Which is important since compositors need to figure out the
  369. * composition of the next frame right after having submitted the
  370. * current layout.
  371. */
  372. drm_atomic_state_get(state);
  373. if (nonblock)
  374. queue_work(system_unbound_wq, &state->commit_work);
  375. else
  376. vc4_atomic_complete_commit(state);
  377. return 0;
  378. }
  379. static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev,
  380. struct drm_file *file_priv,
  381. const struct drm_mode_fb_cmd2 *mode_cmd)
  382. {
  383. struct drm_mode_fb_cmd2 mode_cmd_local;
  384. /* If the user didn't specify a modifier, use the
  385. * vc4_set_tiling_ioctl() state for the BO.
  386. */
  387. if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) {
  388. struct drm_gem_object *gem_obj;
  389. struct vc4_bo *bo;
  390. gem_obj = drm_gem_object_lookup(file_priv,
  391. mode_cmd->handles[0]);
  392. if (!gem_obj) {
  393. DRM_DEBUG("Failed to look up GEM BO %d\n",
  394. mode_cmd->handles[0]);
  395. return ERR_PTR(-ENOENT);
  396. }
  397. bo = to_vc4_bo(gem_obj);
  398. mode_cmd_local = *mode_cmd;
  399. if (bo->t_format) {
  400. mode_cmd_local.modifier[0] =
  401. DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED;
  402. } else {
  403. mode_cmd_local.modifier[0] = DRM_FORMAT_MOD_NONE;
  404. }
  405. drm_gem_object_put(gem_obj);
  406. mode_cmd = &mode_cmd_local;
  407. }
  408. return drm_gem_fb_create(dev, file_priv, mode_cmd);
  409. }
  410. /* Our CTM has some peculiar limitations: we can only enable it for one CRTC
  411. * at a time and the HW only supports S0.9 scalars. To account for the latter,
  412. * we don't allow userland to set a CTM that we have no hope of approximating.
  413. */
  414. static int
  415. vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
  416. {
  417. struct vc4_dev *vc4 = to_vc4_dev(dev);
  418. struct vc4_ctm_state *ctm_state = NULL;
  419. struct drm_crtc *crtc;
  420. struct drm_crtc_state *old_crtc_state, *new_crtc_state;
  421. struct drm_color_ctm *ctm;
  422. int i;
  423. for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
  424. /* CTM is being disabled. */
  425. if (!new_crtc_state->ctm && old_crtc_state->ctm) {
  426. ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
  427. if (IS_ERR(ctm_state))
  428. return PTR_ERR(ctm_state);
  429. ctm_state->fifo = 0;
  430. }
  431. }
  432. for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
  433. if (new_crtc_state->ctm == old_crtc_state->ctm)
  434. continue;
  435. if (!ctm_state) {
  436. ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
  437. if (IS_ERR(ctm_state))
  438. return PTR_ERR(ctm_state);
  439. }
  440. /* CTM is being enabled or the matrix changed. */
  441. if (new_crtc_state->ctm) {
  442. struct vc4_crtc_state *vc4_crtc_state =
  443. to_vc4_crtc_state(new_crtc_state);
  444. /* fifo is 1-based since 0 disables CTM. */
  445. int fifo = vc4_crtc_state->assigned_channel + 1;
  446. /* Check userland isn't trying to turn on CTM for more
  447. * than one CRTC at a time.
  448. */
  449. if (ctm_state->fifo && ctm_state->fifo != fifo) {
  450. DRM_DEBUG_DRIVER("Too many CTM configured\n");
  451. return -EINVAL;
  452. }
  453. /* Check we can approximate the specified CTM.
  454. * We disallow scalars |c| > 1.0 since the HW has
  455. * no integer bits.
  456. */
  457. ctm = new_crtc_state->ctm->data;
  458. for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) {
  459. u64 val = ctm->matrix[i];
  460. val &= ~BIT_ULL(63);
  461. if (val > BIT_ULL(32))
  462. return -EINVAL;
  463. }
  464. ctm_state->fifo = fifo;
  465. ctm_state->ctm = ctm;
  466. }
  467. }
  468. return 0;
  469. }
  470. static int vc4_load_tracker_atomic_check(struct drm_atomic_state *state)
  471. {
  472. struct drm_plane_state *old_plane_state, *new_plane_state;
  473. struct vc4_dev *vc4 = to_vc4_dev(state->dev);
  474. struct vc4_load_tracker_state *load_state;
  475. struct drm_private_state *priv_state;
  476. struct drm_plane *plane;
  477. int i;
  478. if (!vc4->load_tracker_available)
  479. return 0;
  480. priv_state = drm_atomic_get_private_obj_state(state,
  481. &vc4->load_tracker);
  482. if (IS_ERR(priv_state))
  483. return PTR_ERR(priv_state);
  484. load_state = to_vc4_load_tracker_state(priv_state);
  485. for_each_oldnew_plane_in_state(state, plane, old_plane_state,
  486. new_plane_state, i) {
  487. struct vc4_plane_state *vc4_plane_state;
  488. if (old_plane_state->fb && old_plane_state->crtc) {
  489. vc4_plane_state = to_vc4_plane_state(old_plane_state);
  490. load_state->membus_load -= vc4_plane_state->membus_load;
  491. load_state->hvs_load -= vc4_plane_state->hvs_load;
  492. }
  493. if (new_plane_state->fb && new_plane_state->crtc) {
  494. vc4_plane_state = to_vc4_plane_state(new_plane_state);
  495. load_state->membus_load += vc4_plane_state->membus_load;
  496. load_state->hvs_load += vc4_plane_state->hvs_load;
  497. }
  498. }
  499. /* Don't check the load when the tracker is disabled. */
  500. if (!vc4->load_tracker_enabled)
  501. return 0;
  502. /* The absolute limit is 2Gbyte/sec, but let's take a margin to let
  503. * the system work when other blocks are accessing the memory.
  504. */
  505. if (load_state->membus_load > SZ_1G + SZ_512M)
  506. return -ENOSPC;
  507. /* HVS clock is supposed to run @ 250Mhz, let's take a margin and
  508. * consider the maximum number of cycles is 240M.
  509. */
  510. if (load_state->hvs_load > 240000000ULL)
  511. return -ENOSPC;
  512. return 0;
  513. }
  514. static struct drm_private_state *
  515. vc4_load_tracker_duplicate_state(struct drm_private_obj *obj)
  516. {
  517. struct vc4_load_tracker_state *state;
  518. state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
  519. if (!state)
  520. return NULL;
  521. __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
  522. return &state->base;
  523. }
  524. static void vc4_load_tracker_destroy_state(struct drm_private_obj *obj,
  525. struct drm_private_state *state)
  526. {
  527. struct vc4_load_tracker_state *load_state;
  528. load_state = to_vc4_load_tracker_state(state);
  529. kfree(load_state);
  530. }
  531. static const struct drm_private_state_funcs vc4_load_tracker_state_funcs = {
  532. .atomic_duplicate_state = vc4_load_tracker_duplicate_state,
  533. .atomic_destroy_state = vc4_load_tracker_destroy_state,
  534. };
  535. static void vc4_load_tracker_obj_fini(struct drm_device *dev, void *unused)
  536. {
  537. struct vc4_dev *vc4 = to_vc4_dev(dev);
  538. if (!vc4->load_tracker_available)
  539. return;
  540. drm_atomic_private_obj_fini(&vc4->load_tracker);
  541. }
  542. static int vc4_load_tracker_obj_init(struct vc4_dev *vc4)
  543. {
  544. struct vc4_load_tracker_state *load_state;
  545. if (!vc4->load_tracker_available)
  546. return 0;
  547. load_state = kzalloc(sizeof(*load_state), GFP_KERNEL);
  548. if (!load_state)
  549. return -ENOMEM;
  550. drm_atomic_private_obj_init(&vc4->base, &vc4->load_tracker,
  551. &load_state->base,
  552. &vc4_load_tracker_state_funcs);
  553. return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, NULL);
  554. }
  555. static struct drm_private_state *
  556. vc4_hvs_channels_duplicate_state(struct drm_private_obj *obj)
  557. {
  558. struct vc4_hvs_state *old_state = to_vc4_hvs_state(obj->state);
  559. struct vc4_hvs_state *state;
  560. state = kzalloc(sizeof(*state), GFP_KERNEL);
  561. if (!state)
  562. return NULL;
  563. __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
  564. state->unassigned_channels = old_state->unassigned_channels;
  565. return &state->base;
  566. }
  567. static void vc4_hvs_channels_destroy_state(struct drm_private_obj *obj,
  568. struct drm_private_state *state)
  569. {
  570. struct vc4_hvs_state *hvs_state = to_vc4_hvs_state(state);
  571. kfree(hvs_state);
  572. }
  573. static const struct drm_private_state_funcs vc4_hvs_state_funcs = {
  574. .atomic_duplicate_state = vc4_hvs_channels_duplicate_state,
  575. .atomic_destroy_state = vc4_hvs_channels_destroy_state,
  576. };
  577. static void vc4_hvs_channels_obj_fini(struct drm_device *dev, void *unused)
  578. {
  579. struct vc4_dev *vc4 = to_vc4_dev(dev);
  580. drm_atomic_private_obj_fini(&vc4->hvs_channels);
  581. }
  582. static int vc4_hvs_channels_obj_init(struct vc4_dev *vc4)
  583. {
  584. struct vc4_hvs_state *state;
  585. state = kzalloc(sizeof(*state), GFP_KERNEL);
  586. if (!state)
  587. return -ENOMEM;
  588. state->unassigned_channels = GENMASK(HVS_NUM_CHANNELS - 1, 0);
  589. drm_atomic_private_obj_init(&vc4->base, &vc4->hvs_channels,
  590. &state->base,
  591. &vc4_hvs_state_funcs);
  592. return drmm_add_action_or_reset(&vc4->base, vc4_hvs_channels_obj_fini, NULL);
  593. }
  594. /*
  595. * The BCM2711 HVS has up to 7 outputs connected to the pixelvalves and
  596. * the TXP (and therefore all the CRTCs found on that platform).
  597. *
  598. * The naive (and our initial) implementation would just iterate over
  599. * all the active CRTCs, try to find a suitable FIFO, and then remove it
  600. * from the pool of available FIFOs. However, there are a few corner
  601. * cases that need to be considered:
  602. *
  603. * - When running in a dual-display setup (so with two CRTCs involved),
  604. * we can update the state of a single CRTC (for example by changing
  605. * its mode using xrandr under X11) without affecting the other. In
  606. * this case, the other CRTC wouldn't be in the state at all, so we
  607. * need to consider all the running CRTCs in the DRM device to assign
  608. * a FIFO, not just the one in the state.
  609. *
  610. * - To fix the above, we can't use drm_atomic_get_crtc_state on all
  611. * enabled CRTCs to pull their CRTC state into the global state, since
  612. * a page flip would start considering their vblank to complete. Since
  613. * we don't have a guarantee that they are actually active, that
  614. * vblank might never happen, and shouldn't even be considered if we
  615. * want to do a page flip on a single CRTC. That can be tested by
  616. * doing a modetest -v first on HDMI1 and then on HDMI0.
  617. *
  618. * - Since we need the pixelvalve to be disabled and enabled back when
  619. * the FIFO is changed, we should keep the FIFO assigned for as long
  620. * as the CRTC is enabled, only considering it free again once that
  621. * CRTC has been disabled. This can be tested by booting X11 on a
  622. * single display, and changing the resolution down and then back up.
  623. */
  624. static int vc4_pv_muxing_atomic_check(struct drm_device *dev,
  625. struct drm_atomic_state *state)
  626. {
  627. struct vc4_hvs_state *hvs_new_state;
  628. struct drm_crtc_state *old_crtc_state, *new_crtc_state;
  629. struct drm_crtc *crtc;
  630. unsigned int i;
  631. hvs_new_state = vc4_hvs_get_global_state(state);
  632. if (!hvs_new_state)
  633. return -EINVAL;
  634. for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
  635. struct vc4_crtc_state *old_vc4_crtc_state =
  636. to_vc4_crtc_state(old_crtc_state);
  637. struct vc4_crtc_state *new_vc4_crtc_state =
  638. to_vc4_crtc_state(new_crtc_state);
  639. struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  640. unsigned int matching_channels;
  641. /* Nothing to do here, let's skip it */
  642. if (old_crtc_state->enable == new_crtc_state->enable)
  643. continue;
  644. /* Muxing will need to be modified, mark it as such */
  645. new_vc4_crtc_state->update_muxing = true;
  646. /* If we're disabling our CRTC, we put back our channel */
  647. if (!new_crtc_state->enable) {
  648. hvs_new_state->unassigned_channels |= BIT(old_vc4_crtc_state->assigned_channel);
  649. new_vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
  650. continue;
  651. }
  652. /*
  653. * The problem we have to solve here is that we have
  654. * up to 7 encoders, connected to up to 6 CRTCs.
  655. *
  656. * Those CRTCs, depending on the instance, can be
  657. * routed to 1, 2 or 3 HVS FIFOs, and we need to set
  658. * the change the muxing between FIFOs and outputs in
  659. * the HVS accordingly.
  660. *
  661. * It would be pretty hard to come up with an
  662. * algorithm that would generically solve
  663. * this. However, the current routing trees we support
  664. * allow us to simplify a bit the problem.
  665. *
  666. * Indeed, with the current supported layouts, if we
  667. * try to assign in the ascending crtc index order the
  668. * FIFOs, we can't fall into the situation where an
  669. * earlier CRTC that had multiple routes is assigned
  670. * one that was the only option for a later CRTC.
  671. *
  672. * If the layout changes and doesn't give us that in
  673. * the future, we will need to have something smarter,
  674. * but it works so far.
  675. */
  676. matching_channels = hvs_new_state->unassigned_channels & vc4_crtc->data->hvs_available_channels;
  677. if (matching_channels) {
  678. unsigned int channel = ffs(matching_channels) - 1;
  679. new_vc4_crtc_state->assigned_channel = channel;
  680. hvs_new_state->unassigned_channels &= ~BIT(channel);
  681. } else {
  682. return -EINVAL;
  683. }
  684. }
  685. return 0;
  686. }
  687. static int
  688. vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
  689. {
  690. int ret;
  691. ret = vc4_pv_muxing_atomic_check(dev, state);
  692. if (ret)
  693. return ret;
  694. ret = vc4_ctm_atomic_check(dev, state);
  695. if (ret < 0)
  696. return ret;
  697. ret = drm_atomic_helper_check(dev, state);
  698. if (ret)
  699. return ret;
  700. return vc4_load_tracker_atomic_check(state);
  701. }
  702. static const struct drm_mode_config_funcs vc4_mode_funcs = {
  703. .atomic_check = vc4_atomic_check,
  704. .atomic_commit = vc4_atomic_commit,
  705. .fb_create = vc4_fb_create,
  706. };
  707. int vc4_kms_load(struct drm_device *dev)
  708. {
  709. struct vc4_dev *vc4 = to_vc4_dev(dev);
  710. bool is_vc5 = of_device_is_compatible(dev->dev->of_node,
  711. "brcm,bcm2711-vc5");
  712. int ret;
  713. if (!is_vc5) {
  714. vc4->load_tracker_available = true;
  715. /* Start with the load tracker enabled. Can be
  716. * disabled through the debugfs load_tracker file.
  717. */
  718. vc4->load_tracker_enabled = true;
  719. }
  720. sema_init(&vc4->async_modeset, 1);
  721. /* Set support for vblank irq fast disable, before drm_vblank_init() */
  722. dev->vblank_disable_immediate = true;
  723. dev->irq_enabled = true;
  724. ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
  725. if (ret < 0) {
  726. dev_err(dev->dev, "failed to initialize vblank\n");
  727. return ret;
  728. }
  729. if (is_vc5) {
  730. dev->mode_config.max_width = 7680;
  731. dev->mode_config.max_height = 7680;
  732. } else {
  733. dev->mode_config.max_width = 2048;
  734. dev->mode_config.max_height = 2048;
  735. }
  736. dev->mode_config.funcs = &vc4_mode_funcs;
  737. dev->mode_config.preferred_depth = 24;
  738. dev->mode_config.async_page_flip = true;
  739. dev->mode_config.allow_fb_modifiers = true;
  740. ret = vc4_ctm_obj_init(vc4);
  741. if (ret)
  742. return ret;
  743. ret = vc4_load_tracker_obj_init(vc4);
  744. if (ret)
  745. return ret;
  746. ret = vc4_hvs_channels_obj_init(vc4);
  747. if (ret)
  748. return ret;
  749. drm_mode_config_reset(dev);
  750. drm_kms_helper_poll_init(dev);
  751. return 0;
  752. }